diff options
author | Nick Clifton <nickc@redhat.com> | 2019-09-10 15:20:58 +0100 |
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committer | Nick Clifton <nickc@redhat.com> | 2019-09-10 15:20:58 +0100 |
commit | aebcfb76fc165795e67917cb67cf985c4dfdc577 (patch) | |
tree | 3c4539161437c15ad09750a9cfc7e0696f3a2986 /gas | |
parent | efd0b3103f0fbbaa8dac86d82263b46a88b27461 (diff) | |
download | gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.zip gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.tar.gz gdb-aebcfb76fc165795e67917cb67cf985c4dfdc577.tar.bz2 |
Enhance the disassembler so that it will reliably determine whether a reloc applies to the middle of the next insn.
PR 24907
binutils* objdump.c (null_print): New function.
(disassemble_bytes): Delete previous_octets local and replace with
a test of the max_reloc_offset_into_insn field of the
bfd_arch_info structure. If a reloc is a potential match for the
next insn, then perform a dummy disassembly in order to calculate
its real length.
bfd * archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn
field.
(bfd_default_arch_struct): Initialise the new field.
* bfd-in2.h: Regenerate.
* cpu-aarch64.c: Initialise the new field.
* cpu-alpha.c: Likewise.
* cpu-arc.c: Likewise.
* cpu-arm.c: Likewise.
* cpu-avr.c: Likewise.
* cpu-bfin.c: Likewise.
* cpu-bpf.c: Likewise.
* cpu-cr16.c: Likewise.
* cpu-cr16c.c: Likewise.
* cpu-cris.c: Likewise.
* cpu-crx.c: Likewise.
* cpu-csky.c: Likewise.
* cpu-d10v.c: Likewise.
* cpu-d30v.c: Likewise.
* cpu-dlx.c: Likewise.
* cpu-epiphany.c: Likewise.
* cpu-fr30.c: Likewise.
* cpu-frv.c: Likewise.
* cpu-ft32.c: Likewise.
* cpu-h8300.c: Likewise.
* cpu-hppa.c: Likewise.
* cpu-i386.c: Likewise.
* cpu-ia64.c: Likewise.
* cpu-iamcu.c: Likewise.
* cpu-ip2k.c: Likewise.
* cpu-iq2000.c: Likewise.
* cpu-k1om.c: Likewise.
* cpu-l1om.c: Likewise.
* cpu-lm32.c: Likewise.
* cpu-m10200.c: Likewise.
* cpu-m10300.c: Likewise.
* cpu-m32c.c: Likewise.
* cpu-m32r.c: Likewise.
* cpu-m68hc11.c: Likewise.
* cpu-m68hc12.c: Likewise.
* cpu-m68k.c: Likewise.
* cpu-m9s12x.c: Likewise.
* cpu-m9s12xg.c: Likewise.
* cpu-mcore.c: Likewise.
* cpu-mep.c: Likewise.
* cpu-metag.c: Likewise.
* cpu-microblaze.c: Likewise.
* cpu-mips.c: Likewise.
* cpu-mmix.c: Likewise.
* cpu-moxie.c: Likewise.
* cpu-msp430.c: Likewise.
* cpu-mt.c: Likewise.
* cpu-nds32.c: Likewise.
* cpu-nfp.c: Likewise.
* cpu-nios2.c: Likewise.
* cpu-ns32k.c: Likewise.
* cpu-or1k.c: Likewise.
* cpu-pdp11.c: Likewise.
* cpu-pj.c: Likewise.
* cpu-plugin.c: Likewise.
* cpu-powerpc.c: Likewise.
* cpu-pru.c: Likewise.
* cpu-riscv.c: Likewise.
* cpu-rl78.c: Likewise.
* cpu-rs6000.c: Likewise.
* cpu-rx.c: Likewise.
* cpu-s12z.c: Likewise.
* cpu-s390.c: Likewise.
* cpu-score.c: Likewise.
* cpu-sh.c: Likewise.
* cpu-sparc.c: Likewise.
* cpu-spu.c: Likewise.
* cpu-tic30.c: Likewise.
* cpu-tic4x.c: Likewise.
* cpu-tic54x.c: Likewise.
* cpu-tic6x.c: Likewise.
* cpu-tic80.c: Likewise.
* cpu-tilegx.c: Likewise.
* cpu-tilepro.c: Likewise.
* cpu-v850.c: Likewise.
* cpu-v850_rh850.c: Likewise.
* cpu-vax.c: Likewise.
* cpu-visium.c: Likewise.
* cpu-wasm32.c: Likewise.
* cpu-xc16x.c: Likewise.
* cpu-xgate.c: Likewise.
* cpu-xstormy16.c: Likewise.
* cpu-xtensa.c: Likewise.
* cpu-z80.c: Likewise.
* cpu-z8k.c: Likewise.
gas * testsuite/gas/arm/pr24907.s: New test.
* testsuite/gas/arm/pr24907.d: Expected disassembly.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/pr24907.d | 19 | ||||
-rw-r--r-- | gas/testsuite/gas/arm/pr24907.s | 16 |
3 files changed, 41 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 9c484d3..444bd16 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2019-09-10 Nick Clifton <nickc@redhat.com> + + PR 24907 + * testsuite/gas/arm/pr24907.s: New test. + * testsuite/gas/arm/pr24907.d: Expected disassembly. + 2019-09-09 Phil Blundell <pb@pbcl.net> binutils 2.33 branch created. diff --git a/gas/testsuite/gas/arm/pr24907.d b/gas/testsuite/gas/arm/pr24907.d new file mode 100644 index 0000000..8268d4b --- /dev/null +++ b/gas/testsuite/gas/arm/pr24907.d @@ -0,0 +1,19 @@ +# name: Disassembling variable width insns with relocs (PR 24907) +# as: +# objdump: -d +# This test is only valid on ELF based ports. +#notarget: *-*-pe *-*-wince *-*-vxworks + +.*: +file format .*arm.* + +Disassembly of section \.text: + +0+000 <foo>: + 0: 46c0 nop ; .* + 2: f7ff fffe bl 0 <log_func> + 6: e002 b\.n e <func\+0x2> + 8: f7ff fffe bl c <func> + +0+000c <func>: + c: 46c0 nop ; .* + e: 46c0 nop ; .* diff --git a/gas/testsuite/gas/arm/pr24907.s b/gas/testsuite/gas/arm/pr24907.s new file mode 100644 index 0000000..ee8114e --- /dev/null +++ b/gas/testsuite/gas/arm/pr24907.s @@ -0,0 +1,16 @@ + .syntax unified + .text + .thumb + +.global foo +foo: + nop + bl log_func + b.n .L1 + bl func + +.global func +func: + nop +.L1: + nop |