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2018-11-12[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Ex...Sudakshina Das7-0/+120
2018-11-12[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-ASudakshina Das3-0/+10
2018-11-09S/390: Fix optional operand handling after memory addressesAndreas Krebbel4-24/+42
2018-11-09PowerPC, don't use bfd reloc howto in md_assembleAlan Modra2-11/+255
2018-11-07Add updated French and Portuguese translations.Nick Clifton2-2994/+3076
2018-11-07rx: Add target rx-*-linux.Yoshinori Sato5-2/+13
2018-11-06[arm] fix testsuite breakage on pe-coffMatthew Malcomson2-2/+8
2018-11-06[arm] Check for neon and condition in vcvt.f16.f32Matthew Malcomson7-14/+40
2018-11-06PowerPC instruction mask checksAlan Modra2-14/+29
2018-11-06PowerPC instruction operand flag validationAlan Modra2-0/+14
2018-11-06x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+10
2018-11-06x86: correctly handle VMOVD with EVEX.W set outside of 64-bit modeJan Beulich4-0/+20
2018-11-06x86: correctly handle KMOVD with VEX.W set outside of 64-bit modeJan Beulich3-0/+9
2018-11-06x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich8-0/+60
2018-11-06x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich13-31/+241
2018-11-06x86: fix various non-LIG templatesJan Beulich10-0/+433
2018-11-06x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich5-2/+51
2018-11-06x86: add more VexWIGJan Beulich9-18/+70
2018-11-05Correct ChangeLog entries for PR gas/23854 commitH.J. Lu1-1/+1
2018-11-05x86: Disable GOT relaxation with data prefixH.J. Lu3-7/+15
2018-11-01Fix ld action in run_dump_testThomas Preud'homme2-0/+13
2018-10-31[GAS][ARM] Fix ARMv8.1 AdvSIMD testismAndre Vieira2-1/+4
2018-10-31[GAS][ARM] Fix UDF testismAndre Vieira2-23/+23
2018-10-31[GAS][ARM] Fix failing Armv1 testAndre Vieira2-18/+23
2018-10-29Move struc-symbol.h to symbols.cAlan Modra31-326/+353
2018-10-28Correct ChangeLogAlan Modra1-1/+1
2018-10-28PR23837, Segmentation fault in resolve_symbol_valueAlan Modra2-2/+8
2018-10-23S/390: Support vector alignment hintsAndreas Krebbel3-0/+31
2018-10-23S12Z: Handle 16 bit fixups which are constant.John Darrington2-0/+8
2018-10-22gas simple-forward testAlan Modra5-2/+36
2018-10-22Apply alpha BFD_RELOC_8 fixupsAlan Modra4-4/+15
2018-10-22PR23040, .uleb128 directive doesn't accept some valid expressionsAlan Modra4-20/+48
2018-10-20PR23800, .eqv doesn't always defer expression evaluationAlan Modra6-1/+55
2018-10-19Arm: Skip new binary decode tests on pe targetsTamar Christina3-2/+7
2018-10-19Arm: Fix disassembler crashing on -b binary when thumb file and thumb not for...Tamar Christina4-0/+17
2018-10-19This set of changes clarifies the conditions for the R5900 short loop fix and...Fredrik Noring4-10/+71
2018-10-16AArch64: Fix error checking for SIMD udot (by element)Matthew Malcomson4-0/+28
2018-10-15BFD_INIT_MAGICAlan Modra2-1/+8
2018-10-11x86: add {,V}MOVQ cases to xmmword testJan Beulich3-0/+19
2018-10-10x86: fold Size{16,32,64} template attributesJan Beulich2-6/+11
2018-10-09[PATCH, BINUTULS, AARCH64, 9/9] Add SSBS to MSR/MRSSudakshina Das10-0/+220
2018-10-09[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registersSudakshina Das4-0/+25
2018-10-09[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instructionSudakshina Das7-4/+95
2018-10-09[PATCH, BINUTILS, AARCH64, 6/9] Add Random number instructionsSudakshina Das6-1/+19
2018-10-09[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instructionSudakshina Das4-0/+9
2018-10-09[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructionsSudakshina Das9-0/+78
2018-10-09[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB for ARMv8.5-ASudakshina Das6-0/+40
2018-10-09[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-ASudakshina Das3-0/+55
2018-10-09[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5-a and related internal fea...Sudakshina Das3-1/+9
2018-10-05x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu5-0/+11
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