x86: fix various non-LIG templates

Quite a few templates were marked LIG while really the insns aren't.
Introduce descriptive shorthands once again, instead of continuing to
use the less legible original forms.

10 files changed, 433 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 673e8d7..c412458 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,18 @@
 2018-11-06  Jan Beulich  <jbeulich@suse.com>
 
+	* testsuite/gas/i386/evex-lig-2.s,
+	testsuite/gas/i386/x86-64-evex-lig-2.s: Add extract and insert
+	cases.
+	* testsuite/gas/i386/evex-lig-2.d,
+	testsuite/gas/i386/x86-64-evex-lig-2.d: Adjust expectations.
+	* testsuite/gas/i386/vex-lig-2.s,
+	testsuite/gas/i386/vex-lig-2.d,
+	testsuite/gas/i386/x86-64-vex-lig-2.s,
+	testsuite/gas/i386/x86-64-vex-lig-2.d: New.
+	* testsuite/gas/i386/i386.exp: Run new tests.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
 	* testsuite/gas/i386/pseudos.s,
 	testsuite/gas/i386/x86-64-pseudos.s: Add pextrw / vpextrw cases.
 	* testsuite/gas/i386/pseudos.d,
diff --git a/gas/testsuite/gas/i386/evex-lig-2.d b/gas/testsuite/gas/i386/evex-lig-2.d
index dddcc47..c1f9f9f 100644
--- a/gas/testsuite/gas/i386/evex-lig-2.d
+++ b/gas/testsuite/gas/i386/evex-lig-2.d
@@ -15,4 +15,21 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 f1 fd 08 d6 21    	vmovq  %xmm4,\(%ecx\)
  +[a-f0-9]+:	62 f1 fe 08 7e 21    	vmovq  \(%ecx\),%xmm4
  +[a-f0-9]+:	62 f1 fe 08 7e f4    	vmovq  %xmm4,%xmm6
+ +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 17 00 00 	vextractps \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 14 00 00 	vpextrb \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 16 00 00 	vpextrd \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 21 00 00 	vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 00 00 	vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 00 00 	vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
 #pass
diff --git a/gas/testsuite/gas/i386/evex-lig-2.s b/gas/testsuite/gas/i386/evex-lig-2.s
index 040f7fe..f69dece 100644
--- a/gas/testsuite/gas/i386/evex-lig-2.s
+++ b/gas/testsuite/gas/i386/evex-lig-2.s
@@ -12,3 +12,28 @@ _start:
 	{evex} vmovq (%ecx),%xmm4
 
 	{evex} vmovq %xmm4,%xmm6
+
+	{evex} vextractps $0, %xmm0, %eax
+	{evex} vextractps $0, %xmm0, (%eax)
+
+	{evex} vpextrb $0, %xmm0, %eax
+	{evex} vpextrb $0, %xmm0, (%eax)
+
+	{evex} vpextrw $0, %xmm0, %eax
+	{evex} {store} vpextrw $0, %xmm0, %eax
+	{evex} vpextrw $0, %xmm0, (%eax)
+
+	{evex} vpextrd $0, %xmm0, %eax
+	{evex} vpextrd $0, %xmm0, (%eax)
+
+	{evex} vinsertps $0, %xmm0, %xmm0, %xmm0
+	{evex} vinsertps $0, (%eax), %xmm0, %xmm0
+
+	{evex} vpinsrb $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrb $0, (%eax), %xmm0, %xmm0
+
+	{evex} vpinsrw $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrw $0, (%eax), %xmm0, %xmm0
+
+	{evex} vpinsrd $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrd $0, (%eax), %xmm0, %xmm0
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 01be072..60439eb 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -216,6 +216,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "avx-gather-intel"
     run_dump_test "avx-wig"
     run_dump_test "avx2-wig"
+    run_dump_test "vex-lig-2"
     run_dump_test "avx512f"
     run_dump_test "avx512f-intel"
     run_dump_test "avx512f-opts"
@@ -739,6 +740,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-avx-gather-intel"
     run_dump_test "x86-64-avx-wig"
     run_dump_test "x86-64-avx2-wig"
+    run_dump_test "x86-64-vex-lig-2"
     run_dump_test "x86-64-avx512f"
     run_dump_test "x86-64-avx512f-intel"
     run_dump_test "x86-64-avx512f-opts"
diff --git a/gas/testsuite/gas/i386/vex-lig-2.d b/gas/testsuite/gas/i386/vex-lig-2.d
new file mode 100644
index 0000000..458df17
--- /dev/null
+++ b/gas/testsuite/gas/i386/vex-lig-2.d
@@ -0,0 +1,74 @@
+#as: -mavxscalar=256
+#objdump: -dw
+#name: i386 VEX non-LIG insns with -mavxscalar=256
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	c5 f9 6e c0          	vmovd  %eax,%xmm0
+ +[a-f0-9]+:	c5 f9 6e 00          	vmovd  \(%eax\),%xmm0
+ +[a-f0-9]+:	c4 e1 79 6e c0       	vmovd  %eax,%xmm0
+ +[a-f0-9]+:	c4 e1 79 6e 00       	vmovd  \(%eax\),%xmm0
+ +[a-f0-9]+:	c5 f9 7e c0          	vmovd  %xmm0,%eax
+ +[a-f0-9]+:	c5 f9 7e 00          	vmovd  %xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e1 79 7e c0       	vmovd  %xmm0,%eax
+ +[a-f0-9]+:	c4 e1 79 7e 00       	vmovd  %xmm0,\(%eax\)
+ +[a-f0-9]+:	c5 fa 7e c0          	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c5 fa 7e 00          	vmovq  \(%eax\),%xmm0
+ +[a-f0-9]+:	c4 e1 7a 7e c0       	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 7a 7e 00       	vmovq  \(%eax\),%xmm0
+ +[a-f0-9]+:	c5 f9 d6 c0          	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 d6 00          	vmovq  %xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e1 79 d6 c0       	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 d6 00       	vmovq  %xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e3 79 17 c0 00    	vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 17 00 00    	vextractps \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e3 79 14 c0 00    	vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 14 00 00    	vpextrb \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	c5 f9 c5 c0 00       	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e1 79 c5 c0 00    	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 15 c0 00    	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 15 00 00    	vpextrw \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e3 79 16 c0 00    	vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 16 00 00    	vpextrd \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	c4 e3 79 21 c0 00    	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 21 00 00    	vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 20 c0 00    	vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 20 00 00    	vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 c4 c0 00       	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 c4 00 00       	vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 c4 c0 00    	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 c4 00 00    	vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 22 c0 00    	vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 22 00 00    	vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f8 ae 10          	vldmxcsr \(%eax\)
+ +[a-f0-9]+:	c5 f8 ae 18          	vstmxcsr \(%eax\)
+ +[a-f0-9]+:	c4 e1 78 ae 10       	vldmxcsr \(%eax\)
+ +[a-f0-9]+:	c4 e1 78 ae 18       	vstmxcsr \(%eax\)
+ +[a-f0-9]+:	c4 e2 78 f2 00       	andn   \(%eax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 78 f7 00       	bextr  %eax,\(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 10       	blsmsk \(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 08       	blsr   \(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f5 00       	bzhi   %eax,\(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 7b f6 00       	mulx   \(%eax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 7b f5 00       	pdep   \(%eax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 7a f5 00       	pext   \(%eax\),%eax,%eax
+ +[a-f0-9]+:	c4 e3 7b f0 00 00    	rorx   \$0x0,\(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 7a f7 00       	sarx   %eax,\(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 79 f7 00       	shlx   %eax,\(%eax\),%eax
+ +[a-f0-9]+:	c4 e2 7b f7 00       	shrx   %eax,\(%eax\),%eax
+ +[a-f0-9]+:	8f ea 78 10 00 00 00 00 00 	bextr  \$0x0,\(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 08       	blcfill \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 02 30       	blci   \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 28       	blcic  \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 02 08       	blcmsk \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 18       	blcs   \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 10       	blsfill \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 30       	blsic  \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 38       	t1mskc \(%eax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 20       	tzmsk  \(%eax\),%eax
+#pass
diff --git a/gas/testsuite/gas/i386/vex-lig-2.s b/gas/testsuite/gas/i386/vex-lig-2.s
new file mode 100644
index 0000000..dc74d71
--- /dev/null
+++ b/gas/testsuite/gas/i386/vex-lig-2.s
@@ -0,0 +1,83 @@
+# Check VEX non-LIG instructions with with -mavxscalar=256
+
+	.allow_index_reg
+	.text
+_start:
+	       vmovd	%eax, %xmm0
+	       vmovd	(%eax), %xmm0
+	{vex3} vmovd	%eax, %xmm0
+	{vex3} vmovd	(%eax), %xmm0
+
+	       vmovd	%xmm0, %eax
+	       vmovd	%xmm0, (%eax)
+	{vex3} vmovd	%xmm0, %eax
+	{vex3} vmovd	%xmm0, (%eax)
+
+	       vmovq	%xmm0, %xmm0
+	       vmovq	(%eax), %xmm0
+	{vex3} vmovq	%xmm0, %xmm0
+	{vex3} vmovq	(%eax), %xmm0
+
+	{store} vmovq	%xmm0, %xmm0
+	        vmovq	%xmm0, (%eax)
+	{vex3} {store} vmovq %xmm0, %xmm0
+	{vex3} vmovq	%xmm0, (%eax)
+
+	       vextractps $0, %xmm0, %eax
+	       vextractps $0, %xmm0, (%eax)
+
+	       vpextrb $0, %xmm0, %eax
+	       vpextrb $0, %xmm0, (%eax)
+
+	       vpextrw $0, %xmm0, %eax
+	{vex3} vpextrw $0, %xmm0, %eax
+	{store} vpextrw $0, %xmm0, %eax
+	       vpextrw $0, %xmm0, (%eax)
+
+	       vpextrd $0, %xmm0, %eax
+	       vpextrd $0, %xmm0, (%eax)
+
+	       vinsertps $0, %xmm0, %xmm0, %xmm0
+	       vinsertps $0, (%eax), %xmm0, %xmm0
+
+	       vpinsrb $0, %eax, %xmm0, %xmm0
+	       vpinsrb $0, (%eax), %xmm0, %xmm0
+
+	       vpinsrw $0, %eax, %xmm0, %xmm0
+	       vpinsrw $0, (%eax), %xmm0, %xmm0
+	{vex3} vpinsrw $0, %eax, %xmm0, %xmm0
+	{vex3} vpinsrw $0, (%eax), %xmm0, %xmm0
+
+	       vpinsrd $0, %eax, %xmm0, %xmm0
+	       vpinsrd $0, (%eax), %xmm0, %xmm0
+
+	       vldmxcsr (%eax)
+	       vstmxcsr (%eax)
+	{vex3} vldmxcsr (%eax)
+	{vex3} vstmxcsr (%eax)
+
+	andn	(%eax), %eax, %eax
+	bextr	%eax, (%eax), %eax
+	blsi	(%eax), %eax
+	blsmsk	(%eax), %eax
+	blsr	(%eax), %eax
+
+	bzhi	%eax, (%eax), %eax
+	mulx	(%eax), %eax, %eax
+	pdep	(%eax), %eax, %eax
+	pext	(%eax), %eax, %eax
+	rorx	$0, (%eax), %eax
+	sarx	%eax, (%eax), %eax
+	shlx	%eax, (%eax), %eax
+	shrx	%eax, (%eax), %eax
+
+	bextr	$0, (%eax), %eax
+	blcfill	(%eax), %eax
+	blci	(%eax), %eax
+	blcic	(%eax), %eax
+	blcmsk	(%eax), %eax
+	blcs	(%eax), %eax
+	blsfill	(%eax), %eax
+	blsic	(%eax), %eax
+	t1mskc	(%eax), %eax
+	tzmsk	(%eax), %eax
diff --git a/gas/testsuite/gas/i386/x86-64-evex-lig-2.d b/gas/testsuite/gas/i386/x86-64-evex-lig-2.d
index ebdfe9b..ac7bae4 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-lig-2.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-lig-2.d
@@ -17,4 +17,25 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 f1 fd 08 6e 21    	vmovq  \(%rcx\),%xmm4
  +[a-f0-9]+:	62 f1 fd 08 6e e1    	vmovq  %rcx,%xmm4
  +[a-f0-9]+:	62 f1 fe 08 7e f4    	vmovq  %xmm4,%xmm6
+ +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 17 00 00 	vextractps \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 14 00 00 	vpextrb \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 16 00 00 	vpextrd \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 fd 08 16 c0 00 	vpextrq \$0x0,%xmm0,%rax
+ +[a-f0-9]+:	62 f3 fd 08 16 00 00 	vpextrq \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 21 00 00 	vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 00 00 	vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 00 00 	vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 fd 08 22 c0 00 	vpinsrq \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 fd 08 22 00 00 	vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-evex-lig-2.s b/gas/testsuite/gas/i386/x86-64-evex-lig-2.s
index 3261349..9c64f6b 100644
--- a/gas/testsuite/gas/i386/x86-64-evex-lig-2.s
+++ b/gas/testsuite/gas/i386/x86-64-evex-lig-2.s
@@ -13,3 +13,34 @@ _start:
 	{evex} vmovq (%rcx),%xmm4
 	{evex} vmovq %rcx,%xmm4
 	{evex} vmovq %xmm4,%xmm6
+
+	{evex} vextractps $0, %xmm0, %eax
+	{evex} vextractps $0, %xmm0, (%rax)
+
+	{evex} vpextrb $0, %xmm0, %eax
+	{evex} vpextrb $0, %xmm0, (%rax)
+
+	{evex} vpextrw $0, %xmm0, %eax
+	{evex} {store} vpextrw $0, %xmm0, %eax
+	{evex} vpextrw $0, %xmm0, (%rax)
+
+	{evex} vpextrd $0, %xmm0, %eax
+	{evex} vpextrd $0, %xmm0, (%rax)
+
+	{evex} vpextrq $0, %xmm0, %rax
+	{evex} vpextrq $0, %xmm0, (%rax)
+
+	{evex} vinsertps $0, %xmm0, %xmm0, %xmm0
+	{evex} vinsertps $0, (%rax), %xmm0, %xmm0
+
+	{evex} vpinsrb $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrb $0, (%rax), %xmm0, %xmm0
+
+	{evex} vpinsrw $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrw $0, (%rax), %xmm0, %xmm0
+
+	{evex} vpinsrd $0, %eax, %xmm0, %xmm0
+	{evex} vpinsrd $0, (%rax), %xmm0, %xmm0
+
+	{evex} vpinsrq $0, %rax, %xmm0, %xmm0
+	{evex} vpinsrq $0, (%rax), %xmm0, %xmm0
diff --git a/gas/testsuite/gas/i386/x86-64-vex-lig-2.d b/gas/testsuite/gas/i386/x86-64-vex-lig-2.d
new file mode 100644
index 0000000..1c0d9b2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vex-lig-2.d
@@ -0,0 +1,78 @@
+#as: -mavxscalar=256
+#objdump: -dw
+#name: x86-64 VEX non-LIG insns with -mavxscalar=256
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	c5 f9 6e c0          	vmovd  %eax,%xmm0
+ +[a-f0-9]+:	c5 f9 6e 00          	vmovd  \(%rax\),%xmm0
+ +[a-f0-9]+:	c4 e1 79 6e c0       	vmovd  %eax,%xmm0
+ +[a-f0-9]+:	c4 e1 79 6e 00       	vmovd  \(%rax\),%xmm0
+ +[a-f0-9]+:	c5 f9 7e c0          	vmovd  %xmm0,%eax
+ +[a-f0-9]+:	c5 f9 7e 00          	vmovd  %xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e1 79 7e c0       	vmovd  %xmm0,%eax
+ +[a-f0-9]+:	c4 e1 79 7e 00       	vmovd  %xmm0,\(%rax\)
+ +[a-f0-9]+:	c5 fa 7e c0          	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c5 fa 7e 00          	vmovq  \(%rax\),%xmm0
+ +[a-f0-9]+:	c4 e1 7a 7e c0       	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 7a 7e 00       	vmovq  \(%rax\),%xmm0
+ +[a-f0-9]+:	c5 f9 d6 c0          	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 d6 00          	vmovq  %xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e1 79 d6 c0       	vmovq  %xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 d6 00       	vmovq  %xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e3 79 17 c0 00    	vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 17 00 00    	vextractps \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e3 79 14 c0 00    	vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 14 00 00    	vpextrb \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	c5 f9 c5 c0 00       	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e1 79 c5 c0 00    	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 15 c0 00    	vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 15 00 00    	vpextrw \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e3 79 16 c0 00    	vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	c4 e3 79 16 00 00    	vpextrd \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e3 f9 16 c0 00    	vpextrq \$0x0,%xmm0,%rax
+ +[a-f0-9]+:	c4 e3 f9 16 00 00    	vpextrq \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	c4 e3 79 21 c0 00    	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 21 00 00    	vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 20 c0 00    	vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 20 00 00    	vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 c4 c0 00       	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f9 c4 00 00       	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 c4 c0 00    	vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e1 79 c4 00 00    	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 22 c0 00    	vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 79 22 00 00    	vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 f9 22 c0 00    	vpinsrq \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+:	c4 e3 f9 22 00 00    	vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	c5 f8 ae 10          	vldmxcsr \(%rax\)
+ +[a-f0-9]+:	c5 f8 ae 18          	vstmxcsr \(%rax\)
+ +[a-f0-9]+:	c4 e1 78 ae 10       	vldmxcsr \(%rax\)
+ +[a-f0-9]+:	c4 e1 78 ae 18       	vstmxcsr \(%rax\)
+ +[a-f0-9]+:	c4 e2 78 f2 00       	andn   \(%rax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 78 f7 00       	bextr  %eax,\(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 18       	blsi   \(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 10       	blsmsk \(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f3 08       	blsr   \(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 78 f5 00       	bzhi   %eax,\(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 7b f6 00       	mulx   \(%rax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 7b f5 00       	pdep   \(%rax\),%eax,%eax
+ +[a-f0-9]+:	c4 e2 7a f5 00       	pext   \(%rax\),%eax,%eax
+ +[a-f0-9]+:	c4 e3 7b f0 00 00    	rorx   \$0x0,\(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 7a f7 00       	sarx   %eax,\(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 79 f7 00       	shlx   %eax,\(%rax\),%eax
+ +[a-f0-9]+:	c4 e2 7b f7 00       	shrx   %eax,\(%rax\),%eax
+ +[a-f0-9]+:	8f ea 78 10 00 00 00 00 00 	bextr  \$0x0,\(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 08       	blcfill \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 02 30       	blci   \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 28       	blcic  \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 02 08       	blcmsk \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 18       	blcs   \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 10       	blsfill \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 30       	blsic  \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 38       	t1mskc \(%rax\),%eax
+ +[a-f0-9]+:	8f e9 78 01 20       	tzmsk  \(%rax\),%eax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-vex-lig-2.s b/gas/testsuite/gas/i386/x86-64-vex-lig-2.s
new file mode 100644
index 0000000..26338fe
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vex-lig-2.s
@@ -0,0 +1,89 @@
+# Check VEX non-LIG instructions with with -mavxscalar=256
+
+	.allow_index_reg
+	.text
+_start:
+	        vmovd	%eax, %xmm0
+	        vmovd	(%rax), %xmm0
+	{vex3}  vmovd	%eax, %xmm0
+	{vex3}  vmovd	(%rax), %xmm0
+
+	        vmovd	%xmm0, %eax
+	        vmovd	%xmm0, (%rax)
+	{vex3}  vmovd	%xmm0, %eax
+	{vex3}  vmovd	%xmm0, (%rax)
+
+	        vmovq	%xmm0, %xmm0
+	        vmovq	(%rax), %xmm0
+	{vex3}  vmovq	%xmm0, %xmm0
+	{vex3}  vmovq	(%rax), %xmm0
+
+	{store} vmovq	%xmm0, %xmm0
+	        vmovq	%xmm0, (%rax)
+	{vex3} {store} vmovq %xmm0, %xmm0
+	{vex3}  vmovq	%xmm0, (%rax)
+
+	        vextractps $0, %xmm0, %eax
+	        vextractps $0, %xmm0, (%rax)
+
+	        vpextrb $0, %xmm0, %eax
+	        vpextrb $0, %xmm0, (%rax)
+
+	        vpextrw $0, %xmm0, %eax
+	{vex3}  vpextrw $0, %xmm0, %eax
+	{store} vpextrw $0, %xmm0, %eax
+	        vpextrw $0, %xmm0, (%rax)
+
+	        vpextrd $0, %xmm0, %eax
+	        vpextrd $0, %xmm0, (%rax)
+
+	        vpextrq $0, %xmm0, %rax
+	        vpextrq $0, %xmm0, (%rax)
+
+	        vinsertps $0, %xmm0, %xmm0, %xmm0
+	        vinsertps $0, (%rax), %xmm0, %xmm0
+
+	        vpinsrb $0, %eax, %xmm0, %xmm0
+	        vpinsrb $0, (%rax), %xmm0, %xmm0
+
+	        vpinsrw $0, %eax, %xmm0, %xmm0
+	        vpinsrw $0, (%rax), %xmm0, %xmm0
+	{vex3}  vpinsrw $0, %eax, %xmm0, %xmm0
+	{vex3}  vpinsrw $0, (%rax), %xmm0, %xmm0
+
+	        vpinsrd $0, %eax, %xmm0, %xmm0
+	        vpinsrd $0, (%rax), %xmm0, %xmm0
+
+	        vpinsrq $0, %rax, %xmm0, %xmm0
+	        vpinsrq $0, (%rax), %xmm0, %xmm0
+
+	        vldmxcsr (%rax)
+	        vstmxcsr (%rax)
+	{vex3}  vldmxcsr (%rax)
+	{vex3}  vstmxcsr (%rax)
+
+	andn	(%rax), %eax, %eax
+	bextr	%eax, (%rax), %eax
+	blsi	(%rax), %eax
+	blsmsk	(%rax), %eax
+	blsr	(%rax), %eax
+
+	bzhi	%eax, (%rax), %eax
+	mulx	(%rax), %eax, %eax
+	pdep	(%rax), %eax, %eax
+	pext	(%rax), %eax, %eax
+	rorx	$0, (%rax), %eax
+	sarx	%eax, (%rax), %eax
+	shlx	%eax, (%rax), %eax
+	shrx	%eax, (%rax), %eax
+
+	bextr	$0, (%rax), %eax
+	blcfill	(%rax), %eax
+	blci	(%rax), %eax
+	blcic	(%rax), %eax
+	blcmsk	(%rax), %eax
+	blcs	(%rax), %eax
+	blsfill	(%rax), %eax
+	blsic	(%rax), %eax
+	t1mskc	(%rax), %eax
+	tzmsk	(%rax), %eax