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2019-05-16[PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmulAndre Vieira20-15/+350
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (do_mve_vcmul): New encoding function. (do_vcmla): Change to support MVE variants. (do_vcadd): Change to support MVE variants. (insns): Change existing to support MVE variants and add new. * testsuite/gas/arm/mve-vcadd-bad-1.d: New test. * testsuite/gas/arm/mve-vcadd-bad-1.l: New test. * testsuite/gas/arm/mve-vcadd-bad-1.s: New test. * testsuite/gas/arm/mve-vcadd-bad-2.d: New test. * testsuite/gas/arm/mve-vcadd-bad-2.l: New test. * testsuite/gas/arm/mve-vcadd-bad-2.s: New test. * testsuite/gas/arm/mve-vcmla-bad-1.d: New test. * testsuite/gas/arm/mve-vcmla-bad-1.l: New test. * testsuite/gas/arm/mve-vcmla-bad-1.s: New test. * testsuite/gas/arm/mve-vcmla-bad-2.d: New test. * testsuite/gas/arm/mve-vcmla-bad-2.l: New test. * testsuite/gas/arm/mve-vcmla-bad-2.s: New test. * testsuite/gas/arm/mve-vcmul-bad-1.d: New test. * testsuite/gas/arm/mve-vcmul-bad-1.l: New test. * testsuite/gas/arm/mve-vcmul-bad-1.s: New test. * testsuite/gas/arm/mve-vcmul-bad-2.d: New test. * testsuite/gas/arm/mve-vcmul-bad-2.l: New test. * testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
2019-05-16[PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, ↵Andre Vieira17-94/+464
vorn and veor gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): New operands. (parse_operands): Handle new operands. (enum vfp_or_neon_is_neon_bits): Moved (vfp_or_neon_is_neon): Moved (check_simd_pred_availability): Moved. (do_neon_logic): Change to accept MVE variants. (insns): Changed to accept MVE variants. * testsuite/gas/arm/mve-vand-bad.d: New test. * testsuite/gas/arm/mve-vand-bad.l: New test. * testsuite/gas/arm/mve-vand-bad.s: New test. * testsuite/gas/arm/mve-vbic-bad.d: New test. * testsuite/gas/arm/mve-vbic-bad.l: New test. * testsuite/gas/arm/mve-vbic-bad.s: New test. * testsuite/gas/arm/mve-veor-bad.d: New test. * testsuite/gas/arm/mve-veor-bad.l: New test. * testsuite/gas/arm/mve-veor-bad.s: New test. * testsuite/gas/arm/mve-vorn-bad.d: New test. * testsuite/gas/arm/mve-vorn-bad.l: New test. * testsuite/gas/arm/mve-vorn-bad.s: New test. * testsuite/gas/arm/mve-vorr-bad.d: New test. * testsuite/gas/arm/mve-vorr-bad.l: New test. * testsuite/gas/arm/mve-vorr-bad.s: New test.
2019-05-16[PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddvAndre Vieira8-0/+245
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv, M_MNEM_vaddva): New instruction encodings. (mve_encode_rq): New encoding helper function. (do_mve_vaddlv): New encoding function. (do_mve_vaddv): New encoding function. * testsuite/gas/arm/mve-vaddlv-bad.d: New test. * testsuite/gas/arm/mve-vaddlv-bad.l: New test. * testsuite/gas/arm/mve-vaddlv-bad.s: New test. * testsuite/gas/arm/mve-vaddv-bad.d: New test. * testsuite/gas/arm/mve-vaddv-bad.l: New test. * testsuite/gas/arm/mve-vaddv-bad.s: New test.
2019-05-16[PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsrAndre Vieira11-0/+241
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr): New instruction encodings. (do_mve_vadc): New encoding instruction. (do_mve_vbrsr): Likewise. (do_mve_vsbc): Likewise. * testsuite/gas/arm/mve-vadc-bad.d: New test. * testsuite/gas/arm/mve-vadc-bad.l: New test. * testsuite/gas/arm/mve-vadc-bad.s: New test. * testsuite/gas/arm/mve-vbrsr-bad.d: New test. * testsuite/gas/arm/mve-vbrsr-bad.l: New test. * testsuite/gas/arm/mve-vbrsr-bad.s: New test. * testsuite/gas/arm/mve-vsbc-bad.d: New test. * testsuite/gas/arm/mve-vsbc-bad.l: New test. * testsuite/gas/arm/mve-vsbc-bad.s: New test.
2019-05-16[PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vptAndre Vieira14-26/+585
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (MVE_BAD_QREG): New error message. (enum operand_parse_code): Define new operand. (parse_operands): Handle new operand. (do_mve_vpt): Change for VPT blocks. (NEON_SHAPE_DEF): New shape. (neon_logbits): Moved. (LOW4): Moved (HI1): Moved (mve_get_vcmp_vpt_cond): New function to translate vpt conditions. (do_mve_vcmp): New encoding function. (do_vfp_nsyn_cmp): Changed to support MVE variants. (insns): Change to support MVE variants of vcmp and add vpt. * testsuite/gas/arm/mve-vcmp-bad-1.d: New test. * testsuite/gas/arm/mve-vcmp-bad-1.l: New test. * testsuite/gas/arm/mve-vcmp-bad-1.s: New test. * testsuite/gas/arm/mve-vcmp-bad-2.d: New test. * testsuite/gas/arm/mve-vcmp-bad-2.l: New test. * testsuite/gas/arm/mve-vcmp-bad-2.s: New test. * testsuite/gas/arm/mve-vpt-bad-1.d: New test. * testsuite/gas/arm/mve-vpt-bad-1.l: New test. * testsuite/gas/arm/mve-vpt-bad-1.s: New test. * testsuite/gas/arm/mve-vpt-bad-2.d: New test. * testsuite/gas/arm/mve-vpt-bad-2.l: New test. * testsuite/gas/arm/mve-vpt-bad-2.s: New test.
2019-05-16[PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmovAndre Vieira8-84/+520
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct arm_it): Expand isscalar field to be able to distinguish between types of scalar. (parse_typed_reg_or_scalar): Change to accept MVE scalar variants. (parse_scalar): Likewise. (parse_neon_mov): Accept MVE variant. (po_scalar_or_goto): Make use reg_type. (parse_operands): Change uses of po_scalar_or_goto. (do_vfp_sp_monadic): Change to accept MVE variants. (do_vfp_reg_from_sp): Likewise. (do_vfp_sp_from_reg): Likewise. (do_vfp_dp_rd_rm): Likewise. (do_vfp_dp_rd_rn_rm): Likewise. (do_vfp_dp_rm_rd_rn): Likewise. (M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): New instruction encodings. (NEON_SHAPE_DEF): New shape. (do_mve_mov): New encoding fuction. (do_mve_movn): Likewise. (do_mve_movl): Likewise. (do_neon_mov): Change to accept MVE variants. (mcCE): New MACRO. (insns): Accept new MVE variants and instructions. * testsuite/gas/arm/mve-vmov-bad-1.d: New test. * testsuite/gas/arm/mve-vmov-bad-1.l: New test. * testsuite/gas/arm/mve-vmov-bad-1.s: New test. * testsuite/gas/arm/mve-vmov-bad-2.d: New test. * testsuite/gas/arm/mve-vmov-bad-2.l: New test. * testsuite/gas/arm/mve-vmov-bad-2.s: New test.
2019-05-16[PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvtAndre Vieira17-19/+831
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum operand_parse_code): Add new operand. (parse_operands): Handle new operand. (do_neon_cvt_1): Handle MVE variants. (do_neon_cvttb_1): Likewise. (insns): Accept MVE variants. * testsuite/gas/arm/mve-vcvt-bad-1.d: New test. * testsuite/gas/arm/mve-vcvt-bad-1.l: New test. * testsuite/gas/arm/mve-vcvt-bad-1.s: New test. * testsuite/gas/arm/mve-vcvt-bad-2.d: New test. * testsuite/gas/arm/mve-vcvt-bad-2.l: New test. * testsuite/gas/arm/mve-vcvt-bad-2.s: New test. * testsuite/gas/arm/mve-vcvt-bad-3.d: New test. * testsuite/gas/arm/mve-vcvt-bad-3.l: New test. * testsuite/gas/arm/mve-vcvt-bad-3.s: New test. * testsuite/gas/arm/mve-vcvt-bad-4.d: New test. * testsuite/gas/arm/mve-vcvt-bad-4.l: New test. * testsuite/gas/arm/mve-vcvt-bad-4.s: New test. * testsuite/gas/arm/mve-vcvt-bad.d: New test. * testsuite/gas/arm/mve-vcvt-bad.l: New test. * testsuite/gas/arm/mve-vcvt-bad.s: New test.
2019-05-16[PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldrAndre Vieira20-7/+1536
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct arm_it): Make immisreg field larger to hold type of register. (enum shift_kind): Add SHIFT_UXTW shift kind. (enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode. (parse_shift): Handle new shift type. (parse_address_main): Accept new addressing modes. (M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd, M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New instruction encodings. (do_mve_vstr_vldr_QI): New encoding functions. (do_mve_vstr_vldr_RQ): Likewise. (do_mve_vstr_vldr_RI): Likewise. (do_mve_vstr_vldr): Likewise. * testsuite/gas/arm/mve-vldr-bad-1.d: New test. * testsuite/gas/arm/mve-vldr-bad-1.l: New test. * testsuite/gas/arm/mve-vldr-bad-1.s: New test. * testsuite/gas/arm/mve-vldr-bad-2.d: New test. * testsuite/gas/arm/mve-vldr-bad-2.l: New test. * testsuite/gas/arm/mve-vldr-bad-2.s: New test. * testsuite/gas/arm/mve-vldr-bad-3.d: New test. * testsuite/gas/arm/mve-vldr-bad-3.l: New test. * testsuite/gas/arm/mve-vldr-bad-3.s: New test. * testsuite/gas/arm/mve-vstr-bad-1.d: New test. * testsuite/gas/arm/mve-vstr-bad-1.l: New test. * testsuite/gas/arm/mve-vstr-bad-1.s: New test. * testsuite/gas/arm/mve-vstr-bad-2.d: New test. * testsuite/gas/arm/mve-vstr-bad-2.l: New test. * testsuite/gas/arm/mve-vstr-bad-2.s: New test. * testsuite/gas/arm/mve-vstr-bad-3.d: New test. * testsuite/gas/arm/mve-vstr-bad-3.l: New test. * testsuite/gas/arm/mve-vstr-bad-3.s: New test.
2019-05-16[PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4}Andre Vieira5-9/+611
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN. (BAD_EL_TYPE): New error message. (parse_neon_el_struct_list): Adapt to be able to accept MVE variant. (parse_address_main): Likewise. (group_reloc_type): Add GROUP_MVE. (enum operand_parse_code): Add new operands. (parse_operands): Handle new operands. (M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42, M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, M_MNEM_vld41, M_MNEM_vld42, M_MNEM_vld43): New encodings. (do_mve_vst_vld): New encoding function. (do_neon_ld_st_interleave): Use BAD_EL_TYPE. (it_fsm_pre_encode): Handle new it_instruction_type (handle_pred_state): Likewise. * testsuite/gas/arm/mve-vstld-bad.d: New test. * testsuite/gas/arm/mve-vstld-bad.l: New test. * testsuite/gas/arm/mve-vstld-bad.s: New test.
2019-05-16[PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t}Andre Vieira5-2/+192
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (BAD_MVE_AUTO): New error message. (BAD_MVE_SRCDEST): Likewise. (mark_feature_used): Diagnose MVE only instructions when in auto-detection mode or -march=all. (enum operand_parse_code): Define new operand. (parse_operands): Handle new operand. (M_MNEM_vmullt, M_MNEM_vmullb): New encodings. (mve_encode_qqq): New encoding helper function. (do_mve_vmull): New encoding function. (insns): Handle new instructions. * testsuite/gas/arm/mve-vmullbt-bad.d: New test. * testsuite/gas/arm/mve-vmullbt-bad.l: New test. * testsuite/gas/arm/mve-vmullbt-bad.s: New test.
2019-05-16[PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and ↵Andre Vieira14-3/+488
vmlsdav gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (struct asm_opcode): Make avalue a full int. (BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors. (enum operand_parse_code): Handle new operands. (parse_operands): Likewise. (M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx, M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx, M_MNEM_vmlsdavax): Define new encodings. (NEON_SHAPE_DEF): Add new shape. (neon_check_type): Use BAD_SIMD_TYPE. (mve_encode_rqq): New encoding helper function. (do_mve_vabav, do_mve_vmladav): New encoding functions. (mCEF): New MACRO. * testsuite/gas/arm/mve-vabav-bad.d: New test. * testsuite/gas/arm/mve-vabav-bad.l: New test. * testsuite/gas/arm/mve-vabav-bad.s: New test. * testsuite/gas/arm/mve-vmladav-bad.d: New test. * testsuite/gas/arm/mve-vmladav-bad.l: New test. * testsuite/gas/arm/mve-vmladav-bad.s: New test. * testsuite/gas/arm/mve-vmlav-bad.d: New test. * testsuite/gas/arm/mve-vmlav-bad.l: New test. * testsuite/gas/arm/mve-vmlav-bad.s: New test. * testsuite/gas/arm/mve-vmlsdav-bad.d: New test. * testsuite/gas/arm/mve-vmlsdav-bad.l: New test. * testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
2019-05-16[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vnegAndre Vieira8-6/+161
gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant. (insns): Change vabs and vneg entries to accept MVE variants. * testsuite/gas/arm/mve-vabsneg-bad-1.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-1.s: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.d: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.l: New test. * testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
2019-05-16[PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub ↵Andre Vieira16-353/+1328
and vabd gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (enum it_instruction_type): Rename to... (enum pred_instruction_type): ... this. Include VPT types. (it_insn_type): Rename to ... (pred_insn_type): .. this. (arm_it): Change comment. (enum arm_reg_type): Add new value. (reg_expected_msgs): New entry. (asm_opcode): Add mayBeVecPred member. (BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT, MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS. (arm_vcond_hsh): New table for vector condition codes. (now_it): Rename to ... (now_pred): ... this. (now_it_compatible): Rename to ... (now_pred_compatible): ... this. (in_it_block): Rename to ... (in_pred_block): ... this. (handle_it_state): Rename to ... (handle_pred_state): ... this. And change it to accept VPT blocks. (set_it_insn_type): Rename to ... (set_pred_insn_type): ... this. (set_it_insn_type_nonvoid): Rename to ... (set_pred_insn_type_nonvoid): ... this. (set_it_insn_type_last): Rename to ... (set_pred_insn_type_last): ... this. (record_feature_use): Moved. (mark_feature_used): Likewise. (parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ. (emit_insn): Use renamed functions and variables. (enum operand_parse_code): Add new operands. (parse_operands): Handle new operands. (do_scalar_fp16_v82_encode): Change predication detection. (do_it): Use renamed functions and variables. (do_t_add_sub): Likewise. (do_t_arit3): Likewise. (do_t_arit3c): Likewise. (do_t_blx): Likewise. (do_t_branch): Likewise. (do_t_bkpt_hlt1): Likewise. (do_t_branch23): Likewise. (do_t_bx): Likewise. (do_t_bxj): Likewise. (do_t_cond): Likewise. (do_t_csdb): Likewise. (do_t_cps): Likewise. (do_t_cpsi): Likewise. (do_t_cbz): Likewise. (do_t_it): Likewise. (do_mve_vpt): New function to handle VPT blocks. (encode_thumb2_multi): Use renamed functions and variables. (do_t_ldst): Use renamed functions and variables. (do_t_mov_cmp): Likewise. (do_t_mvn_tst): Likewise. (do_t_mul): Likewise. (do_t_nop): Likewise. (do_t_neg): Likewise. (do_t_rsb): Likewise. (do_t_setend): Likewise. (do_t_shift): Likewise. (do_t_smc): Likewise. (do_t_tb): Likewise. (do_t_udf): Likewise. (do_t_loloop): Likewise. (do_neon_cvt_1): Likewise. (do_vfp_nsyn_cvt_fpv8): Likewise. (do_vsel): Likewise. (do_vmaxnm): Likewise. (do_vrint_1): Likewise. (do_crypto_2op_1): Likewise. (do_crypto_3op_1): Likewise. (do_crc32_1): Likewise. (it_fsm_pre_encode): Likewise. (it_fsm_post_encode): Likewise. (force_automatic_it_block_close): Likewise. (check_it_blocks_finished): Likewise. (check_pred_blocks_finished): Likewise. (arm_cleanup): Likewise. (now_it_add_mask): Rename to ... (now_pred_add_mask): ... this. And use new variables and functions. (NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl. (N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs. (neon_check_type): Generalize error message. (mve_encode_qqr): New MVE generic encoding function. (neon_dyadic_misc): Change to accept MVE variants. (do_neon_dyadic_if_su): Likewise. (do_neon_addsub_if_i): Likewise. (do_neon_dyadic_long): Likewise. (vfp_or_neon_is_neon): Add extra checks. (check_simd_pred_availability): Helper function to check SIMD instruction availability with respect to predication. (enum opcode_tag): New suffix value. (opcode_lookup): Change to handle VPT blocks. (new_automatic_it_block): Rename to ... (close_automatic_it_block): ...this. (TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU, toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF, NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new field. (mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs. (insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE variants. Add entries for vscclrm, and vpst. (md_begin): Add arm_vcond_hsh initialization. * config/tc-arm.h (enum it_state): Rename to... (enum pred_state): ...this. (struct current_it): Rename to... (struct current_pred): ...this. (enum pred_type): New enum. (struct arm_segment_info_type): Use current_pred. * testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message. * testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message. * testsuite/gas/arm/dotprod-illegal.l: Update error message. * testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test. * testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test. * testsuite/gas/arm/mve-vpst-bad.d: New test. * testsuite/gas/arm/mve-vpst-bad.l: New test. * testsuite/gas/arm/mve-vpst-bad.s: New test. * testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
2019-05-16[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fpAndre Vieira3-1/+30
bfd/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch. binutils/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values. (arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch. elfcpp/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * arm.h (Tag_MVE_arch): Define new enum value. gas/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/tc-arm.c (mve_ext, mve_fp_ext): New features. (armv8_1m_main_ext_table): Add new extensions. (aeabi_set_public_attributes): Translate new features to new build attributes. (arm_convert_symbolic_attribute): Add Tag_MVE_arch. * doc/c-arm.texi: Document new extensions and new build attribute. include/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> * elf/arm.h (Tag_MVE_arch): Define new enum value. * opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
2019-05-15S12Z: New option -mreg-prefixJohn Darrington6-17/+155
Add a new machine dependent option to set a prefix for register names. gas/ * config/tc-s12z.c (register_prefix): New variable. (md_show_usage, md_parse_option): parse the new option. (lex_reg_name): Scan the prefix if one is set. * doc/c-s12z.texi (S12Z-Opts): Document the new option. * testsuite/gas/s12z/reg-prefix.d: New file. * testsuite/gas/s12z/reg-prefix.s: New file. * testsuite/gas/s12z/s12z.exp: Add them.
2019-05-15GAS (doc): Fix misaligned menu entry.John Darrington2-1/+5
gas/ * doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
2019-05-15C-SKY FAIL: jbt - cskyAlan Modra2-0/+7
Another failure seen with MALLOC_PERTURB_=1. * config/tc-csky.c (md_convert_frag): Initialise trailing padding for COND_JUMP_PIC.
2019-05-15.file file number checkingAlan Modra2-22/+31
This adds another test for file numbers given in .file directives, checking that the value can be represented as an unsigned int and that a memory allocation expression doesn't overflow. I removed a test added recently since an earlier test (num < 1) already covers the (num < 0) case. * dwarf2dbg.c: Whitespace fixes. (get_filenum): Don't strdup "file". Adjust error message. (dwarf2_directive_filename): Use an unsigned type for "num". Catch truncation of file number and overflow of get_filenum XRESIZEVEC multiplication. Delete dead code.
2019-05-15tic54x_start_line_hookAlan Modra2-6/+9
git commit 3076e59490 caused tic54x-coff +FAIL: c54x subsym assignment/use PR 24538 * config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line chars in setting endp.
2019-05-14Fix illegal memory access triggered when attempting to assemble a bogus i386 ↵Nick Clifton2-0/+12
source file. PR 24538 * config/tc-i386-intel.c (i386_intel_simplify_register): Reject illegal register numbers.
2019-05-14A series of fixes to addres problems detected by compiling the assembler ↵Nick Clifton29-138/+168
with address sanitization enabled. PR 24538 gas * macro.c (get_any_string): Increase size of buffer used to hold decimal value of expression result. * dw2gencfi.c (get_debugseg_name): Handle an empty name. * dwarf2dbg.c (get_filenum): Catch integer wraparound when extending allocate file array. (dwarf2_directive_filename): Add extra checks of the computed file number. * config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into warning hash table. (s_arm_eabi_attribute): Check for obj_elf_vendor_attribute returning -1. * config/tc-i386.c (i386_output_nops): Catch an attempt to generate nops of negative lengths. * as.h (MAX_LITTLENUMS): Move definition to here from... * config/atof-ieee.c: ...here. * config/tc-aarch64.c: ...here. * config/tc-arc.c: ...here. * config/tc-arm.c: ...here. * config/tc-epiphany.c: ...here. * config/tc-i386.c: ...here. * config/tc-ia64.c: ...here. (And correct the value). * config/tc-m32c.c: ...here. * config/tc-m32r.c: ...here. * config/tc-metag.c: ...here. * config/tc-microblaze.c: ...here. * config/tc-nds32.c: ...here. * config/tc-or1k.c: ...here. * config/tc-score.c: ...here. * config/tc-score7.c: ...here. * config/tc-tic4x.c: ...here. * config/tc-tilegx.c: ...here. * config/tc-tilepro.c: ...here. * config/tc-visium.c: ...here. * config/tc-sh.c (md_assemble): Add check for an instruction with no opcodes. * config/tc-mips.c (mips_lookup_insn): Add check for very short instruction name. * config/tc-tic54x.c: Use unsigned chars to access is_end_of_line array. (tic54x_start_line_hook): Check for an empty line. (next_line_shows_parallel): Do not walk off the end of the string. (tic54x_macro_start): Check for too much macro nesting. (tic54x_start_label): Add label_start parameter. Use this parameter to check the first character of the label. * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass line_start variable to tic54x_start_label. PR 24538 opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the end of the table prematurely.
2019-05-10Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6Faraz Shahbazker7-10/+62
Release 6 of the MIPS architecture does not have an ADDI instruction. ADD/SUB instructions with immediate operands can be expanded to load and immediate value and then perform the operation. gas/ * config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>: Add expansions for MIPS r6. * testsuite/gas/mips/add.s: Enable tests for R6. * testsuite/gas/mips/daddi.s: Annotate to test DADD for R6. * testsuite/gas/mips/mipsr6@add.d: Likewise. * gas/testsuite/gas/mips/mipsr6@dadd.d: New test. * gas/testsuite/gas/mips/mips.exp: Run the new test. opcodes/ * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB macros for R6.
2019-05-09Update printing of optional operands during disassembly.Peter Bergner2-4/+4
opcodes/ * ppc-dis.c (skip_optional_operands): Change return type and returns. (print_insn_powerpc) <skip_optional>: Change type. Call skip_optional_operands if we have not skipped any operands. gas/ * testsuite/gas/ppc/476.d: Update expected output. * testsuite/gas/ppc/power6.d: Likewise.
2019-05-09[gas][testsuite] Don't specify arch in testsuite outputMatthew Malcomson2-1/+5
My testcase matched against a file format of elf64-littleaarch64 in the objdump output. This was unnecessarily restrictive and causes testcase failures on aarch64_be. Here we remove that restriction. Committed as obvious. Testing done on aarch64_be-none-elf gas to see the failure goes away. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/sve2.d: Remove file format restriction.
2019-05-09[binutils][aarch64] Add SVE2 testsMatthew Malcomson13-0/+8621
Add tests that SVE2 instructions are encoded as they should be, and tests that invalid instructions have their problems reported. Also check that each sve2 cryptographic extension is required to use the corresponding cryptographic instructions. Finally, test to ensure that sve2 instructions using mnemonics that exist in sve1 still need the sve2 feature to be used. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: New test. * testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.s: Test new instructions. * testsuite/gas/aarch64/sve1-extended-sve2.s: New test. * testsuite/gas/aarch64/sve2.d: Test new instructions. * testsuite/gas/aarch64/sve2.s: Test new instructions.
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson2-0/+6
New operand describes a shift-left immediate encoded in bits 22:20-19:18-16 where UInt(bits) - esize == shift. This operand is useful for instructions like sshllb. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHLIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson2-0/+6
This includes defining a new single bit field SVE_i2h at position 20. SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm4_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. (fields): Handle SVE_i2h field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
2019-05-09[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.Matthew Malcomson2-0/+6
Include a new iclass to extract the variant from the most significant 3 bits of this operand. Instructions such as rshrnb include a constant shift amount as an operand, where the most significant three bits of this operand determine what size elements the instruction is operating on. The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that the SVE qualifier is encoded in bits 22:20-19. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 operand. (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-asm.c (aarch64_ins_sve_shrimm): (aarch64_encode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass encode. * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle sve_shift_tsz_hsd iclass decode. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_SHRIMM_UNPRED_22. (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 operand.
2019-05-09[binutils][aarch64] New SVE_ADDR_ZX operand.Matthew Malcomson2-4/+54
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses in a Zn register, offset by an Xm register. This is used with scatter/gather SVE2 instructions. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (REG_ZR): Macro specifying zero register. (parse_address_main): Account for new addressing mode [Zn.S, Xm]. (parse_operands): Handle new SVE_ADDR_ZX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_ADDR_ZX. (aarch64_print_operand): Add printing for SVE_ADDR_ZX. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
2019-05-09[binutils][aarch64] New SVE_Zm3_11_INDEX operand.Matthew Malcomson2-0/+6
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_Zm3_11_INDEX. (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. (fields): Handle SVE_i3l and SVE_i3h2 fields. * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 fields. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson2-0/+5
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate operand encoded at bit position 10. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking for SVE_IMM_ROT3. (aarch64_print_operand): Add printing for SVE_IMM_ROT3. (fields): Handle SVE_rot3 field. * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson3-0/+29
Include all feature flag macros. The "sve2" extension that enables the core sve2 instructions. This also enables the sve extension, since sve is a requirement of sve2. Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions. These are all given extra feature flags, "bitperm", "sve2-sm4", "sve2-aes", and "sve2-sha3" respectively. The sm4, aes, and sha3 extensions are explicitly marked as sve2 extensions to distinguish them from the corresponding NEON extensions. Rather than continue extending the current feature flag numbers, I used some bits that have been skipped. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * config/tc-aarch64.c: Add command line architecture feature flags "sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm". * doc/c-aarch64.texi: Document new architecture feature flags. include/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_SVE2 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM, AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New feature macros. opcodes/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * aarch64-tbl.h (aarch64_feature_sve2, aarch64_feature_sve2aes, aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, aarch64_feature_sve2bitperm): New feature sets. (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros for feature set addresses. (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2019-05-08gas/elf dwarf2 testsAlan Modra35-220/+243
Make them work for tile, by using ".quad 0" as the simulated instruction and doubling size of aligns. The larger aligns tripped over riscv alignment handling, fixed by adding -mno-relax there. Also disable link-relax for avr, pru and xtensa, allowing these targets to pass these tests. With link-time relaxation enabled, these targets emit alignment relocations rather than aligning at assembly time. This means the assembler doesn't see a change in PC when it is expected over an alignment frag and thus view numbers are calculated incorrectly. * testsuite/gas/elf/dwarf2-1.s, * testsuite/gas/elf/dwarf2-2.s, * testsuite/gas/elf/dwarf2-5.s, * testsuite/gas/elf/dwarf2-7.s, * testsuite/gas/elf/dwarf2-8.s, * testsuite/gas/elf/dwarf2-9.s, * testsuite/gas/elf/dwarf2-10.s, * testsuite/gas/elf/dwarf2-11.s, * testsuite/gas/elf/dwarf2-12.s, * testsuite/gas/elf/dwarf2-13.s, * testsuite/gas/elf/dwarf2-14.s, * testsuite/gas/elf/dwarf2-15.s, * testsuite/gas/elf/dwarf2-16.s, * testsuite/gas/elf/dwarf2-17.s, * testsuite/gas/elf/dwarf2-18.s, * testsuite/gas/elf/dwarf2-19.s: Double size of align and simulated instructions. * testsuite/gas/elf/dwarf2-1.d, * testsuite/gas/elf/dwarf2-2.d, * testsuite/gas/elf/dwarf2-5.d, * testsuite/gas/elf/dwarf2-7.d, * testsuite/gas/elf/dwarf2-8.d, * testsuite/gas/elf/dwarf2-9.d, * testsuite/gas/elf/dwarf2-10.d, * testsuite/gas/elf/dwarf2-11.d, * testsuite/gas/elf/dwarf2-12.d, * testsuite/gas/elf/dwarf2-13.d, * testsuite/gas/elf/dwarf2-14.d, * testsuite/gas/elf/dwarf2-15.d, * testsuite/gas/elf/dwarf2-16.d, * testsuite/gas/elf/dwarf2-17.d, * testsuite/gas/elf/dwarf2-18.d, * testsuite/gas/elf/dwarf2-19.d: Use xfail rather than notarget. Remove avr, pru, tile, xtensa from xfails. Update expected output. * testsuite/gas/elf/elf.exp: Sort targets. (dump_opts): Pass {as -mno-relax} for riscv, {as -mno-link-relax} for avr and pru, and {as --no-link-relax} for xtensa to dwarf tests. * testsuite/gas/elf/section2.e-miwmmxt: Delete unused file.
2019-05-08xtensa ignores option --no-link-relaxAlan Modra2-3/+10
md_begin happens after md_parse_option. * config/tc-xtensa.c (opt_linkrelax): New variable. (md_parse_option): Set it here. (md_begin): Copy opt_linkrelax to linkrelax.
2019-05-07xfail locview tests on mep that use complex relocs for view numbersAlexandre Oliva3-2/+9
Expressions that compute view numbers that aren't simplified early enough to a constant end up being selected for representation as complex relocations, enabled on mep-* targets. It would be possible to recognize such expressions, that can resolve to constants, but this problem was hit before, in preexisting tests, so xfail the new hits similarly. The new hits were caused by yesterday's patch to dwarf2dbg.c: views in the beginning of subsections are now computed later, based on the final views or previous subsections in the same section. for gas/ChangeLog * testsuite/gas/elf/dwarf2-18.d: Xfail mep-*. * testsuite/gas/elf/dwarf2-19.d: Likewise.
2019-05-07Tidy use_complex_relocs_forAlan Modra2-22/+18
Since I was looking at this I decided to fix the formatting, and used an old C switch statements trick to factor out common code. * symbols.c (use_complex_relocs_for): Formatting. Factor out X_add_symbol tests.
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker6-1/+91
Add paired load-link and store-conditional instructions to the EVA ASE for MIPS32R6[1]. These instructions are optional within the EVA ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 230-231, pp. 357-360. gas/ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. (mips_after_parse_args): Translate EVA to EVA_R6. * testsuite/gas/mips/ase-errors-1.s: Add new instructions. * testsuite/gas/mips/eva.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Check errors for new instructions. * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. include/ * opcode/mips.h (ASE_EVA_R6): New macro. (M_LLWPE_AB, M_SCWPE_AB): New enum values. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Add ISA argument and set ASE_EVA_R6 appropriately. (set_default_mips_dis_options): Pass ISA to above. (parse_mips_dis_option): Likewise. * mips-opc.c (EVAR6): New macro. (mips_builtin_opcodes): Add llwpe, scwpe. Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
2019-05-06sym->sy_value is not valid for struct local_symbolAlan Modra2-1/+6
Fixes this mep-elf error: gas/elf/dwarf2-19.s: Error: Unknown expression operator (enum 0) gas/elf/dwarf2-19.s: Error: cannot convert expression symbol .L2 to complex relocation * symbols.c (symbol_relc_make_sym): Do not access sym->sy_value directly.
2019-05-06PowerPC reloc symbols that shouldn't be adjustedAlan Modra3-1/+27
GOT and PLT relocs shouldn't have their symbols replaced with a section symbol plus added. Nor should the HIGHA TLS relocations, which failed to be caught by the range test in ppc_fix_adjustable. bfd/ * reloc.c (BFD_RELOC_PPC64_TPREL16_HIGH, BFD_RELOC_PPC64_TPREL16_HIGHA), (BFD_RELOC_PPC64_DTPREL16_HIGH, BFD_RELOC_PPC64_DTPREL16_HIGHA): Sort before BFD_RELOC_PPC64_DTPREL16_HIGHESTA entry. gas/ * config/tc-ppc.c (ppc_fix_adjustable): Exclude all GOT and PLT relocs, and VLE sdarel relocs. * testsuite/gas/ppc/power4.d: Adjust.
2019-05-05[LVu] base subseg head view on prev subseg's tailAlexandre Oliva5-5/+107
Location views at borders between subsegments/subsections in the same segment/section are computed as if each new subsegment/subsection started with a forced view reset to zero, but the line number program does not introduce resets that are not explicitly requested, so if a subsegment ends at the same address another starts, the line number program will have a continuity of views at the border address, whereas the initial view number label in the latter subsegment will be miscomputed as zero. This patch delays the assignment of view expressions at subsegment heads to the time of chaining the frags of subsegments into a single segment, so that they are set based on the view at the end of the previous subsegment in the same segment. The line number program created for the test program had an unnecessary DW_LNS_advance_pc at the end. This patch also arranges for us not to emit it. for gas/ChangeLog * dwarf2dbg.c (set_or_check_view): Skip heads when assigning views of prior locs. (dwarf2_gen_line_info_1): Skip heads. (size_inc_line_addr, emit_inc_line_addr): Drop DW_LNS_advance_pc for zero addr delta. (dwarf2_finish): Assign views for heads of segments. * testsuite/gas/elf/dwarf2-19.d: New. * testsuite/gas/elf/dwarf2-19.s: New. * testsuite/gas/elf/elf.exp: Test it.
2019-05-04m32c padding with nopsAlan Modra8-31/+23
m32c_md_end attempted to pad out a code section with nops, but this was just plain wrong in many ways: - The padding didn't happen at all if the last section emitted wasn't a code section. - The padding went to the wrong place if subsections were used, and the last subseg used wasn't the highest numbered subseg. - Padding wasn't added to all code sections. - If the last section was empty, it was padded to 4 bytes. - The padding didn't go to a 4-byte alignment boundary, instead it effectively made the last instruction 4 bytes in size. - The padding didn't take into account that code sections may have contents other than machine instructions. So, rip it out and handle nop padding properly, also fixing .align .balign/.p2align in the middle of code. gas/ * config/tc-m32c.c (insn_size): Delete static var. (md_begin): Don't set it. (m32c_md_end): Delete. (md_assemble): Add insn_size auto var. * config/tc-m32c.h (md_end): Don't define. (m32c_md_end): Delete. (NOP_OPCODE, HANDLE_ALIGN, MAX_MEM_FOR_RS_ALIGN_CODE): Define. * testsuite/gas/all/align.d: Remove m32c from notarget list. * testsuite/gas/all/incbin.d: Likewise. * testsuite/gas/elf/dwarf2-11.d: Likewise. * testsuite/gas/macros/semi.d: Likewise. * testsuite/gas/all/gas.exp (do_comment): Similarly. ld/ * testsuite/ld-scripts/fill.d: Don't xfail m32c * testsuite/ld-scripts/fill16.d: Likewise.
2019-05-02i386: Issue a warning to IRET without suffix for .code16gccH.J. Lu5-7/+46
The .code16gcc directive to support 16-bit mode with 32-bit address. For IRET without a suffix, generate 16-bit IRET with a warning to return from an interrupt handler in 16-bit mode. PR gas/24485 * config/tc-i386.c (process_suffix): Issue a warning to IRET without a suffix for .code16gcc. * testsuite/gas/i386/jump16.s: Add tests for iretX. * testsuite/gas/i386/jump16.d: Updated. * testsuite/gas/i386/jump16.e: New file.
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das8-0/+111
This patch enables the new Transactional Memory Extension added recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> The ISA for the above can be found here: https://developer.arm.com/docs/ddi0602/latest/base-instructions-alphabetic-order *** gas/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * config/tc-aarch64.c (parse_operands): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_features): Add "tme". * doc/c-aarch64.texi: Document the same. * testsuite/gas/aarch64/tme-invalid.d: New test. * testsuite/gas/aarch64/tme-invalid.l: New test. * testsuite/gas/aarch64/tme-invalid.s: New test. * testsuite/gas/aarch64/tme.d: New test. * testsuite/gas/aarch64/tme.s: New test. *** include/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16. *** opcodes/ChangeLog *** 2019-05-01 Sudakshina Das <sudi.das@arm.com> * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated. * aarch64-opc.c (operand_general_constraint_met_p): Add case for AARCH64_OPND_TME_UIMM16. (aarch64_print_operand): Likewise. * aarch64-tbl.h (QL_IMM_NIL): New. (TME): New. (_TME_INSN): New. (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2019-04-29S12Z: Opcodes: Fix crash when trying to decode a truncated operation.John Darrington4-0/+27
opcodes/ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. gas/ * testsuite/gas/s12z/truncated.d: New file. * testsuite/gas/s12z/truncated.s: New file. * testsuite/gas/s12z/s12z.exp: Add new test.
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett14-10/+228
Add several baseline MIPS32R6[1] and MIPS64R6[2] instructions that were omitted from the initial spec. These instructions are optional in implementations but not associated with any ASE or pseudo-ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 228-229, pp. 354-357. [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 289-290 and pp. 458-460. gas/ * config/tc-mips.c (macro) <M_LLWP_AB, M_LLDP_AB, M_SCWP_AB, M_SCDP_AB>: New cases and expansions for paired instructions. * testsuite/gas/mips/llpscp-32.s: New test source. * testsuite/gas/mips/llpscp-64.s: Likewise. * testsuite/gas/mips/llpscp-32.d: New test. * testsuite/gas/mips/llpscp-64.d: Likewise. * testsuite/gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/r6.s: Add new instructions to test source. * testsuite/gas/mips/r6-64.s: Likewise. * testsuite/gas/mips/r6-64-n32.d: Check new instructions. * testsuite/gas/mips/r6-64-n64.d: Likewise. * testsuite/gas/mips/r6-n32.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likwwise. * testsuite/gas/mips/r6.d: Likewise. include/ * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values. (M_SCWP_AB, M_SCDP_AB): Likewise. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2019-04-26i386: Don't add 0x66 prefix to IRET for .code16gccH.J. Lu4-0/+22
The .code16gcc directive supports 16bit mode with 32-bit address. Since IRET (opcode 0xcf) in 16bit mode returns from an interrupt in 16bit mode, we shouldn't add 0x66 prefix for IRET. PR gas/24485 * config/tc-i386.c (process_suffix): Don't add DATA_PREFIX_OPCODE to IRET for .code16gcc. * testsuite/gas/i386/jump16.s: Add IRET tests. * testsuite/gas/i386/jump16.d: Updated.
2019-04-25Speed up locview resolution with relaxable fragsAlexandre Oliva4-1/+69
Targets such as xtensa incur a much higher overhead to resolve location view numbers than e.g. x86, because the expressions used to compute view numbers cannot be resolved soon enough. Each view number is computed by incrementing the previous view, if they are both at the same address, or by resetting it to zero otherwise. If PV is the previous view number, PL is its location, and NL is the location of the next view, its number is computed by evaluating NV = !(NL > PL) * (PV + 1). set_or_check_view uses resolve_expression to decide whether portions of this expression can be simplified to constants. The (NL > PL) subexpression is one that can often be resolved to a constant, breaking chains of view number computations at instructions of nonzero length, but not after alignment that might be unnecessary. Alas, when nearly every frag ends with a relaxable instruction, frag_offset_fixed_p will correctly fail to determine a known offset between two unresolved addresses in neighboring frags, so the unresolved symbolic operation will be constructed and used in the computation of most view numbers. This results in very deep expressions. As view numbers get referenced in location view lists, each operand in the list goes through symbol_clone_if_forward_ref, which recurses on every subexpression. If each view number were to be referenced, this would exhibit O(n^2) behavior, where n is the depth of the view number expressions, i.e., the length of view number sequences without an early resolution that cuts the expression short. This patch enables address compares used by view numbering to be resolved even when exact offsets are not known, using new logic to determine when the location either remained the same or changed for sure, even with the possibility of relaxation. This enables most view number expressions to be resolved with a small, reasonable depth. PR gas/24444 * frags.c (frag_gtoffset_p): New. * frags.h (frag_gtoffset_p): Declare it. * expr.c (resolve_expression): Use it.
2019-04-24resolve_symbol_value vs. .loc view resolutionAlan Modra3-29/+35
In most cases we don't want expression symbols, such as that created for an expression like "symbol + (1f - .)", resolved down to a constant. Instead we'd like to leave the expression as "symbol + constant" once the "1f - ." part has been resolved, and let the backend decide whether "symbol" can be reduced further. However, that doesn't work when trying to resolve .loc view symbols early. We get expression symbols left as an O_symbol expression pointing at an absolute symbol, and marked as sy_flags.sy_resolved. That wouldn't really be a problem, but when one of those expression symbols is used in further .loc view expressions, its value is taken as zero. This patch fixes the symbol value mistake, and stops creation of O_symbol expression symbols pointing to absolute symbols. Either of these fixes would cure the .loc view usage. PR 24444 * symbols.c (resolve_symbol_value): When handling symbols marked as sy_flags.resolved, return correct value for the case of expression symbols left as an O_symbol expression. Merge O_symbol code handling undefined and common symbols with code handling special cases of expression symbols. Use seg_left to test for undefined and common symbols. Don't leave an O_symbol expression when X_add_symbol resolves to the absolute_section. Init final_val later. * testsuite/gas/mmix/basep-7.d: Adjust expected output.
2019-04-24S12Z: Opcodes: Handle bit map operations with non-canonical operands.John Darrington3-1/+15
opcodes/ * s12z-opc.c (bm_decode): Handle the RESERVERD0 case. gas/ * testsuite/gas/s12z/bit-manip-invalid.d: Extend the test. * testsuite/gas/s12z/bit-manip-invalid.s: Extend the test.
2019-04-19RX Assembler: Ensure that the internal limit on the number of relaxation ↵Nick Clifton3-8/+31
iterations is not larger that the external limit. PR 24464 * config/tc-rx.h (md_relax_frag): Pass the max_iterations variable to the relaxation function. * config/tc-rx.c (rx_relax_frag): Add new parameter - the maximum number of iterations. Make sure that our internal iteration limit does not exceed this external iteration limit.
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