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gas/ChangeLog:
* NEWS: Update gas/NEWS for Intel APX.
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RISC-V Profiles document defines number of "extensions" that indicate
certain platform properties/capabilities just like 'Zkt' extension from the
RISC-V cryptography extensions.
This commit defines 20 platform property/capability extensions as defined
in the RISC-V Profiles documentation.
The only exception: 'Ssstateen' extension is defined separately because it
defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension.
This is based on the ratified version of RISC-V Profiles:
<https://github.com/riscv/riscv-profiles/releases/tag/v1.0>
[Definition]
"Main memory regions":
Main memory regions (in contrast to I/O or vacant memory regions) with
both the cacheability and coherence PMAs.
[New Unprivileged Extensions]
1. 'Ziccif'
"Main memory regions" support instruction fetch and any instruction
fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN)
are atomic.
2. 'Ziccrse'
"Main memory regions" provide the eventual success guarantee for
LR/SC sequence (RsrvEventual).
3. 'Ziccamoa'
"Main memory regions" support all currently-defined AMO operations
including swap, logical and arithmetic operations (AMOArithmetic).
4. 'Za64rs'
For LR/SC instructions, reservation sets are contiguous, naturally
aligned and at most 64-bytes in size.
5. 'Za128rs'
Likewise, but reservation sets are at most 128-bytes in size.
6. 'Zicclsm'
Misaligned loads / stores to "main memory regions" are supported.
Those include both regular scalar and vector accesses but does not
include AMOs and other specialized forms of memory accesses.
7. 'Zic64b'
Cache blocks are (exactly) 64-bytes in size and naturally aligned.
[New Privileged Extensions]
1. 'Svbare'
"satp" mode Bare is supported.
2. 'Svade'
Page-fault exceptions are raised when a page is accessed when A bit is
clear, or written when D bit is clear.
3. 'Ssccptr'
"Main memory regions" support hardware page-table reads.
4. 'Sstvecd'
"stvec" mode Direct is supported. When "stvec" mode is Direct,
"stvec.BASE" is capable of holding any valid 4-byte aligned address.
5. 'Sstvala'
"stval" is always written with a nonzero value whenever possible as
specified in the Privileged Architecture documentation
(version 20211203: see section 4.1.9).
6. 'Sscounterenw'
For any "hpmcounter" that is not read-only zero, the corresponding bit
in "scounteren" is writable.
7. 'Ssu64xl'
"sstatus.UXL" is capable of holding the value 0b10
(UXLEN==64 is supported).
8. 'Shcounterenw'
Similar to 'Sscounterenw' but the same rule applies to "hcounteren".
9. 'Shvstvala'
Similar to 'Sstvala' but the same rule applies to "vstval".
10. 'Shtvala'
"htval" is written with the faulting guest physical address as long as
permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala').
11. 'Shvstvecd'
Similar to 'Sstvecd' but the same rule applies to "vstvec".
12. 'Shvsatpa'
All translation modes supported in "satp" are also supported in "vsatp".
13. 'Shgatpa'
For each supported virtual memory scheme SvNN supported in "satp", the
corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare
is also supported.
[Implications]
(Due to reservation set size constraints)
- 'Za64rs' -> 'Za128rs'
(Due to the fact that a privileged "extension" directly refers a CSR)
- 'Svbare' -> 'Zicsr'
- 'Sstvecd' -> 'Zicsr'
- 'Sstvala' -> 'Zicsr'
- 'Sscounterenw' -> 'Zicsr'
- 'Ssu64xl' -> 'Zicsr'
(Due to the fact that a privileged "extension" indirectly depends on CSRs)
- 'Svade' -> 'Zicsr'
(Due to the fact that a privileged "extension" is a hypervisor property)
- 'Shcounterenw' -> 'H'
- 'Shvstvala' -> 'H'
- 'Shtvala' -> 'H'
- 'Shvstvecd' -> 'H'
- 'Shvsatpa' -> 'H'
- 'Shgatpa' -> 'H'
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Updated for property
and capability extensions.
(riscv_supported_std_z_ext): Added zic64b, ziccamoa, ziccif, zicclsm,
ziccrse, za64rs and za128rs extensions.
(riscv_supported_std_s_ext): Added shcounterenw, shgatpa, shtvala,
shvsatpa, shvstvala, shvstvecd, ssccptr, sscounterenw, sstvala,
sstvecd, ssu64xlm svade and svbare extensions.
gas/
* testsuite/gas/riscv/imply.d: Updated for property and capability
extensions.
* testsuite/gas/riscv/imply.s: Likewise.
* testsuite/gas/riscv/march-help.l: Likewse.
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Fixes a failure on rx-elf where the standard data section isn't .data.
run_dump_test has machinery to translate .data in both options and
expected results for objdump, but not for readelf -x.
PR 31964
* testsuite/gas/all/base64.d: Dump .data with objdump. Run on
all targets.
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PR 31964
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This patch adds support for followign SVE2p1 instruction, spec is available here [1].
1. PMOV (to vector)
2. PMOV (to predicate)
Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.
AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".
As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
PMOV <Pn>.D, <Zd>{[<imm>]}
Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d
Assembly: pmov z5, p6.d
Disassembly: pmov z5, p6.d
Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5
Assembly: pmov p4.b, z5
Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch adds support for SVE2p1 "tbxq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch adds support for SVE2p1 "zipq1" and "zipq2" instructions, spec is
available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch adds support for SVE2p1 "uzpq1" and "uzpq2" instructions, spec is
available here [1]
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch adds support for SVE2p1 "tblq" instruction, spec is available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch adds support for SVE2p1 "orqv" instruction, spec available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
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This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
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AArch64 defines new registers for the feature step2 (Enhanced Software Step
Extension). step2 is an Armv9.5-A feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
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AArch64 defines new registers for the feature spmu2 (System Performance
Monitors Extension version 2). spmu2 is an Armv9.5-A feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
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AArch64 defines new registers for the feature e3dse (Delegated SError
exceptions for EL3): vdisr_el3 and vdisr_el3. e3dse is an Armv9.5-A
feature.
This patch also adds relevant tests. Regression tested on aarch64-none-elf,
and no regression found.
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Added the restriction in assemble for APX TLS IE that the destination
can only be a register.
gas/
* config/tc-i386.c (md_assemble): Added stricter restrictions
for APX TLS IE.
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As was pointed out several times before, old glibc declares index(),
resulting in warnings from -Wshadow, in turn failing the build due to
-Werror.
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Added new macro %SW to CCMPcc to print ".s" after the mnemonic.
Before:
ccmpbl {dfv=}.s %edx,%eax
After:
ccmpbl.s {dfv=} %edx,%eax
gas/ChangeLog:
* testsuite/gas/i386/x86-64-pseudos-apx.d: Add tests for CCMPcc.
* testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex.h: Added %SW for CCMPcc swap operands.
* i386-dis.c (struct dis386): Added %SW.
(putop): Handle %SW.
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gas/ChangeLog:
* testsuite/gas/i386/x86-64.exp: Add {load}/{store} tests for apx
instructions.
* testsuite/gas/i386/x86-64-pseudos-apx.d: New test.
* testsuite/gas/i386/x86-64-pseudos-apx.s: Ditto.
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In commit dff565fcca8137954d6ad571ef39f6aec5c0429c, the fixups
for PCREL_LO12_I and PCREL_LO12_S were mixed, so the "IMM"
field were applied to incorrect position, this caused incorrect
src registers to be encoded.
gas/
* config/tc-riscv.c (md_apply_fix): Fix PCREL_LO12_S issue.
* testsuite/gas/riscv/ixup-local.s: Updated for PCREL_LO12_S cases.
* testsuite/gas/riscv/fixup-local-relax.d: Likewise.
* testsuite/gas/riscv/fixup-local-norelax.d: Likewise.
Signed-off-by: Jianwei Sun <sunny.sun@corelabtech.com>
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When the same address across different segments (sections) needs to be
recorded, it will overwrite the slot, leading to a memory leak. To ensure
uniqueness, the segment (section) ID needs to be included in the hash key
calculation.
gas/
* config/tc-riscv.c (riscv_pcrel_hi_fixup): New "const asection *sec".
(riscv_pcrel_fixup_hash): make sec->id and e->adrsess as the
hash key.
(riscv_pcrel_fixup_eq): Check sec->id at first.
(riscv_record_pcrel_fixup): New member "sec".
(md_apply_fix) <case BFD_RELOC_RISCV_PCREL_HI20>: Likewise.
(md_apply_fix) <case BFD_RELOC_RISCV_PCREL_LO12_I>: Likewise.
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The encoding was previously not taking into account that the Quad vector
registers were being encoded using their Q-register numbers rather than their
D-register equivalent (multiply by 2).
gas/
* config/tc-arm.c (do_neon_cvttb_1): Use Q-register vector number
rather than their D-register equivalent.
gas/testsuite/
* gas/arm/mve-vcvt-3.d: Correct expected values in test.
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Verify all architectures participating in SFrame generation do define
the mandatory SFrame return address (RA) tracking predicate function
sframe_ra_tracking_p. Do so by explicitly not testing for the macro
SFRAME_FRE_RA_TRACKING as otherwise required.
Verify that architectures not using SFrame RA tracking specify a valid
fixed RA offset.
gas/
* gen-sframe.c (output_sframe_internal): Validate SFrame
RA tracking and fixed RA offset.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The existence of the macro SFRAME_FRE_RA_TRACKING only ensures the
existence of the macro SFRAME_CFA_RA_REG and the predicate function
sframe_ra_tracking_p. It does not indicate whether SFrame RA tracking
is actually used.
Test the return value of the SFrame RA tracking predicate function
sframe_ra_tracking_p to determine whether RA tracking is used.
This aligns the logic in functions get_fre_num_offsets and
output_sframe_row_entry to the one used in all other places.
gas/
* gen-sframe.c (get_fre_num_offsets, output_sframe_row_entry):
Test predicate to determine whether SFrame RA tracking is used.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Neither ".cfi_offset SP, <offset>", ".cfi_register SP, <regno>", nor
".cfi_val_offset SP, <offset>" alter the tracking information to recover
the stack pointer (SP). Doing so would need an explicit .cfi_def_cfa,
which SFrame tracks.
The stack pointer (SP) register contents on entry can be reconstructed
from the SFrame CFA tracking information using information from the
current and initial SFrame FREs of the SFrame FDE:
1. Compute CFA from the current CFA base register (SP or FP) and CFA
offset from the SFrame CFA tracking information from the SFrame FRE
for the current instruction address:
CFA = <current_base_reg> + <current_cfa_offset>
2. Compute SP from the current CFA and the CFA offset from the SFrame
CFA tracking information from the initial SFrame FRE of the FDE:
SP = CFA - <initial_cfa_offset>
While at it add comments to the processing of .cfi_offset and
.cfi_val_offset that the SP can be reconstructed from the CFA tracking
information.
gas/
* gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame
FDE if .cfi_register specifies SP register.
(sframe_xlate_do_offset,sframe_xlate_do_val_offset): Add comment
that this is likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Do not skip SFrame FDE if .cfi_register specifies RA register without
RA tracking being actually used. Without RA tracking the register
contents can always be restored from the stack using the fixed
RA offset from CFA.
gas/
* gen-sframe.c (sframe_xlate_do_register): Do not skip SFrame
FDE if .cfi_register specifies RA register without RA tracking
being used.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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CFI opcode DW_CFA_AARCH64_negate_ra_state is multiplexed with
DW_CFA_GNU_window_save. Process DW_CFA_AARCH64_negate_ra_state on
AArch64. Skip generation of SFrame FDE otherwise with the following
warning message:
skipping SFrame FDE; .cfi_window_save
gas/
* gen-sframe.c: Skip SFrame FDE if .cfi_window_save.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The SFrame format cannot represent the frame pointer (FP) being saved
on the stack without the return address (RA) also being saved on the
stack, if RA tracking is used.
A SFrame FDE is followed by 1-3 offsets with the following information:
Without RA tracking:
1. Offset from base pointer (SP or FP) to locate the CFA
2. Optional: Offset to CFA to restore the frame pointer (FP)
With RA tracking:
1. Offset from base pointer (SP or FP) to locate the CFA
2. Optional: Offset to CFA to restore the return address (RA)
3. Optional: Offset to CFA to restore the frame pointer (FP)
When RA tracking is used and a FDE is followed by two offsets the
SFrame format does not provide any information to distinguish whether
the second offset is the RA or FP offset. SFrame assumes the offset to
be the RA offset, which may be wrong.
Therefore skip generation of SFrame FDE information and print the
following warning, if RA tracking is used and the FP is saved on the
stack without the RA being saved as well:
skipping SFrame FDE; FP without RA on stack
gas/
* gen-sframe.c (sframe_do_fde): Skip SFrame FDE if FP without RA
on stack, as the SFrame format cannot represent this case.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The following generic warning message, which is printed whenever the
assembler skips generation of SFrame FDE, is not very helpful for the
user:
skipping SFrame FDE; CFI insn <name> (0x<hexval>)
Whenever possible print meaningful warning messages, when the assembler
skips generation of SFrame FDE:
- skipping SFrame FDE; non-SP/FP register <regno> in .cfi_def_cfa
- skipping SFrame FDE; non-SP/FP register <regno> in
.cfi_def_cfa_register
- skipping SFrame FDE; .cfi_def_cfa_offset without CFA base register
in effect
- skipping SFrame FDE; {FP|RA} register <regno> in .cfi_val_offset
- skipping SFrame FDE; {SP|FP|RA} register <regno> in in .cfi_register
- skipping SFrame FDE; .cfi_remember_state without prior SFrame FRE
state
- skipping SFrame FDE; non-default RA register <regno>
gas/
* gen-sframe.h (SFRAME_FRE_BASE_REG_INVAL): New macro for
invalid SFrame FRE CFA base register value of -1.
* gen-sframe.c: User readable warnings if SFrame FDE is not
generated.
gas/testsuite/
* gas/cfi-sframe/common-empty-1.d: Update generic SFrame test
case to updated warning message texts.
* gas/cfi-sframe/common-empty-2.d: Likewise.
* gas/cfi-sframe/common-empty-3.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Refactor SFrame processing of CFI opcode DW_CFA_register into a separate
function. This harmonizes the CFI opcode processing.
While at it reword the comment on CFI opcodes that are not processed.
This is a purely mechanical change.
gas/
* gen-sframe.c (sframe_do_cfi_insn, sframe_xlate_do_register):
Refactor SFrame CFI opcode DW_CFA_register processing.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Print a warning message if SFrame FDE is skipped due to a non-default
DWARF return column (i.e. return address (RA) register number). This
may be caused by the use of CFI directive .cfi_return_column with a
non-default return address (RA) register number in the processed
assembler source code.
Warning: skipping SFrame FDE due to non-default DWARF return column
gas/
* gen-sframe.c: Warn if SFrame FDE is skipped due to non-default
DWARF return column.
gas/testsuite/
* gas/cfi-sframe/common-empty-3.d: Update test case to expect
for new warning message when SFrame FDE is skipped due to
a non-default DWARF return column.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Do not generate SFrame FDE if DWARF CFI directives .cfi_def_cfa or
.cfi_def_cfa_register specify a CFA base register number other than
the architecture-specific stack-pointer (SP) or frame-pointer (FP)
register numbers.
This also causes the assembler to print a warning message, so that
skipping of the SFrame FDE does not occur silently.
Update the generic ld SFrame test case to be architecture independent.
Do not use CFI directive .cfi_def_cfa, as the specified CFA base
register number is not a valid SP/FP register number on all
architectures. An invalid SP/FP register number will now cause the
assembler to print a warning message and skip SFrame FDE generation.
Remove the offending CFI directive, that cannot be coded architecture-
independent, as the test case requires SFrame information to be
generated. This was reported by the Linaro-TCWG-CI for AArch64.
gas/
* gen-sframe.c: Skip SFrame generation if CFI specifies
non-FP/SP base register.
ld/testsuite/
* ld-sframe/discard.s: Update generic SFrame test case to be
architecture independent.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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SFrame generation prints the DWARF call frame instruction opcode in
hexadecimal. Leverage get_DW_CFA_name to additionally print the
DWARF call frame instruction name in human readable form, while also
respecting fake CFI types. Use "(unknown)", if the DWARF call frame
instruction name is not known.
While at it use the terminology "instruction" for these DW_CFA_*, as
suggested by Indu.
This changes the following assembler SFrame generation warning message
as follows:
Old:
Warning: skipping SFrame FDE due to DWARF CFI op 0x<hexval>
New:
Warning: skipping SFrame FDE; CFI insn <name> (0x<hexval>)
gas/
* gen-sframe.c (sframe_get_cfi_name): New function to get the
DWARF call frame instruction name for a DWARF call frame
instruction opcode.
(sframe_do_cfi_insn): Use sframe_get_cfi_name to print the
DWARF call frame instruction name for the DWARF call frame
instruction opcode in the warning message.
gas/testsuite/
* gas/cfi-sframe/common-empty-1.d: Update expected SFrame
warning message text for DWARF call frame insn name.
* gas/cfi-sframe/common-empty-2.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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For the SFrame FRE frame-pointer (FP) offset from CFA a 'u' is displayed
if it is unavailable.
For the SFrame FRE return-address (RA) offset from CFA a 'u' was
displayed if the ABI uses a fixed RA offset from CFA. By chance a
'u' was also displayed if the RA offset is unavailable, as the string
buffer was not initialized after formatting the FP offset. Note that it
could not occur that the FP offset was erroneously displayed as RA
offset, as the SFrame format cannot have a FRE with FP offset without
RA offset.
For the FRE RA offset display 'f' if the ABI uses a fixed RA offset
from CFA. Display a 'u' if it is unavailable.
libsframe/
* sframe-dump.c: Display SFrame fixed RA offset as 'f' in dump.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe-common-4.d: Test for RA displayed
either as 'u' (if RA tracking) or as 'f' (fixed RA offset if no
RA tracking).
* gas/cfi-sframe/cfi-sframe-common-5.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-6.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-7.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-8.d: Likewise.
* gas/cfi-sframe/cfi-sframe-x86_64-1.d: Test for RA displayed
as 'f' (fixed RA offset), as x86-64 does not use RA tracking.
* gas/scfi/x86_64/scfi-cfi-sections-1.d: Likewise.
* gas/scfi/x86_64/scfi-dyn-stack-1.d: Likewise.
ld/testsuite/
* ld-x86-64/sframe-plt-1.d: Test for RA displayed as 'f' (fixed
RA offset), as x86-64 does not use RA tracking.
* ld-x86-64/sframe-simple-1.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The SFrame format allows architectures to specify fixed offsets from the
CFA, if any, from which the frame pointer (FP) and/or return address
(RA) may be recovered. These offsets are stored in the SFrame header.
For instance the SFrame generation in the assembler for x86 AMD64
specifies a fixed offset from the CFA, from which the return address
(RA) may be recovered.
When dumping the SFrame header, for instance in readelf/objdump with
option --sframe, do also dump the specified fixed offsets from the CFA,
if any, from which the frame pointer (FP) and return address (RA) may
be recovered.
Update the common SFrame test case verification patterns to allow for
the optional dumping of the CFA fixed FP/RA offsets. Update the x86-
specific SFrame and SCFI test case verification patterns to require a
CFA fixed RA offset of -8.
libsframe/
* sframe-dump.c: Dump CFA fixed FP and RA offsets.
gas/testsuite/
* gas/cfi-sframe/cfi-sframe-common-1.d: Test for optional fixed
FP and RA offsets.
* gas/cfi-sframe/cfi-sframe-common-2.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-3.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-4.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-5.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-6.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-7.d: Likewise.
* gas/cfi-sframe/cfi-sframe-common-8.d: Likewise.
* gas/cfi-sframe/cfi-sframe-x86_64-1.d: Test for fixed
RA offset.
* gas/cfi-sframe/common-empty-1.d: Test for optional fixed
FP and RA offsets.
* gas/cfi-sframe/common-empty-2.d: Likewise.
* gas/cfi-sframe/common-empty-3.d: Likewise.
* gas/scfi/x86_64/scfi-cfi-sections-1.d: Test for SFrame fixed
RA offset.
* gas/scfi/x86_64/scfi-dyn-stack-1.d: Likewise.
ld/testsuite/
* ld-x86-64/sframe-plt-1.d: Test for SFrame fixed RA offset.
* ld-x86-64/sframe-simple-1.d: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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Explicitly mention "SFrame" in the descriptions for the architecture-
specific SFrame configuration macros, variables, and functions.
Use the term "frame pointer" (FP) instead of "base pointer". This aligns
with the terminology used in the SFrame specification. Additionally it
helps not to confuse "base-pointer register" with the term "BASE_REG"
used in the specification to denote either the SP or FP register.
Specify what the SFRAME_CFA_*_REG register numbers are used for:
- SP (stack pointer): CFA tracking
- FP (frame pointer): CFA and FP tracking
- RA (return address): RA tracking
Align the descriptions for definitions in the source files to the
declarations in the header files.
gas/
* config/tc-aarch64.h: Enhance architecture-specific SFrame
configuration descriptions.
* config/tc-aarch64.c: Likewise.
* config/tc-i386.h: Likewise.
* config/tc-i386.c: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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gas/
* config/tc-i386.c (x86_sframe_cfa_ra_reg): Remove.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
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The CMOVcc instruction proposed by EVEX has four different forms,
corresponding to the four possible combinations of EVEX.ND and EVEX.NF
values.
In the encoder part, when the CFCMOV template supports EVEX_NF, it means that
it requires EVEX.NF to be 1.
In the decoder part, CFCMOV_Fixup is used to reverse source and destination
operands in the 2-operand case.
gas/ChangeLog:
* config/tc-i386.c (build_apx_evex_prefix): Set NF bit for cfcmov
when the insn template supports EVEX_NF.
* testsuite/gas/i386/x86-64-apx-inval.l: Add invalid tests for cfcmov.
* testsuite/gas/i386/x86-64-apx-inval.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Add tests for cfcmov and cmov.
* testsuite/gas/i386/x86-64-apx-cfcmov-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-cfcmov.d: Ditto.
* testsuite/gas/i386/x86-64-apx-cfcmov.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Add cfcmov instructions.
* i386-dis.c (CFCMOV_Fixup): Special handling of cfcmov.
(putop): Print 'cf' for cfcmov instructions.
* i386-opc.h (EVEX_NF): New.
* i386-opc.tbl: Add cfcmov instructions.
* i386-mnem.h: Regerated.
* i386-tbl.h: Regerated.
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gas/
* testsuite/gas/riscv/imply.s: New testcase for all imply cases.
* testsuite/gas/riscv/imply.d: Likewise.
* testsuite/gas/riscv/march-imply-i.s: Renamed to
imply-zicsr-zifencei.s.
* testsuite/gas/riscv/march-imply-i2p0-02.d: Renamed to
imply-zicsr-zifencei-i2p0-misa-spec-2p2.d.
* testsuite/gas/riscv/march-imply-i2p1-01.d/l: Renamed to
imply-zicsr-zifencei-i2p1-misa-spec-20191213.d.
* testsuite/gas/riscv/march-imply-i2p0-01.d: Removed.
Combined into new imply testcase.
* testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise.
* testsuite/gas/riscv/march-imply-a.d: Likewise.
* testsuite/gas/riscv/march-imply-b.d: Likewise.
* testsuite/gas/riscv/march-imply-f.d: Likewise.
* testsuite/gas/riscv/march-imply-g.d: Likewise.
* testsuite/gas/riscv/march-imply-h.d: Likewise.
* testsuite/gas/riscv/march-imply-q.d: Likewise.
* testsuite/gas/riscv/march-imply-smcsrind.d: Likewise.
* testsuite/gas/riscv/march-imply-smstateen.d: Likewise.
* testsuite/gas/riscv/march-imply-unsupported.d: Likewise.
* testsuite/gas/riscv/march-imply-v.d: Likewise.
* testsuite/gas/riscv/march-imply-zcd.d: Likewise.
* testsuite/gas/riscv/march-imply-zcf.d: Likewise.
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Matches what both fb_label_name and dollar_label_name use.
* symbols.c (decode_local_label_name): Use unsigned variables.
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gas/
* doc/c-riscv.texi: Fixed typo of `.insn cj' format.
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Support APX NF TLS IE with 2 operands.Verify it with ld and gold.
gas/
* config/tc-i386.c (md_assemble): Allow APX NF TLS IE with
2 operands.
* testsuite/gas/i386/x86-64-gottpoff.d: Updated.
* testsuite/gas/i386/x86-64-gottpoff.s: Add APX NF TLS IE
tests with 2 operands.
gold/
* testsuite/x86_64_ie_to_le.s: Add APX NF TLS IE tests with
2 operands.
* testsuite/x86_64_ie_to_le.sh: Updated.
ld/
* testsuite/ld-x86-64/tlsbindesc.s: Add APX NF TLS IE tests
with 2 operands.
* testsuite/ld-x86-64/tlsbindesc.d: Updated.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
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gas/
* doc/c-riscv.texi: Fixed syntax of `.option arc'h when reseting whole
architecture. Don't need the `=' before ISA.
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Verify that
{nf} add %reg1, foo@gottpoff(%rip), %reg2
{nf} add foo@gottpoff(%rip), %reg, %reg2
work correctly with ld and gold.
gas/
* testsuite/gas/i386/x86-64-gottpoff.d: Updated.
* testsuite/gas/i386/x86-64-gottpoff.s: Add tests for
"{nf} add %reg1, foo@gottpoff(%rip), %reg2" and
"{nf} add foo@gottpoff(%rip), %reg, %reg2".
gold/
* testsuite/x86_64_ie_to_le.s: Add tests for
"{nf} add %reg1, foo@gottpoff(%rip), %reg2" and
"{nf} add foo@gottpoff(%rip), %reg, %reg2".
* testsuite/x86_64_ie_to_le.sh: Updated.
ld/
* testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_6_GOTTPOFF
for APX NF tests.
* testsuite/ld-x86-64/tlsbindesc.d: Updated.
* testsuite/ld-x86-64/tlsbindesc.rd: Likewise.
Co-Authored-By: H.J. Lu <hjl.tools@gmail.com>
Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
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The new -march=armv9.5-a flag enables access to the
mandatory cpa, lut and faminmax extensions.
Existing test cases for features are extended to verify they
work without additional flags.
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With both sources being registers, these insns are almost commutative;
the only extra adjustment needed is inversion of the encoded condition.
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The same properties apply there.
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..., for differing only in the resulting EFLAGS, which are left
untouched anyway. That's a shorter encoding, available as long as
certain constraints on operands are met; see code comments. (SHL-by-1
forms may then be subject to further optimization that was introduced
earlier.)
Note that kind of as a side effect this also converts multiplication by
1 to shift by 0, which is a plain move or even no-op anyway. That could
be further shrunk (as could be presence of shifts/rotates by 0 in the
original code as well as a fair set of other {nf}-form insns), yet the
expectation (for now) is that people won't write such code in the first
place.
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Avoid changing the encoding when there's no size gain: If there's a REX
or REX2 prefix anyway and the base opcode wouldn't be changed, dropping
just REX.W / REX2.W has no (size) effect. (Same for the AND-by-imm7 case
in the same big conditional.)
While there also pull out the .qword check: For the 2-register-operands
case whether that's done on the 1st or 2nd operand doesn't matter. Due
to reduction in necessary parentheses this improves readability a tiny
bit.
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..., as that leaves EFLAGS untouched anyway. That's a shorter encoding,
available as long as certain constraints on operand size and registers
are met; see code comments.
Note that this requires deferring to derive encoding_evex from {nf}
presence, as in optimize_encoding() we want to avoid touching the insns
when {evex} was also used.
Note further that this requires want_disp32() to now also consider the
opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still
report the original mnemonic (or else things can get confusing). While
there, correct adjacent mis-indentation.
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Unlike for the legacy forms, where there's a difference in the resulting
EFLAGS.CF, for the NF variants the immediate can be got rid of in that
case by switching to a 1-bit rotate in the opposite direction.
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