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20 hoursPowerPC: Add support for RFC02677 - VSX Vector Rotate Left WordPeter Bergner2-0/+2
opcodes/ * ppc-opc.c (powerpc_opcodes): Add xvrlw. gas/ * testsuite/gas/ppc/future.s: Add test for xvrlw. * testsuite/gas/ppc/future.d: Likewise.
26 hoursarm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M MainlineAndre Vieira3-1/+231
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR instructions when assembling for Armv8.1-M Mainline, as well as adding the corresponding support for disassembling instructions that use it.
43 hoursRISC-V: Add Zcmt instructions and csr.Jiawei14-0/+93
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
3 daysSupport x86 Intel MSR_IMMHu, Lin112-11/+145
gas/ChangeLog: * NEWS: Support x86 Intel MSR_IMM. * config/tc-i386.c (cpu_arch): Add MSR_IMM. (cpu_flags_match): Add MSR_IMM to APX_F related processing. (i386_assemble): WRMSRNS's first operand is imm32, so add MN_wrmsrns like MN_uwrmsr. * doc/c-i386.texi: Document .msr_imm. * testsuite/gas/i386/i386.exp: Run MSR_IMM tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/msr_imm-inval.l: New test. * testsuite/gas/i386/msr_imm-inval.s: Ditto. * testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.d: Ditto. * testsuite/gas/i386/x86-64-msr_imm.s: Ditto. opcodes/ChangeLog: * i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0, PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64, X86_64_VEX_MAP7_F6_L_0_W_0_R_0, VEX_LEN_MAP7_F6, VEX_W_MAP7_F6_L_0. (reg_table): New entry for MSR_IMM. (prefix_table): Ditto. (x86_64_table): Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (map7_f6_opcode): New variable for MAP7. (get_valid_dis386): Support MAP7. * i386-gen.c (cpu_flags): Add MSR_IMM. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (i386_cpu_flags): Add cpumsr_imm. * i386-opc.tbl: Add MSR_IMM instructions. * i386-tbl.h: Regenerated.
3 daysx86: rename SPACE_{,E}VEX_MAP<N>Jan Beulich1-21/+21
Map7 already has dual purpose for USER-MSR (and is to gain more for MSR-IMM), while Map5 is about to gain VEX uses for AMX extensions. Drop the not really meaningful infixes and (in the opcode table) prefixes, retaining merely EVexMap4 for encoding EVex128 at the same time.
3 daysx86: VP2INTERSECT{D,Q} have mask register destination groupJan Beulich16-244/+293
Much like AVX512-{4FMAPS,4VNNIW} have a constraint on their register source, there's a constraint (need to be even) on the destination register here. Adjust "good" test cases accordingly, and add a new test case to check the warning.
3 daysx86: generalize "implicit quad group" handlingJan Beulich6-33/+67
We'll want to re-use it for VP2INTERSECT{D,Q}. While there add a testcase for the similarly affected AVX512-4VNNIW insns.
3 daysgas: move had_errors() invocation in finishing of subsegsJan Beulich1-6/+6
Invoking this repeatedly in an inner loop is not only inefficient, but may lead to inconsistencies in e.g. the listings that the original comment author cared about. (Accept potential inconsistencies across distinct sections though, to cover all invocations of the function.)
3 daysELF: SHF_STRINGS isn't really tied to SHF_MERGEJan Beulich3-23/+28
It's not overly useful without it, but the spec doesn't name any dependency between the two. People may want to use it for purely informational purposes, for example. Adjust, in particular, entity size processing to be engaged if either flag is set, as mandated by the spec.
3 daysELF: SHF_MERGE vs SHT_NOBITSJan Beulich1-0/+3
bfd/merge.c puts in quite some effort to track mergable sections. That's all wasted for sections which don't have contents, as for them _bfd_write_merged_section() will never be called. With the combination not having any useful effect, also warn about this in gas.
3 daysgas/ELF: also reject merge entity size being zeroJan Beulich1-1/+1
This won't have any useful effect, so is at best marginally less bogus than a negative value. The change actually points out a flawed (for Arm) testcase: @ is a comment character there.
3 dayss390: Add arch15 Concurrent-Functions Facility insnsJens Remus2-0/+8
opcodes/ * s390-opc.txt: Add arch15 Concurrent-Functions Facility instructions. * s390-opc.c (INSTR_SSF_RRDRD2, MASK_SSF_RRDRD2): New SSF instruction format variant. gas/testsuite/ * gas/s390/zarch-arch15.d: Tests for arch15 Concurrent-Functions Facility instructions. * gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
9 daysgas: add .cv_ucomp and .cv_scomp pseudo-directivesMark Harmstone8-1/+356
Add .cv_ucomp and .cv_scomp pseudo-directives for object files for Windows targets, which encode compressed CodeView integers according to the algorithm in CVCompressData in https://github.com/Microsoft/microsoft-pdb/blob/master/include/cvinfo.h. This is essentially Microsoft's answer to the LEB128, though used in far fewer places. CodeView uses these to encode the "binary annotations" in the S_INLINESITE symbol, which express the relationship between code offsets and line numbers in inlined functions. This has to be done in the assembler as GCC doesn't know how many bytes each instruction takes up. There's no equivalent for this for MSVC or LLVM, as in both cases the assembler and compiler are integrated. .cv_ucomp represents an unsigned big-endian integer between 0 and 0x1fffffff, taking up 1, 2, or 4 bytes: Value between 0 and 0x7f: 0aaaaaaa -> 0aaaaaaa (identity-mapped) Value between 0x80 and 0x3fff: 00aaaaaa bbbbbbbb -> 10aaaaaa bbbbbbbb Value between 0x4000 and 0x1fffffff: 000aaaaa bbbbbbbb ccccccccc dddddddd -> 110aaaaa bbbbbbbb ccccccccc dddddddd .cv_scomp represents a signed big-endian integer between -0xfffffff and 0xfffffff, encoded according to EncodeSignedInt32 in cvinfo.h. The absolute value of the integer is shifted left one bit, the LSB set for a negative value, and the result expressed as if it were a .cv_ucomp: cv_scomp(x) = cv_ucomp((abs(x) << 1) | (x < 0 ? 1 : 0))
13 daysaarch64: testsuite: remove hard-coded instruction addressesMatthieu Longo1-26/+26
13 daysaarch64: remove redundant register type R_NMatthieu Longo1-5/+1
The register type R_N is redundant with R_ZR_SP. This patch removes it, and replaces its usage by R_ZR_SP.
13 daysaarch64: constify unchanged char* argumentsMatthieu Longo1-1/+1
13 daysarm, objdump: print obsolote warning when 26-bit set in instructionsAndre Vieira5-76/+36
Arm has obsoleted the 26-bit addressing mode. Diagnose this when disasembling these instructions by printing OBSOLETE.
13 daysarm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira4-17/+19
For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
2024-11-07arm: Skip two failing tests for wince & pe targetsAndre Simoes Dias Vieira2-0/+2
We don't seem to support any m-profile assembly/disassembly tests for wince or pe, so skipping the pacbti one too. The pr29494 test needs to be skipped because it uses assembly syntax that is not supported in wince/pe like for instance eabi_attribute directives.
2024-11-06PowerPC: Merge rfc2655 and rfc2656 test cases into one future test casePeter Bergner5-32/+18
gas/ * testsuite/gas/ppc/rfc02655.[ds]: Rename from this... * testsuite/gas/ppc/future.[ds]: ... to this. * testsuite/gas/ppc/rfc02656.[ds]: Delete. Move tests to future.[ds]. * testsuite/gas/ppc/ppc.exp: Update for file name changes.
2024-10-31gas/doc/riscv: Fixed misaligned instruction tableNelson Chu1-42/+42
gas/ * doc/c-riscv.texi: Fixed misaligned instruction table.
2024-10-30x86: add a helper to copy insn operand infoJan Beulich1-133/+44
We're doing such in fairly many places, and yet more are likely to appear; centralize the logic, much like we already have swap_2_operands(). While there also correct mis-indentation in adjacent code in process_operands().
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich5-8/+51
Without this APX support isn't really complete. For Intel syntax displacement form is needed, such that symbolic operands won't need prefixing by "offset". (The other form is actually not used at all in Intel syntax.) For the record: To restrict displacement form to Intel syntax is not something I actually agree with.
2024-10-30x86/APX: squash REX prefix when REX2 is being emittedJan Beulich3-1/+13
We should not (silently) emit a REX prefix ahead of a REX2-encoded insn; such encodings are illegal. Best we can do is fold the REX bits into the REX2 prefix, and then zap the REX one from i.prefix[].
2024-10-29LoongArch: Corrected to GNU style codeLulu Cai1-10/+10
2024-10-29gas: make fix_new_exp()'s "exp" parameter constJan Beulich2-16/+4
This really should be only an input; in particular it looks bogus that O_add expressions are even altered. That altering and the recursion are even pointless: Once expanding what the inner call would do (with O_symbol) it becomes clear that this is no different than the default case. Simplify the code accordingly, retaining the comment.
2024-10-29gas: constify md_{short,long}opts and md_longopts_sizeJan Beulich78-237/+232
First of all make the declarations globally visible, such that producer and consumer actually share them. For the latter two simply add const (as PPC already had it,), while for the former achieve the effect by converting to an array: There's no need for the extra level of indirection.
2024-10-29RISC-V: Update the doc to match ISA manualKito Cheng1-36/+36
ISA manual use funct* rather than func*[1] (e.g. funct7 rather than func7), and I realized that may something I typo at beginning when I write the patch for `.insn` support...:P [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/rv32.adoc#integer-register-register-operations
2024-10-28RISC-V: Fix typo in gas/testsuite/gas/riscv/mapping.sJim Lin3-6/+6
gas/ * gas/riscv/mapping.s: Fix typo. * gas/riscv/mapping-dis.d: Fix typo. * gas/riscv/mapping-symbols.d. Fix typo.
2024-10-24Replace uses of asprintf with xasprintfAlan Modra7-49/+11
xasprintf has a nicer interface and behaves like xmalloc as far as memory is concerned, ie. no need to check a return status and the program exits with an error on OOM. binutils/ * dwarf.c (load_debug_sup_file): Replace asprintf with xasprintf. * nm.c (get_elf_symbol_type, get_coff_symbol_type): Likewise. * objdump.c (dump_ctf_indent_lines): Likewise. * readelf.c (display_lto_symtab, dump_ctf_indent_lines): Likewise. * windres.c (main): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. gas/ * config/tc-kvx.c (kvx_emit_single_noop): Simplify. * config/tc-riscv.c (md_assemblef): Replace asprintf with xasprintf. * read.c (s_nop, do_s_func): Likewise. * stabs.c (stabs_generate_asm_func): Likewise. (stabs_generate_asm_endfunc): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate. ld/ * ldlang.c (lang_leave_overlay_section): Replace xmalloc+sprintf with xasprintf. Localise vars. * lexsup.c (parse_args): Replace asprintf with xasprintf. * pe-dll.c (make_head, make_tail, make_one): Likewise. (make_singleton_name_thunk, make_import_fixup_entry): Likewise. (make_runtime_pseudo_reloc): Likewise. (pe_create_runtime_relocator_reference): Likewise. * configure.ac: Remove asprintf from AC_CHECK_DECLS. * config.in: Regenerate. * configure: Regenerate.
2024-10-22LoongArch: Force relocation for every reference to the global offset tableLulu Cai4-0/+75
Local absolute symbols are resolved at assembly stage and the symbol value is placed in the relocation addend. But non-zero addend will cause an assertion failure during linking. Forces emission of relocations to defer resolution of local abs symbols until link time. bfd/ * elfnn-loongarch.c (loongarch_elf_relax_section): Determine absolute symbols in advance to avoid ld crash. gas/ * config/tc-loongarch.c (loongarch_force_relocation): New function to force relocation. * config/tc-loongarch.h (TC_FORCE_RELOCATION): New macros to force relocation. (loongarch_force_relocation): Function declaration. * testsuite/gas/loongarch/localpic.d: New test. * testsuite/gas/loongarch/localpic.s: New test.
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc6-2/+28
gas/ChangeLog: * NEWS: Support ZHAOXIN GMI instructions. * config/tc-i386.c: Add gmi. * doc/c-i386.texi: Document gmi. * testsuite/gas/i386/i386.exp: Add gmi test. * testsuite/gas/i386/gmi.d: Ditto. * testsuite/gas/i386/gmi.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New comment. * i386-gen.c: Add gmi. * i386-opc.h (CpuGMI): New. * i386-opc.tbl: Add Zhaoxin GMI instructions. * i386-tbl.h: Regenerated. * i386-mnem.h: Ditto. * i386-init.h: Ditto.
2024-10-16Support Intel AVX10.2 convert instructionsLiwei Xu14-0/+1292
In this patch, we will support AVX10.2 convert instructions. All of them are new instruction forms. Among all the instructions, vcvtbiasph2[b,h]f8[,s] needs extra care. Since Operand 2 could indicate memory size, we do not need suffix under ATTmode. However, we could not fold all three templates but only XMM/YMM since the dst operand size are the same for them. Also, a new iterator <cvt8> is added to reduce redundancy. gas/ * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-cvt-intel.d: New. * testsuite/gas/i386/avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/avx10_2-512-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-cvt.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-cvt.s: Ditto. opcodes/ * i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F3874, PREFIX_EVEX_MAP5_18, PREFIX_EVEX_MAP5_1B, PREFIX_EVEX_MAP5_1E and PREFIX_EVEX_MAP5_74. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c (MOD_EVEX_0F38B1): New. (PREFIX_EVEX_0F3874): Ditto. (PREFIX_EVEX_MAP5_18): Ditto. (PREFIX_EVEX_MAP5_1B): Ditto. (PREFIX_EVEX_MAP5_1E): Ditto. (PREFIX_EVEX_MAP5_74): Ditto. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Kong Lingling <lingling.kong@intel.com> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
2024-10-15x86: Refine instruction check in x86_check_tls_relocationCui, Lili1-10/+11
gas/ChangeLog: * config/tc-i386.c (x86_check_tls_relocation): Refine instruction check.
2024-10-15x86/testsuite: Rename AVX10.2 media testcasesHaochen Jiang14-12/+12
Change these testcase name to make them clearer. gas/ChangeLog: * testsuite/gas/i386/avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/avx10_2-256-media.d: ...this. * testsuite/gas/i386/avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/avx10_2-256-media.s: ...this. * testsuite/gas/i386/avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/avx10_2-512-media.d: ...this. * testsuite/gas/i386/avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/avx10_2-512-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-256-media.s: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media-intel.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.d: ...this. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Renamed to... * testsuite/gas/i386/x86-64-avx10_2-512-media.s: ...this. * testsuite/gas/i386/i386.exp: Change testcase name. * testsuite/gas/i386/x86-64.exp: Ditto.
2024-10-14ia64/ELF: fix HPUX testsuite falloutJan Beulich3-13/+13
... from 1f1b5e506bf0 ("bfd/ELF: restrict file alignment for object files"), as noticed / reported by Alan.
2024-10-14gas: drop SKIP_WHITESPACE_AFTER_NAME()Jan Beulich21-98/+85
Exclusively all users should use restore_line_pointer() instead, at which point SKIP_WHITESPACE() suffices as a check afterwards.
2024-10-14LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bugLulu Cai3-1/+20
The enum BFD_RELOC_[32/64] was mistakenly used in the macro instead of the relocation in fixp. This can cause the second relocation of a pair to be deleted when -mthin-add-sub is enabled. Apply the correct macro to fix this. Also sets the initial value of -mthin-add-sub.
2024-10-11x86: bring 64-bit-only cmdline option handling in syncJan Beulich1-2/+8
--64 and --x32 are already suppressed in --help output when BFD64 is not defined. Also avoid recognizing these options in such configurations.
2024-10-11bfd/ELF: restrict file alignment for object filesJan Beulich5-18/+18
While for executables properly aligning sections within the file can be quite relevant, the same is of pretty little importance for relocatable object files. Avoid passing "true" into _bfd_elf_assign_file_position_for_section() when dealing with object files, but compensate minimally by applying log_file_align in such cases as a cap to the alignment put in place.
2024-10-11Support Intel AVX10.2 media instructionsHaochen Jiang18-0/+1604
In disassembler part, for vnni instructions, we extended previous VEX part using %XE in disassembler to promote them to EVEX by reusing the original VEX table. For vmpsadbw, we will also use %XE. However, it is hard to reuse the VEX table, so we are using new ones. In assmbler part, we put the vnni table entries with previous vnni instructions since they are just promotion from AVX-VNNI-INT{8,16}. Since we will prefer VEX encoding, we need to use the different table order in template <vnni>, which prefers EVEX due to earlier introduction for AVX512_VNNI than AVX_VNNI. This means a new <vnni>. For vdpphps and vmpsadbw, we put them at the end of the table, with future AVX10.2 instructions. Nit: I will remove the arch requirement for avx_vnni_int{8,16} in evex-promote testcases after AVX10.2 implies AVX-VNNI-INT{8,16}. gas/Changelog: * testsuite/gas/i386/i386.exp: Add AVX10.2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/avx10_2-256-1-intel.d: New. * testsuite/gas/i386/avx10_2-256-1.d: Ditto. * testsuite/gas/i386/avx10_2-256-1.s: Ditto. * testsuite/gas/i386/avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.d: Ditto. * testsuite/gas/i386/avx10_2-512-1.s: Ditto. * testsuite/gas/i386/avx10_2-promote.d: Ditto. * testsuite/gas/i386/avx10_2-promote.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-256-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1-intel.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-512-1.s: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.d: Ditto. * testsuite/gas/i386/x86-64-avx10_2-promote.s: Ditto. opcodes/Changelog: * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F3852. Add PREFIX_EVEX_0F3A42_W_0. * i386-dis-evex-w.h: Adjust EVEX_W_0F3A42. * i386-dis-evex.h: Add table pass for AVX10.2 instructions. * i386-dis.c: Adjust PREFIX_VEX_0F3850_W_0, PREFIX_VEX_0F3851_W_0, PREFIX_VEX_0F38D2_W_0 and PREFIX_VEX_0F38D3_W_0. * i386-opc.tbl: Add AVX10.2 instructions. * i386-mnem.h: Regenerated. * i386-tbl.h: Ditto. Co-authored-by: Lili Cui <lili.cui@intel.com>
2024-10-10s390: Add arch15 instructionsAndreas Krebbel6-4/+206
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-10-08RISC-V: Fix implicit dependency of Zabha and ZacasXiao Zeng1-2/+2
1 Zabha depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc> 2 Zacas depends on Zaamo: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc> bfd/ChangeLog: * elfxx-riscv.c: Zabha and Zacas implicitly depend on Zaamo. gas/ChangeLog: * testsuite/gas/riscv/imply.d: Updated. Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
2024-10-04gas: hide emulation struct format_ops instances when not neededJan Beulich7-114/+131
Most targets don't even support emulations, so this data (and certain functions) are entirely dead code for them.
2024-10-04x86: prune OBJ_MAYBE_... usesJan Beulich3-169/+113
With the removal of emulations, OBJ_MAYBE_... can no longer be defined. Tidy code wherever they're used, which also includes the dropping of most IS_ELF and uses and checks of OUTPUT_FLAVOR. Where touching such constructs anyway, also drop TE_PEP checks when used together with TE_PE ones (the former implies the latter).
2024-10-04x86: drop largely defunct gas emulationsJan Beulich10-185/+2
Both ELF and COFF have various sub-flavors, each of which would then require its own emulation: Right now when configuring a COFF/PE secondary target (with perhaps an ELF primary one), one gets plain COFF emulation rather than COFF/PE one. As such a multitude of emulations would be unwieldy (and likely fragile) drop gas emulations altogether instead.
2024-10-04include: de-duplicate i386.h and x86_64.hJan Beulich1-6/+1
Move common definitions to a new x86.h, thus allowing gas'es obj-coff.h to include just that, getting rid of a TE_PEP compile-time dependency.
2024-10-04gas: drop generate_asm_lineno emulation hookJan Beulich5-14/+0
It's not wired up, so can't be used.
2024-10-04gas: don't use COFF-specific SF_SET_LOCAL() directly from read.cJan Beulich8-3/+23
Make this a proper obj-format hook instead.
2024-10-04gas/dw2gencfi: correct .sframe section conditionalJan Beulich1-6/+5
While originally this was in preparation of a subsequent change making SUPPORT_FRAME_LINKONCE potentially dependent on a global variable, the construct appears unlikely to have been correct in the first place: The variable would have been passed reliably uninitialized when SUPPORT_FRAME_LINKONCE is build-time true. While there correct indentation of the parameters passed to get_cfi_seg().
generated by cgit v1.1 at 2024-11-21 19:43:01 +0000