[binutils][aarch64] Add SVE2 tests

Add tests that SVE2 instructions are encoded as they should be, and tests that invalid instructions have their problems reported. Also check that each sve2 cryptographic extension is required to use the corresponding cryptographic instructions. Finally, test to ensure that sve2 instructions using mnemonics that exist in sve1 still need the sve2 feature to be used. gas/ChangeLog: 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> * testsuite/gas/aarch64/illegal-sve2-aes.d: New test. * testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test. * testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.d: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.l: Test new instructions. * testsuite/gas/aarch64/illegal-sve2.s: Test new instructions. * testsuite/gas/aarch64/sve1-extended-sve2.s: New test. * testsuite/gas/aarch64/sve2.d: Test new instructions. * testsuite/gas/aarch64/sve2.s: Test new instructions.
author: Matthew Malcomson <matthew.malcomson@arm.com> 2019-05-09 10:29:29 +0100
committer: Matthew Malcomson <matthew.malcomson@arm.com> 2019-05-09 10:29:51 +0100
commit: e111c7d1eb8404f29c45f3aa5dbc531062ebbd73 (patch)
tree: 6e85950c386a282064ae0374411d9c34e03c40f0 /gas
parent: 42e6288f9f9d7dfe560d2bed1fb5e7f27ac3256f (diff)
download: gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.zip
gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.tar.gz
gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.tar.bz2
13 files changed, 8621 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2a37acf..fa81e97 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,20 @@
 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
 
+	* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
+	* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
+	* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
+	* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
+	* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
+	* testsuite/gas/aarch64/sve2.d: Test new instructions.
+	* testsuite/gas/aarch64/sve2.s: Test new instructions.
+
+2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
+
 	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
 	operand.
 
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-aes.d b/gas/testsuite/gas/aarch64/illegal-sve2-aes.d
new file mode 100644
index 0000000..8e6daa2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-aes.d
@@ -0,0 +1,20 @@
+#name: Missing SVE2 AES argument
+#as: -march=armv8-a+sve2+sve2-sm4+sve2-sha3+bitperm
+#source: sve2.s
+#error: [^ :]+: Assembler messages:
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesd z17\.b,z17\.b,z21\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesd z0\.b,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aese z17\.b,z17\.b,z21\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aese z0\.b,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesimc z17\.b,z17\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesimc z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesmc z17\.b,z17\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `aesmc z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z17\.q,z21\.d,z27\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.q,z0\.d,z0\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.h,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullb z0\.d,z0\.s,z0\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z17\.q,z21\.d,z27\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.q,z0\.d,z0\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.h,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `pmullt z0\.d,z0\.s,z0\.s'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-bitperm.d b/gas/testsuite/gas/aarch64/illegal-sve2-bitperm.d
new file mode 100644
index 0000000..3009a73
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-bitperm.d
@@ -0,0 +1,19 @@
+#name: Missing SVE2 BITPERM argument
+#as: -march=armv8-a+sve2+sve2-sm4+sve2-sha3+sve2-aes
+#source: sve2.s
+#error: [^ :]+: Assembler messages:
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bdep z17\.b,z21\.b,z27\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bdep z0\.b,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bdep z0\.h,z0\.h,z0\.h'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bdep z0\.s,z0\.s,z0\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bdep z0\.d,z0\.d,z0\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bext z17\.b,z21\.b,z27\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bext z0\.b,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bext z0\.h,z0\.h,z0\.h'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bext z0\.s,z0\.s,z0\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bext z0\.d,z0\.d,z0\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bgrp z17\.b,z21\.b,z27\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bgrp z0\.b,z0\.b,z0\.b'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bgrp z0\.h,z0\.h,z0\.h'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bgrp z0\.s,z0\.s,z0\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `bgrp z0\.d,z0\.d,z0\.d'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-sha3.d b/gas/testsuite/gas/aarch64/illegal-sve2-sha3.d
new file mode 100644
index 0000000..35b0382
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-sha3.d
@@ -0,0 +1,6 @@
+#name: Missing SVE2 SHA3 argument
+#as: -march=armv8-a+sve2+sve2-sm4+sve2-aes+bitperm
+#source: sve2.s
+#error: [^ :]+: Assembler messages:
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `rax1 z17\.d,z21\.d,z27\.d'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `rax1 z0\.d,z0\.d,z0\.d'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-sm4.d b/gas/testsuite/gas/aarch64/illegal-sve2-sm4.d
new file mode 100644
index 0000000..ee3734f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-sm4.d
@@ -0,0 +1,8 @@
+#name: Missing SVE2 SM4 argument
+#as: -march=armv8-a+sve2+sve2-sha3+sve2-aes+bitperm
+#source: sve2.s
+#error: [^ :]+: Assembler messages:
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `sm4e z17\.s,z17\.s,z21\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `sm4e z0\.s,z0\.s,z0\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `sm4ekey z17\.s,z21\.s,z27\.s'
+#error: [^ :]+:[0-9]+: Error: selected processor does not support `sm4ekey z0\.s,z0\.s,z0\.s'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.d b/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.d
new file mode 100644
index 0000000..9f58b2b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.d
@@ -0,0 +1,4 @@
+#name: SVE2 extensions to SVE1 instructions only available in SVE2
+#as: -march=armv8-a+sve
+#source: sve1-extended-sve2.s
+#error_output: illegal-sve2-sve1ext.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.l b/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.l
new file mode 100644
index 0000000..856ca7f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2-sve1ext.l
@@ -0,0 +1,128 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `ext z17\.b,{z21\.b,z22\.b},#221'
+[^ :]+:[0-9]+: Error: selected processor does not support `ext z0\.b,{z0\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `ext z0\.b,{z31\.b,z0\.b},#0'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.d},p5/z,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.d},p0/z,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z17\.s},p5/z,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.s},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1b {z0\.s},p0/z,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z17\.d},p5/z,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1d {z0\.d},p0/z,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.d},p5/z,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.d},p0/z,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z17\.s},p5/z,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.s},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1h {z0\.s},p0/z,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.s},p5/z,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.s},p0/z,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z17\.d},p5/z,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ldnt1w {z0\.d},p0/z,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z17\.h,z21\.h,z3\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z0\.h,z0\.h,z0\.h\[4\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z17\.s,z21\.s,z3\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z17\.d,z21\.d,z11\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mla z0\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z17\.h,z21\.h,z3\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z0\.h,z0\.h,z0\.h\[4\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z17\.s,z21\.s,z3\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z17\.d,z21\.d,z11\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mls z0\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z17\.h,z21\.h,z3\.h\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.h,z0\.h,z0\.h\[4\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z17\.s,z21\.s,z3\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z17\.d,z21\.d,z11\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z17\.b,z21\.b,z27\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `mul z0\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `smulh z17\.b,z21\.b,z27\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `smulh z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `smulh z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `smulh z0\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `smulh z0\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z17\.b,p5,{z21\.b,z22\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z0\.b,p0,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z0\.h,p0,{z0\.h,z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z0\.s,p0,{z0\.s,z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z0\.d,p0,{z0\.d,z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `splice z0\.b,p0,{z31\.b,z0\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqadd z17\.b,p5/m,z17\.b,z21\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqadd z0\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqadd z0\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqadd z0\.s,p0/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqadd z0\.d,p0/m,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqsub z17\.b,p5/m,z17\.b,z21\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqsub z0\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqsub z0\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqsub z0\.s,p0/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqsub z0\.d,p0/m,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.s},p5,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.s},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.s},p0,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z17\.d},p5,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1b {z0\.d},p0,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z17\.d},p5,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1d {z0\.d},p0,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.s},p5,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.s},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.s},p0,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z17\.d},p5,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1h {z0\.d},p0,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.s},p5,\[z21\.s,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.s},p0,\[z0\.s,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z17\.d},p5,\[z21\.d,x27\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `stnt1w {z0\.d},p0,\[z0\.d,xzr\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z17\.b,{z21\.b,z22\.b},z27\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z0\.b,{z0\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z0\.h,{z0\.h,z1\.h},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z0\.s,{z0\.s,z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z0\.d,{z0\.d,z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `tbl z0\.b,{z31\.b,z0\.b},z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `umulh z17\.b,z21\.b,z27\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `umulh z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `umulh z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `umulh z0\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `umulh z0\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqadd z17\.b,p5/m,z17\.b,z21\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqadd z0\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqadd z0\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqadd z0\.s,p0/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqadd z0\.d,p0/m,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqsub z17\.b,p5/m,z17\.b,z21\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqsub z0\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqsub z0\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqsub z0\.s,p0/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqsub z0\.d,p0/m,z0\.d,z0\.d'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.d b/gas/testsuite/gas/aarch64/illegal-sve2.d
new file mode 100644
index 0000000..f1626ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.d
@@ -0,0 +1,4 @@
+#name: Illegal SVE2
+#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+bitperm
+#source: illegal-sve2.s
+#error_output: illegal-sve2.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
new file mode 100644
index 0000000..7d93a09
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -0,0 +1,3322 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: operand mismatch -- `movprfx z0\.d,z1\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	movprfx z0, z1
+[^ :]+:[0-9]+: Warning: predicated instruction expected after `movprfx' -- `adclb z0\.d,z1\.d,z2\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `adclb z0\.d,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	adclb z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	adclb z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclb z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `adclt z0\.d,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	adclt z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	adclt z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `addhnb z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	addhnb z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	addhnb z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	addhnb z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `addhnt z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	addhnt z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	addhnt z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	addhnt z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `addp z0\.b,p0/m,z0\.b,z1\.b'
+[^ :]+:[0-9]+: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `addp z0\.d,p1/m,z0\.d,z1\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `addp z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	addp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	addp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	addp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	addp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `addp z0\.h,p0/m,z1\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `addp z0\.s,p0/m,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	aesd z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aesd z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	aese z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aese z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	aesimc z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	aesmc z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesmc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bcax z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bcax z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bcax z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl1n z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl1n z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl1n z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl2n z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl2n z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bsl2n z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bdep z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bdep z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	bdep z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	bdep z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	bdep z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bdep z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bdep z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bdep z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bext z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bext z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	bext z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	bext z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	bext z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bext z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bext z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bext z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bgrp z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bgrp z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	bgrp z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	bgrp z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	bgrp z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bgrp z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bgrp z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bgrp z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `cadd z18\.b,z17\.b,z21\.b,#90'
+[^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `cadd z0\.b,z0\.b,z0\.b,#91'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cadd z0\.b,z0\.h,z0\.h,#90'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cadd z0\.h, z0\.h, z0\.h, #90
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	cadd z0\.b, z0\.b, z0\.b, #90
+[^ :]+:[0-9]+: Info:    	cadd z0\.s, z0\.s, z0\.s, #90
+[^ :]+:[0-9]+: Info:    	cadd z0\.d, z0\.d, z0\.d, #90
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.s,z0\.b,z0\.b\[0\],#1'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cdot z0\.s,z0\.b,z0\.b\[4\],#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.d,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cdot z0\.s,z0\.b,z8\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.d,z0\.h,z0\.h\[0\],#1'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.d,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cdot z0\.d,z0\.h,z16\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cdot z0\.s,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.b,z0\.s,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cdot z0\.s, z0\.b, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h, #0
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.s,z0\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	cdot z0\.s, z0\.b, z0\.b, #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cmla z0\.h,z0\.h,z8\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.h,z0\.h,z0\.d\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cmla z0\.h, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cmla z0\.h,z0\.h,z0\.h\[4\],#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.h,z0\.h,z0\.h\[0\],#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cmla z0\.s,z0\.s,z16\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.s,z0\.s,z0\.d\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cmla z0\.h, z0\.h, z0\.h\[0\], #0
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `cmla z0\.s,z0\.s,z0\.s\[2\],#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.s,z0\.s,z0\.s\[0\],#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cmla z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.b,z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	cmla z0\.b, z0\.b, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	cmla z0\.h, z0\.h, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	cmla z0\.s, z0\.s, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	cmla z0\.d, z0\.d, z0\.d, #0
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.b,z0\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `eor3 z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `eor3 z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	eor3 z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `eor3 z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	eor3 z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `eorbt z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	eorbt z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	eorbt z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	eorbt z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	eorbt z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eorbt z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eorbt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eorbt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `eortb z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	eortb z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	eortb z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	eortb z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	eortb z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.h,z1\.b},#0'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.h},#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b},#0'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ext z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `faddp z0\.h,p0/m,z1\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	faddp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	faddp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	faddp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/m,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	faddp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	faddp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	faddp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtlt z0\.s,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.s,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.s,p8/m,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.s,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.d,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.d,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/m,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/z,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtnt z0\.h,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.h,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.h,p8/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.h,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/z,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtx z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtx z0\.s,p8/m,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtx z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtx z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/z,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtx z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtx z0\.s,p0/m,z2\.d'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtxnt z0\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtxnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtxnt z0\.s,p8/m,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtxnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtxnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/z,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvtxnt z0\.s, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	flogb z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	flogb z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	flogb z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.b,p0/m,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	flogb z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	flogb z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	flogb z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.h,p0/z,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	flogb z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	flogb z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	flogb z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `flogb z32\.h,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `flogb z0\.h,p8/m,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `flogb z0\.h,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.b,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxnmp z1\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxnmp z0\.h,p8/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.b,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fmaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxp z1\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxp z0\.h,p8/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.b,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fminnmp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminnmp z1\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminnmp z0\.h,p8/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.b,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	fminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminp z1\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminp z0\.h,p8/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlalb z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlalt z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlslb z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.s,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlslb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlslt z0\.s, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.s,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmlslt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `histcnt z0\.s,p8/z,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.s,p0/m,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	histcnt z0\.s, p0/z, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	histcnt z0\.d, p0/z, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.d,p0/z,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	histcnt z0\.s, p0/z, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	histcnt z0\.d, p0/z, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histseg z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `histseg z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histseg z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	histseg z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1b {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1b {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1d {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.s},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1h {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.s},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sb {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sb {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1sh {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1sh {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `ldnt1w {z0\.d,z1\.d},p0/z,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.s},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `match p0\.h,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	match p0\.b, p0/z, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	match p0\.h, p0/z, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `match p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `match p0\.b,p8/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `match p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `match p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mla z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mla z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mla z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mla z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mls z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mls z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mls z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mls z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mul z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mul z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mul z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mul z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	mul z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	mul z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	mul z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.h,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	nmatch p0\.b, p0/z, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	nmatch p0\.h, p0/z, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	nmatch p0\.b, p0/z, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	nmatch p0\.h, p0/z, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `nmatch p0\.b,p8/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `nbsl z0\.d,z1\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.d,z0\.h,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	nbsl z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.h,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	nbsl z0\.d, z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `pmul z0\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	pmul z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmul z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	pmullb z0\.q, z0\.d, z0\.d
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	pmullb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	pmullb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	pmullt z0\.q, z0\.d, z0\.d
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	pmullt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	pmullt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `raddhnb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	raddhnb z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	raddhnb z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	raddhnb z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `raddhnt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	raddhnt z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	raddhnt z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	raddhnt z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `rax1 z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rax1 z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rax1 z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `rax1 z0\.d,z0\.d,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	rax1 z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `rshrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	rshrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	rshrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	rshrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `rshrnt z0\.b,z1\.h,#8'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `rshrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	rshrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	rshrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	rshrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `rshrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	rsubhnb z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	rsubhnb z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	rsubhnb z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	rsubhnt z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	rsubhnt z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	rsubhnt z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saba z0\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saba z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saba z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	saba z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	saba z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saba z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saba z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saba z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sabalb z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sabalb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sabalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sabalb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sabalt z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sabalt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sabalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sabalt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sabdlb z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sabdlb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sabdlb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sabdlb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sabdlt z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sabdlt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sabdlt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sabdlt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sadalp z0\.h, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sadalp z0\.s, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sadalp z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.h,p0/z,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sadalp z0\.h, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sadalp z0\.s, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sadalp z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sadalp z0\.h,p8/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saddlb z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saddlb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saddlb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	saddlb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saddlbt z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saddlbt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saddlbt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	saddlbt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saddlt z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saddlt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saddlt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	saddlt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saddwb z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saddwb z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saddwb z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	saddwb z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `saddwt z0\.b,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	saddwt z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	saddwt z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	saddwt z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sbclb z0\.d,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sbclb z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sbclb z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclb z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sbclt z0\.d,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sbclt z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sbclt z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `shrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	shrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `shrnt z0\.b,z1\.h,#8'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `shrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	shrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `shrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsub z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsub z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsubr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsubr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	shsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	shsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	shsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	shsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sli z0\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sli z0\.b, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sli z0\.h, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sli z0\.s, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	sli z0\.d, z0\.d, #0
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sli z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sli z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sli z0\.b,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sli z0\.h,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sli z0\.s,z0\.s,#32'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 3 -- `sli z0\.d,z0\.d,#64'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sm4e z0\.s,z0\.s,z1\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sm4e z1\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4e z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4e z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4e z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sm4e z0\.s,z0\.s,z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sm4e z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4ekey z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4ekey z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sm4ekey z0\.s,z0\.s,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sm4ekey z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `smaxp z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smaxp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	smaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `smaxp z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smaxp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	smaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `smaxp z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sminp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sminp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sminp z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smlalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlalt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smlalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smlslb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smlslt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smlslt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smlslt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `smulh z0\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smulh z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smulh z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smulh z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	smulh z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smulh z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `smulh z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smulh z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smullb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	smullt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	smullt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	smullt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	splice z0\.b, p0, {z0\.b, z1\.b}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	splice z0\.h, p0, {z0\.h, z1\.h}
+[^ :]+:[0-9]+: Info:    	splice z0\.s, p0, {z0\.s, z1\.s}
+[^ :]+:[0-9]+: Info:    	splice z0\.d, p0, {z0\.d, z1\.d}
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `splice z32\.b,p0,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `splice z0\.b,p8,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z31\.b,z32\.b}'
+[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z32\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqabs z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqabs z0\.b,p8/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqabs z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/m,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqabs z0\.b, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqabs z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sqabs z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	sqabs z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/z,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqabs z0\.b, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqabs z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sqabs z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	sqabs z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `sqcadd z0\.b,z0\.b,z0\.b,#180'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sqcadd z0\.b,z1\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcadd z0\.b,z0\.b,z0\.h,#90'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcadd z0\.b, z0\.b, z0\.b, #90
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcadd z0\.h, z0\.h, z0\.h, #90
+[^ :]+:[0-9]+: Info:    	sqcadd z0\.s, z0\.s, z0\.s, #90
+[^ :]+:[0-9]+: Info:    	sqcadd z0\.d, z0\.d, z0\.d, #90
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalbt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalbt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalbt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlalbt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlalbt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlalt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlslb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslbt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslbt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslbt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlslbt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlslbt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmlslt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmlslt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmulh z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmulh z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmulh z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqdmulh z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.h,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmulh z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqdmulh z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmullb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqdmullt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqdmullt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqneg z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqneg z0\.b,p8/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqneg z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/m,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqneg z0\.b, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqneg z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sqneg z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	sqneg z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/z,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqneg z0\.b, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqneg z0\.h, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	sqneg z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Info:    	sqneg z0\.d, p0/m, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z8\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[4\],#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#1'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#360'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.h,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.s,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z16\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[2\],#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#1'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#360'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.s,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.h,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#360'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.b,z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.b, z0\.b, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.h, z0\.h, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.d, z0\.d, z0\.d, #0
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlah z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.h,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlah z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlah z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrdmlah z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.h,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlsh z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.h,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmulh z0\.h,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.s,z0\.s,z8\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmulh z0\.s,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.s,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmulh z0\.d,z0\.d,z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmulh z0\.d,z0\.d,z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.h,z0\.d\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.d,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmulh z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrdmulh z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqrshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqrshrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrnt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqrshrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshrunb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshrunb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqrshrunb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrunt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqrshrunt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqrshrunt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqrshrunt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrunt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.h,p0/m,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshl z0\.b, p0/m, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshl z0\.h, p0/m, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sqshl z0\.s, p0/m, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	sqshl z0\.d, p0/m, z0\.d, #0
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,#0'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshl z0\.h,p0/m,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshl z0\.s,p0/m,z0\.s,#32'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshl z0\.d,p0/m,z0\.d,#64'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshlu z0\.h,p0/m,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshlu z0\.b, p0/m, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshlu z0\.h, p0/m, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sqshlu z0\.s, p0/m, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	sqshlu z0\.d, p0/m, z0\.d, #0
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlu z0\.b,p0/m,z1\.b,#0'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlu z0\.b,p8/m,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshlu z0\.b,p0/m,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshlu z0\.h,p0/m,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshlu z0\.s,p0/m,z0\.s,#32'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshlu z0\.d,p0/m,z0\.d,#64'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqshrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrnt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqshrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshrunb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshrunb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqshrunb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrunt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqshrunt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqshrunt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	sqshrunt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsub z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsub z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsubr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsubr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	sqsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnb z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqxtnb z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqxtnb z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	sqxtnb z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnt z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqxtnt z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqxtnt z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	sqxtnt z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunb z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqxtunb z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqxtunb z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	sqxtunb z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunt z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqxtunt z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqxtunt z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	sqxtunt z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srhadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srhadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `sri z0\.h,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sri z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sri z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	sri z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	sri z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sri z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sri z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `sri z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	srshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	srshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `srshr z0\.h,p0/m,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srshr z0\.b, p0/m, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srshr z0\.h, p0/m, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	srshr z0\.s, p0/m, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	srshr z0\.d, p0/m, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshr z0\.b,p0/m,z1\.b,#1'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshr z0\.b,p8/m,z0\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `srshr z0\.h,p0/m,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `srshr z0\.h,p0/m,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `srshr z0\.s,p0/m,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `srshr z0\.s,p0/m,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `srshr z0\.d,p0/m,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `srshr z0\.d,p0/m,z0\.d,#65'
+[^ :]+:[0-9]+: Error: operand mismatch -- `srsra z0\.h,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	srsra z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	srsra z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	srsra z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	srsra z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srsra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `srsra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `srsra z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `srsra z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `srsra z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sshllb z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sshllb z0\.h, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sshllb z0\.s, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sshllb z0\.d, z0\.s, #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllb z0\.h,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllb z0\.s,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllb z0\.d,z0\.s,#32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sshllt z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sshllt z0\.h, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sshllt z0\.s, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	sshllt z0\.d, z0\.s, #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllt z0\.h,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllt z0\.s,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllt z0\.d,z0\.s,#32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssra z0\.h,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssra z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssra z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	ssra z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	ssra z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ssra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ssra z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssublb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssublb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssublb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	ssublb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublbt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssublbt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssublbt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssublbt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	ssublbt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssublt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssublt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssublt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	ssublt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubltb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubltb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubltb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubltb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssubltb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssubltb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssubltb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	ssubltb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwb z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssubwb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssubwb z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssubwb z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	ssubwb z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwt z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ssubwt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ssubwt z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ssubwt z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	ssubwt z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1b {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.s},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1d {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.s},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1h {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.s},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: invalid register list at operand 1 -- `stnt1w {z0\.d,z1\.d},p0,\[z0\.d,x0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,x32\]'
+[^ :]+:[0-9]+: Error: invalid use of 32-bit register offset at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,w16\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,z0\.d\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.s},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
+[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: base register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
+[^ :]+:[0-9]+: Error: offset register expected at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,x32\]'
+[^ :]+:[0-9]+: Error: invalid addressing mode at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,z0\.s\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `subhnb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	subhnb z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	subhnb z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	subhnb z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `subhnt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	subhnt z0\.b, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	subhnt z0\.h, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	subhnt z0\.s, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `suqadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `suqadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	suqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	suqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	suqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	suqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	suqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	suqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	suqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	suqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `tbl z0\.b,{z31\.b,z32\.b},z0\.b'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	tbl z0\.h, {z0\.h, z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info:    	tbl z0\.s, {z0\.s, z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:    	tbl z0\.d, {z0\.d, z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
+[^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbx z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `tbx z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbx z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `tbx z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `tbx z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	tbx z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	tbx z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	tbx z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	tbx z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaba z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaba z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaba z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaba z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uaba z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uaba z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uaba z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	uaba z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uaba z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uabalb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uabalb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uabalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uabalb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uabalt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uabalt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uabalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uabalt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uabdlb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uabdlb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uabdlb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uabdlb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uabdlt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uabdlt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uabdlt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uabdlt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `uadalp z0\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uadalp z0\.h, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uadalp z0\.s, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	uadalp z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `uadalp z0\.h,p0/z,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uadalp z0\.h, p0/m, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uadalp z0\.s, p0/m, z0\.h
+[^ :]+:[0-9]+: Info:    	uadalp z0\.d, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uadalp z0\.h,p8/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uaddlb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uaddlb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uaddlb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uaddlb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uaddlt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uaddlt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uaddlt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uaddlt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwb z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uaddwb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uaddwb z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uaddwb z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	uaddwb z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwt z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uaddwt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uaddwt z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uaddwt z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	uaddwt z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsub z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsub z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsubr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsubr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uhsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `umaxp z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `umaxp z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umaxp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	umaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umaxp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umaxp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umaxp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	umaxp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uminp z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uminp z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uminp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uminp z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uminp z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uminp z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uminp z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umlalb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlalt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umlalt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umlslb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umlslt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umlslt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `umulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umulh z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umulh z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umulh z0\.h, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umulh z0\.b, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    	umulh z0\.s, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	umulh z0\.d, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullb z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullb z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullb z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullb z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umullb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullt z0\.s,z0\.h,z8\.h\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullt z0\.s,z0\.h,z0\.h\[8\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullt z0\.d,z0\.s,z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullt z0\.d,z0\.s,z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s\[0\]
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	umullt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	umullt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqrshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqrshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	uqrshrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqrshrnt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqrshrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqrshrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	uqrshrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqrshrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.h,p0/m,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshl z0\.b, p0/m, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshl z0\.h, p0/m, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	uqshl z0\.s, p0/m, z0\.s, #0
+[^ :]+:[0-9]+: Info:    	uqshl z0\.d, p0/m, z0\.d, #0
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,#0'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `uqshl z0\.h,p0/m,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `uqshl z0\.s,p0/m,z0\.s,#32'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `uqshl z0\.d,p0/m,z0\.d,#64'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnb z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshrnb z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshrnb z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	uqshrnb z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnb z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnb z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqshrnt z0\.b,z0\.h,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnt z0\.h,z0\.h,#8'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqshrnt z0\.b, z0\.h, #8
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqshrnt z0\.h, z0\.s, #8
+[^ :]+:[0-9]+: Info:    	uqshrnt z0\.s, z0\.d, #8
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#33'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsub z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsub z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqsub z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqsub z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqsub z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqsub z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsubr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsubr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	uqsubr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnb z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqxtnb z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqxtnb z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	uqxtnb z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnt z0\.b,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	uqxtnt z0\.b, z0\.h
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	uqxtnt z0\.h, z0\.s
+[^ :]+:[0-9]+: Info:    	uqxtnt z0\.s, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urecpe z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urecpe z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urecpe z0\.s,p8/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `urecpe z0\.d,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urecpe z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urhadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urhadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urhadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urhadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urhadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urhadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshl z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshl z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urshl z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urshl z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urshl z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urshl z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshlr z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshlr z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urshlr z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urshlr z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	urshlr z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	urshlr z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `urshr z0\.h,p0/m,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	urshr z0\.b, p0/m, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	urshr z0\.h, p0/m, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	urshr z0\.s, p0/m, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	urshr z0\.d, p0/m, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshr z0\.b,p0/m,z1\.b,#1'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshr z0\.b,p8/m,z0\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `urshr z0\.h,p0/m,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `urshr z0\.h,p0/m,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#65'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ursqrte z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ursqrte z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ursqrte z0\.s,p8/m,z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ursqrte z0\.d,p0/m,z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ursqrte z0\.s, p0/m, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `ursra z0\.h,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ursra z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ursra z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	ursra z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	ursra z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ursra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ursra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ursra z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ursra z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ursra z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ushllb z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ushllb z0\.h, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ushllb z0\.s, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	ushllb z0\.d, z0\.s, #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllb z0\.h,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllb z0\.s,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllb z0\.d,z0\.s,#32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ushllt z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	ushllt z0\.h, z0\.b, #0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	ushllt z0\.s, z0\.h, #0
+[^ :]+:[0-9]+: Info:    	ushllt z0\.d, z0\.s, #0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllt z0\.h,z0\.b,#8'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllt z0\.s,z0\.h,#16'
+[^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllt z0\.d,z0\.s,#32'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `usqadd z0\.b,p0/m,z1\.b,z0\.b'
+[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `usqadd z0\.b,p8/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.h,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	usqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	usqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usqadd z0\.b, p0/m, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usqadd z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	usqadd z0\.s, p0/m, z0\.s, z0\.s
+[^ :]+:[0-9]+: Info:    	usqadd z0\.d, p0/m, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `usra z0\.h,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usra z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usra z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	usra z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	usra z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `usra z0\.d,z0\.d,#0'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublb z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `usublb z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usublb z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usublb z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	usublb z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublt z0\.s,z0\.h,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `usublt z0\.h,z0\.b,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usublt z0\.h, z0\.b, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usublt z0\.s, z0\.h, z0\.h
+[^ :]+:[0-9]+: Info:    	usublt z0\.d, z0\.s, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwb z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `usubwb z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usubwb z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usubwb z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	usubwb z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwt z0\.s,z0\.s,z0\.x'
+[^ :]+:[0-9]+: Error: operand mismatch -- `usubwt z0\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	usubwt z0\.h, z0\.h, z0\.b
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	usubwt z0\.s, z0\.s, z0\.h
+[^ :]+:[0-9]+: Info:    	usubwt z0\.d, z0\.d, z0\.s
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,x0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,x0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,x0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,x0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilerw p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilerw p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilerw p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilerw p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilerw p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilerw p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilerw p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilerw p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilerw p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilerw p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0\.b,w0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilewr p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilewr p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilewr p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilewr p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0/m,x0,x0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	whilewr p0\.b, x0, x0
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	whilewr p0\.h, x0, x0
+[^ :]+:[0-9]+: Info:    	whilewr p0\.s, x0, x0
+[^ :]+:[0-9]+: Info:    	whilewr p0\.d, x0, x0
+[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilewr p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilewr p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `xar z0\.h,z0\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	xar z0\.b, z0\.b, z0\.b, #1
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	xar z0\.h, z0\.h, z0\.h, #1
+[^ :]+:[0-9]+: Info:    	xar z0\.s, z0\.s, z0\.s, #1
+[^ :]+:[0-9]+: Info:    	xar z0\.d, z0\.d, z0\.d, #1
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `xar z0\.b,z1\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `xar z0\.b,z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#9'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#17'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#0'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `xar z0\.s,z0\.s,z0\.s,#33'
+[^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `xar z0\.d,z0\.d,z0\.d,#0'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.s b/gas/testsuite/gas/aarch64/illegal-sve2.s
new file mode 100644
index 0000000..c6c408c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.s
@@ -0,0 +1,2062 @@
+movprfx z0.d, z1.d
+adclb z0.d, z1.d, z2.d
+
+movprfx z0.d, p0/m, z1.d
+adclb z0.d, z1.d, z2.d
+
+adclb z0.d, z0.s, z0.s
+adclb z32.d, z0.d, z0.d
+adclb z0.d, z32.d, z0.d
+adclb z0.d, z0.d, z32.d
+adclt z0.d, z0.s, z0.s
+adclt z32.s, z0.s, z0.s
+adclt z0.s, z32.s, z0.s
+adclt z0.s, z0.s, z32.s
+
+addhnb z0.b, z0.h, z0.b
+addhnb z32.b, z0.h, z0.h
+addhnb z0.b, z32.h, z0.h
+addhnb z0.b, z0.h, z32.h
+addhnt z0.b, z0.h, z0.b
+addhnt z32.b, z0.h, z0.h
+addhnt z0.b, z32.h, z0.h
+addhnt z0.b, z0.h, z32.h
+
+movprfx z0.d, p0/m, z1.d
+addp z0.b, p0/m, z0.b, z1.b
+
+movprfx z0.d, p0/m, z1.d
+addp z0.d, p1/m, z0.d, z1.d
+
+addp z0.b, p0/z, z0.b, z0.b
+addp z0.h, p0/m, z1.h, z0.h
+addp z32.s, p0/m, z32.s, z0.s
+addp z0.s, p0/m, z0.s, z32.s
+addp z0.s, p8/m, z0.s, z0.s
+
+movprfx z0, z1
+aesd z0.b, z0.b, z0.b
+
+aesd z0.b, z1.b, z0.b
+aesd z0.b, z0.s, z0.b
+aesd z32.b, z0.b, z0.b
+aesd z0.b, z0.b, z32.b
+
+movprfx z0, z1
+aese z0.b, z0.b, z0.b
+
+aese z0.b, z1.b, z0.b
+aese z0.b, z0.s, z0.b
+aese z32.b, z0.b, z0.b
+aese z0.b, z0.b, z32.b
+
+movprfx z0, z1
+aesimc z0.b, z0.b
+
+aesimc z0.b, z1.b
+aesimc z0.b, z0.s
+aesimc z32.b, z0.b
+
+movprfx z0, z1
+aesmc z0.b, z0.b
+
+aesmc z0.b, z1.b
+aesmc z0.b, z0.s
+aesmc z32.b, z0.b
+
+bcax z0.d, z1.d, z0.d, z0.d
+bcax z0.d, z0.d, z0.h, z0.d
+bcax z0.d, z0.h, z0.d, z0.d
+bcax z32.d, z32.d, z0.d, z0.d
+bcax z0.d, z0.d, z32.d, z0.d
+bcax z0.d, z0.d, z0.d, z32.d
+
+bsl z0.d, z1.d, z0.d, z0.d
+bsl z0.d, z0.d, z0.h, z0.d
+bsl z0.d, z0.h, z0.d, z0.d
+bsl z32.d, z32.d, z0.d, z0.d
+bsl z0.d, z0.d, z32.d, z0.d
+bsl z0.d, z0.d, z0.d, z32.d
+
+bsl1n z0.d, z1.d, z0.d, z0.d
+bsl1n z0.d, z0.d, z0.h, z0.d
+bsl1n z0.d, z0.h, z0.d, z0.d
+bsl1n z32.d, z32.d, z0.d, z0.d
+bsl1n z0.d, z0.d, z32.d, z0.d
+bsl1n z0.d, z0.d, z0.d, z32.d
+
+bsl2n z0.d, z1.d, z0.d, z0.d
+bsl2n z0.d, z0.d, z0.h, z0.d
+bsl2n z0.d, z0.h, z0.d, z0.d
+bsl2n z32.d, z32.d, z0.d, z0.d
+bsl2n z0.d, z0.d, z32.d, z0.d
+bsl2n z0.d, z0.d, z0.d, z32.d
+
+bdep z0.b, z0.h, z0.b
+bdep z32.h, z0.h, z0.h
+bdep z0.s, z32.s, z0.s
+bdep z0.d, z0.d, z32.d
+
+bext z0.b, z0.h, z0.b
+bext z32.h, z0.h, z0.h
+bext z0.s, z32.s, z0.s
+bext z0.d, z0.d, z32.d
+
+bgrp z0.b, z0.h, z0.b
+bgrp z32.h, z0.h, z0.h
+bgrp z0.s, z32.s, z0.s
+bgrp z0.d, z0.d, z32.d
+
+cadd z18.b, z17.b, z21.b, #90
+cadd z0.b, z0.b, z0.b, #91
+cadd z0.b, z0.h, z0.h, #90
+
+cdot z0.s, z0.b, z0.b[0], #1
+cdot z0.s, z0.b, z0.b[4], #0
+cdot z0.s, z0.d, z0.b[0], #0
+cdot z32.s, z0.b, z0.b[0], #0
+cdot z0.s, z32.b, z0.b[0], #0
+cdot z0.s, z0.b, z8.b[0], #0
+
+cdot z0.d, z0.h, z0.h[0], #1
+cdot z0.d, z0.h, z0.h[1], #0
+cdot z0.d, z0.d, z0.h[0], #0
+cdot z32.d, z0.h, z0.h[0], #0
+cdot z0.d, z32.h, z0.h[0], #0
+cdot z0.d, z0.h, z16.h[0], #0
+
+cdot z32.s, z0.b, z0.b, #0
+cdot z0.s, z32.b, z0.b, #0
+cdot z0.s, z0.b, z32.b, #0
+cdot z0.s, z0.b, z0.s, #0
+cdot z0.s, z0.b, z0.b, #1
+cdot z0.d, z0.h, z0.b, #0
+
+cmla z32.h, z0.h, z0.h[0], #0
+cmla z0.h, z32.h, z0.h[0], #0
+cmla z0.h, z0.h, z8.h[0], #0
+cmla z0.h, z0.h, z0.d[0], #0
+cmla z0.h, z0.h, z0.h[4], #0
+cmla z0.h, z0.h, z0.h[0], #1
+
+cmla z32.s, z0.s, z0.s[0], #0
+cmla z0.s, z32.s, z0.s[0], #0
+cmla z0.s, z0.s, z16.s[0], #0
+cmla z0.s, z0.s, z0.d[0], #0
+cmla z0.s, z0.s, z0.s[2], #0
+cmla z0.s, z0.s, z0.s[0], #1
+
+cmla z32.b, z0.b, z0.b, #0
+cmla z0.b, z32.b, z0.b, #0
+cmla z0.b, z0.b, z32.b, #0
+cmla z0.b, z0.b, z0.h, #0
+cmla z0.b, z0.b, z0.b, #1
+
+eor3 z0.d, z1.d, z0.d, z0.d
+eor3 z0.d, z0.d, z0.h, z0.d
+eor3 z0.d, z0.h, z0.d, z0.d
+
+eorbt z0.b, z0.h, z0.b
+eorbt z32.h, z0.h, z0.h
+eorbt z0.s, z32.s, z0.s
+eorbt z0.s, z0.s, z32.s
+
+eortb z0.b, z0.h, z0.b
+eortb z32.h, z0.h, z0.h
+eortb z0.s, z32.s, z0.s
+eortb z0.s, z0.s, z32.s
+
+ext z0.b, { z0.b, z2.b }, #0
+ext z0.h, { z0.b, z1.b }, #0
+ext z0.b, { z0.h, z1.b }, #0
+ext z0.b, { z0.b, z1.h }, #0
+ext z0.b, { z0.h, z1.h }, #0
+ext z0.b, { z0.b, z1.b, z2.b }, #0
+ext z0.b, { z0.b }, #0
+ext z0.b,  z0.b, #0
+ext z0.b, { z31.b, z1.b }, #0
+ext z0.b, { z0.b, z31.b }, #0
+ext z0.b, { z0.b, z1.b }, #256
+ext z32.b, { z0.b, z1.b }, #0
+ext z0.b, { z31.b, z32.b }, #0
+ext z0.b, { z32.b, z33.b }, #0
+
+faddp z32.h, p0/m, z32.h, z0.h
+faddp z0.h, p8/m, z0.h, z0.h
+faddp z0.h, p0/m, z0.h, z32.h
+faddp z0.h, p0/m, z1.h, z0.h
+faddp z0.h, p0/z, z0.h, z0.h
+faddp z0.h, p0/m, z0.b, z0.h
+
+movprfx z0.s, p0/m, z1.s
+fcvtlt z0.s, p0/m, z0.h
+
+fcvtlt z32.s, p0/m, z0.h
+fcvtlt z0.s, p8/m, z0.h
+fcvtlt z0.s, p0/m, z32.h
+fcvtlt z0.s, p0/m, z0.s
+fcvtlt z0.s, p0/z, z0.h
+fcvtlt z32.d, p0/m, z0.s
+fcvtlt z0.d, p8/m, z0.s
+fcvtlt z0.d, p0/m, z32.s
+fcvtlt z0.d, p0/m, z0.d
+fcvtlt z0.d, p0/z, z0.s
+
+movprfx z0.s, p0/m, z1.s
+fcvtnt z0.h, p0/m, z0.s
+
+fcvtnt z32.h, p0/m, z0.s
+fcvtnt z0.h, p8/m, z0.s
+fcvtnt z0.h, p0/m, z32.s
+fcvtnt z0.h, p0/m, z0.h
+fcvtnt z0.h, p0/z, z0.s
+fcvtnt z32.s, p0/m, z0.d
+fcvtnt z0.s, p8/m, z0.d
+fcvtnt z0.s, p0/m, z32.d
+fcvtnt z0.s, p0/m, z0.s
+fcvtnt z0.s, p0/z, z0.d
+
+fcvtx z32.s, p0/m, z0.d
+fcvtx z0.s, p8/m, z0.d
+fcvtx z0.s, p0/m, z32.d
+fcvtx z0.s, p0/m, z0.s
+fcvtx z0.s, p0/z, z0.d
+
+movprfx z0.s, p0/z, z1.s
+fcvtx z0.s, p0/m, z2.d
+
+movprfx z0.s, p0/m, z1.s
+fcvtxnt z0.s, p0/m, z0.d
+
+fcvtxnt z32.s, p0/m, z0.d
+fcvtxnt z0.s, p8/m, z0.d
+fcvtxnt z0.s, p0/m, z32.d
+fcvtxnt z0.s, p0/m, z0.s
+fcvtxnt z0.s, p0/z, z0.d
+
+flogb z0.b, p0/m, z0.b
+flogb z0.b, p0/m, z0.h
+flogb z0.h, p0/z, z0.h
+flogb z32.h, p0/m, z0.h
+flogb z0.h, p8/m, z0.h
+flogb z0.h, p0/m, z32.h
+
+fmaxnmp z0.b, p0/m, z0.h, z0.h
+fmaxnmp z0.h, p0/z, z0.h, z0.h
+fmaxnmp z1.h, p0/m, z0.h, z0.h
+fmaxnmp z32.h, p0/m, z32.h, z0.h
+fmaxnmp z0.h, p8/m, z0.h, z0.h
+fmaxnmp z0.h, p0/m, z0.h, z32.h
+
+fmaxp z0.b, p0/m, z0.h, z0.h
+fmaxp z0.h, p0/z, z0.h, z0.h
+fmaxp z1.h, p0/m, z0.h, z0.h
+fmaxp z32.h, p0/m, z32.h, z0.h
+fmaxp z0.h, p8/m, z0.h, z0.h
+fmaxp z0.h, p0/m, z0.h, z32.h
+
+fminnmp z0.b, p0/m, z0.h, z0.h
+fminnmp z0.h, p0/z, z0.h, z0.h
+fminnmp z1.h, p0/m, z0.h, z0.h
+fminnmp z32.h, p0/m, z32.h, z0.h
+fminnmp z0.h, p8/m, z0.h, z0.h
+fminnmp z0.h, p0/m, z0.h, z32.h
+
+fminp z0.b, p0/m, z0.h, z0.h
+fminp z0.h, p0/z, z0.h, z0.h
+fminp z1.h, p0/m, z0.h, z0.h
+fminp z32.h, p0/m, z32.h, z0.h
+fminp z0.h, p8/m, z0.h, z0.h
+fminp z0.h, p0/m, z0.h, z32.h
+
+fmlalb z0.s, z0.h, z0.h[8]
+fmlalb z0.s, z0.h, z8.h[0]
+fmlalb z0.s, z32.h, z0.h[0]
+fmlalb z32.s, z0.h, z0.h[0]
+fmlalb z0.h, z0.h, z0.h[0]
+
+fmlalb z32.s, z0.h, z0.h
+fmlalb z0.s, z32.h, z0.h
+fmlalb z0.s, z0.h, z32.h
+fmlalb z0.s, z0.h, z0.d
+
+fmlalt z0.s, z0.h, z0.h[8]
+fmlalt z0.s, z0.h, z8.h[0]
+fmlalt z0.s, z32.h, z0.h[0]
+fmlalt z32.s, z0.h, z0.h[0]
+fmlalt z0.h, z0.h, z0.h[0]
+
+fmlalt z32.s, z0.h, z0.h
+fmlalt z0.s, z32.h, z0.h
+fmlalt z0.s, z0.h, z32.h
+fmlalt z0.s, z0.h, z0.d
+
+fmlslb z0.s, z0.h, z0.h[8]
+fmlslb z0.s, z0.h, z8.h[0]
+fmlslb z0.s, z32.h, z0.h[0]
+fmlslb z32.s, z0.h, z0.h[0]
+fmlslb z0.h, z0.h, z0.h[0]
+
+fmlslb z32.s, z0.h, z0.h
+fmlslb z0.s, z32.h, z0.h
+fmlslb z0.s, z0.h, z32.h
+fmlslb z0.s, z0.h, z0.d
+
+fmlslt z0.s, z0.h, z0.h[8]
+fmlslt z0.s, z0.h, z8.h[0]
+fmlslt z0.s, z32.h, z0.h[0]
+fmlslt z32.s, z0.h, z0.h[0]
+fmlslt z0.h, z0.h, z0.h[0]
+
+fmlslt z32.s, z0.h, z0.h
+fmlslt z0.s, z32.h, z0.h
+fmlslt z0.s, z0.h, z32.h
+fmlslt z0.s, z0.h, z0.d
+
+histcnt z32.s, p0/z, z0.s, z0.s
+histcnt z0.s, p8/z, z0.s, z0.s
+histcnt z0.s, p0/z, z32.s, z0.s
+histcnt z0.s, p0/z, z0.s, z32.s
+histcnt z0.s, p0/m, z0.s, z0.s
+histcnt z0.d, p0/z, z0.s, z0.s
+
+histseg z32.b, z0.b, z0.b
+histseg z0.b, z32.b, z0.b
+histseg z0.b, z0.b, z32.b
+histseg z0.b, z0.b, z0.h
+
+ldnt1b { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1b { z0.d }, p0/m, [z0.d]
+ldnt1b { z32.d }, p0/z, [z0.d]
+ldnt1b { z0.d }, p8/z, [z0.d]
+ldnt1b { z0.d }, p0/z, [z32.d]
+ldnt1b { z0.d }, p0/z, [z0.d, sp]
+ldnt1b { z0.d }, p0/z, [z0.d, x32]
+ldnt1b { z0.d }, p0/z, [z0.d, w16]
+ldnt1b { z0.d }, p0/z, [z0.d, z0.d]
+ldnt1b { z0.s }, p0/z, [z0.d]
+ldnt1b { z0.d }, p0/z, [z0.s]
+ldnt1b { z0.s, z1.d }, p0/z, [z0.s, x0]
+ldnt1b { z0.s }, p0/m, [z0.s]
+ldnt1b { z32.s }, p0/z, [z0.s]
+ldnt1b { z0.s }, p8/z, [z0.s]
+ldnt1b { z0.s }, p0/z, [z32.s]
+ldnt1b { z0.s }, p0/z, [z0.s, sp]
+ldnt1b { z0.s }, p0/z, [z0.s, x32]
+ldnt1b { z0.s }, p0/z, [z0.s, z0.s]
+
+ldnt1d { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1d { z0.d }, p0/m, [z0.d]
+ldnt1d { z32.d }, p0/z, [z0.d]
+ldnt1d { z0.d }, p8/z, [z0.d]
+ldnt1d { z0.d }, p0/z, [z32.d]
+ldnt1d { z0.d }, p0/z, [z0.d, sp]
+ldnt1d { z0.d }, p0/z, [z0.d, x32]
+ldnt1d { z0.d }, p0/z, [z0.d, w16]
+ldnt1d { z0.d }, p0/z, [z0.d, z0.d]
+ldnt1d { z0.s }, p0/z, [z0.d]
+ldnt1d { z0.d }, p0/z, [z0.s]
+ldnt1d { z0.d }, p0/m, [z0.d]
+
+ldnt1h { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1h { z0.d }, p0/m, [z0.d]
+ldnt1h { z32.d }, p0/z, [z0.d]
+ldnt1h { z0.d }, p8/z, [z0.d]
+ldnt1h { z0.d }, p0/z, [z32.d]
+ldnt1h { z0.d }, p0/z, [z0.d, sp]
+ldnt1h { z0.d }, p0/z, [z0.d, x32]
+ldnt1h { z0.d }, p0/z, [z0.d, w16]
+ldnt1h { z0.d }, p0/z, [z0.d, z0.d]
+ldnt1h { z0.s }, p0/z, [z0.d]
+ldnt1h { z0.s, z1.d }, p0/z, [z0.s, x0]
+ldnt1h { z32.s }, p0/z, [z0.s]
+ldnt1h { z0.s }, p8/z, [z0.s]
+ldnt1h { z0.s }, p0/z, [z32.s]
+ldnt1h { z0.s }, p0/z, [z0.s, sp]
+ldnt1h { z0.s }, p0/z, [z0.s, x32]
+ldnt1h { z0.s }, p0/z, [z0.s, z0.s]
+
+ldnt1sb { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1sb { z0.d }, p0/m, [z0.d]
+ldnt1sb { z32.d }, p0/z, [z0.d]
+ldnt1sb { z0.d }, p8/z, [z0.d]
+ldnt1sb { z0.d }, p0/z, [z32.d]
+ldnt1sb { z0.d }, p0/z, [z0.d, sp]
+ldnt1sb { z0.d }, p0/z, [z0.d, x32]
+ldnt1sb { z0.d }, p0/z, [z0.d, w16]
+ldnt1sb { z0.d }, p0/z, [z0.d, z0.d]
+
+ldnt1sh { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1sh { z0.d }, p0/m, [z0.d]
+ldnt1sh { z32.d }, p0/z, [z0.d]
+ldnt1sh { z0.d }, p8/z, [z0.d]
+ldnt1sh { z0.d }, p0/z, [z32.d]
+ldnt1sh { z0.d }, p0/z, [z0.d, sp]
+ldnt1sh { z0.d }, p0/z, [z0.d, x32]
+ldnt1sh { z0.d }, p0/z, [z0.d, w16]
+ldnt1sh { z0.d }, p0/z, [z0.d, z0.d]
+
+ldnt1sh { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1sh { z0.d }, p0/m, [z0.d]
+ldnt1sh { z32.d }, p0/z, [z0.d]
+ldnt1sh { z0.d }, p8/z, [z0.d]
+ldnt1sh { z0.d }, p0/z, [z32.d]
+ldnt1sh { z0.d }, p0/z, [z0.d, sp]
+ldnt1sh { z0.d }, p0/z, [z0.d, x32]
+ldnt1sh { z0.d }, p0/z, [z0.d, w16]
+ldnt1sh { z0.d }, p0/z, [z0.d, z0.d]
+
+ldnt1w { z0.d, z1.d }, p0/z, [z0.d, x0]
+ldnt1w { z0.d }, p0/m, [z0.d]
+ldnt1w { z32.d }, p0/z, [z0.d]
+ldnt1w { z0.d }, p8/z, [z0.d]
+ldnt1w { z0.d }, p0/z, [z32.d]
+ldnt1w { z0.d }, p0/z, [z0.d, sp]
+ldnt1w { z0.d }, p0/z, [z0.d, x32]
+ldnt1w { z0.d }, p0/z, [z0.d, w16]
+ldnt1w { z0.d }, p0/z, [z0.d, z0.d]
+ldnt1w { z0.s }, p0/z, [z0.d]
+ldnt1w { z0.s, z1.d }, p0/z, [z0.s, x0]
+ldnt1w { z32.s }, p0/z, [z0.s]
+ldnt1w { z0.s }, p8/z, [z0.s]
+ldnt1w { z0.s }, p0/z, [z32.s]
+ldnt1w { z0.s }, p0/z, [z0.s, sp]
+ldnt1w { z0.s }, p0/z, [z0.s, x32]
+ldnt1w { z0.s }, p0/z, [z0.s, z0.s]
+
+match p0.h, p0/z, z0.b, z0.b
+match p16.b, p0/z, z0.b, z0.b
+match p0.b, p8/z, z0.b, z0.b
+match p0.b, p0/z, z32.b, z0.b
+match p0.b, p0/z, z0.b, z32.b
+
+mla z0.h, z0.h, z0.h[8]
+mla z0.s, z0.h, z0.h[0]
+mla z0.h, z0.h, z0.s[0]
+mla z32.h, z0.h, z0.h[0]
+mla z0.h, z32.h, z0.h[0]
+mla z0.h, z0.h, z8.h[0]
+
+mla z0.s, z0.s, z0.s[4]
+mla z0.h, z0.s, z0.s[0]
+mla z0.s, z0.s, z0.h[0]
+mla z32.s, z0.s, z0.s[0]
+mla z0.s, z32.s, z0.s[0]
+mla z0.s, z0.s, z8.s[0]
+
+mla z0.d, z0.d, z0.d[2]
+mla z0.h, z0.d, z0.d[0]
+mla z0.d, z0.d, z0.h[0]
+mla z32.d, z0.d, z0.d[0]
+mla z0.d, z32.d, z0.d[0]
+mla z0.d, z0.d, z16.d[0]
+
+mls z0.h, z0.h, z0.h[8]
+mls z0.s, z0.h, z0.h[0]
+mls z0.h, z0.h, z0.s[0]
+mls z32.h, z0.h, z0.h[0]
+mls z0.h, z32.h, z0.h[0]
+mls z0.h, z0.h, z8.h[0]
+
+mls z0.s, z0.s, z0.s[4]
+mls z0.h, z0.s, z0.s[0]
+mls z0.s, z0.s, z0.h[0]
+mls z32.s, z0.s, z0.s[0]
+mls z0.s, z32.s, z0.s[0]
+mls z0.s, z0.s, z8.s[0]
+
+mls z0.d, z0.d, z0.d[2]
+mls z0.h, z0.d, z0.d[0]
+mls z0.d, z0.d, z0.h[0]
+mls z32.d, z0.d, z0.d[0]
+mls z0.d, z32.d, z0.d[0]
+mls z0.d, z0.d, z16.d[0]
+
+mul z0.h, z0.h, z0.h[8]
+mul z0.s, z0.h, z0.h[0]
+mul z0.h, z0.h, z0.s[0]
+mul z32.h, z0.h, z0.h[0]
+mul z0.h, z32.h, z0.h[0]
+mul z0.h, z0.h, z8.h[0]
+
+mul z0.s, z0.s, z0.s[4]
+mul z0.h, z0.s, z0.s[0]
+mul z0.s, z0.s, z0.h[0]
+mul z32.s, z0.s, z0.s[0]
+mul z0.s, z32.s, z0.s[0]
+mul z0.s, z0.s, z8.s[0]
+
+mul z0.d, z0.d, z0.d[2]
+mul z0.h, z0.d, z0.d[0]
+mul z0.d, z0.d, z0.h[0]
+mul z32.d, z0.d, z0.d[0]
+mul z0.d, z32.d, z0.d[0]
+mul z0.d, z0.d, z16.d[0]
+
+mul z0.h, z0.b, z0.b
+mul z32.b, z0.b, z0.b
+mul z0.b, z32.b, z0.b
+mul z0.b, z0.b, z0.b
+
+nmatch p0.h, p0/z, z0.b, z0.b
+nmatch p0.b, p0/m, z0.b, z0.b
+nmatch p16.b, p0/z, z0.b, z0.b
+nmatch p0.b, p8/z, z0.b, z0.b
+nmatch p0.b, p0/z, z32.b, z0.b
+nmatch p0.b, p0/z, z0.b, z32.b
+
+nbsl z0.d, z1.d, z0.d, z0.d
+nbsl z0.d, z0.d, z0.h, z0.d
+nbsl z0.d, z0.h, z0.d, z0.d
+
+pmul z0.h, z0.b, z0.b
+pmul z32.b, z0.b, z0.b
+pmul z0.b, z32.b, z0.b
+pmul z0.b, z0.b, z32.b
+
+pmullb z32.q, z0.d, z0.d
+pmullb z0.q, z32.d, z0.d
+pmullb z0.q, z0.d, z32.d
+pmullb z0.d, z0.d, z0.d
+
+pmullt z32.q, z0.d, z0.d
+pmullt z0.q, z32.d, z0.d
+pmullt z0.q, z0.d, z32.d
+pmullt z0.d, z0.d, z0.d
+
+raddhnb z0.h, z0.h, z0.h
+raddhnb z32.b, z0.h, z0.h
+raddhnb z0.b, z32.h, z0.h
+raddhnb z0.b, z0.h, z32.h
+
+raddhnt z0.h, z0.h, z0.h
+raddhnt z32.b, z0.h, z0.h
+raddhnt z0.b, z32.h, z0.h
+raddhnt z0.b, z0.h, z32.h
+
+rax1 z32.d, z0.d, z0.d
+rax1 z0.d, z32.d, z0.d
+rax1 z0.d, z0.d, z32.d
+rax1 z0.d, z0.d, z0.h
+
+# Too high a shift, too low a shift, invalid arguments.
+rshrnb z32.b, z0.h, #8
+rshrnb z0.b, z32.h, #8
+rshrnb z0.b, z0.h, #9
+rshrnb z0.b, z0.h, #0
+rshrnb z0.h, z0.h, #8
+rshrnb z0.h, z0.s, #0
+rshrnb z0.h, z0.s, #17
+rshrnb z0.s, z0.d, #0
+rshrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+rshrnt z0.b, z1.h, #8
+
+rshrnt z32.b, z0.h, #8
+rshrnt z0.b, z32.h, #8
+rshrnt z0.b, z0.h, #9
+rshrnt z0.b, z0.h, #0
+rshrnt z0.h, z0.h, #8
+rshrnt z0.h, z0.s, #0
+rshrnt z0.h, z0.s, #17
+rshrnt z0.s, z0.d, #0
+rshrnt z0.s, z0.d, #33
+
+rsubhnb z0.h, z0.h, z0.h
+rsubhnb z32.b, z0.h, z0.h
+rsubhnb z0.b, z32.h, z0.h
+rsubhnb z0.b, z0.h, z32.h
+
+rsubhnt z0.h, z0.h, z0.h
+rsubhnt z32.b, z0.h, z0.h
+rsubhnt z0.b, z32.h, z0.h
+rsubhnt z0.b, z0.h, z32.h
+
+saba z0.h, z0.b, z0.b
+saba z32.b, z0.b, z0.b
+saba z0.b, z32.b, z0.b
+saba z0.b, z0.b, z32.b
+
+sabalb z0.b, z0.b, z0.b
+sabalb z32.h, z0.b, z0.b
+sabalb z0.h, z32.b, z0.b
+sabalb z0.h, z0.b, z32.b
+
+sabalt z0.b, z0.b, z0.b
+sabalt z32.h, z0.b, z0.b
+sabalt z0.h, z32.b, z0.b
+sabalt z0.h, z0.b, z32.b
+
+sabdlb z0.b, z0.b, z0.b
+sabdlb z32.h, z0.b, z0.b
+sabdlb z0.h, z32.b, z0.b
+sabdlb z0.h, z0.b, z32.b
+
+sabdlt z0.b, z0.b, z0.b
+sabdlt z32.h, z0.b, z0.b
+sabdlt z0.h, z32.b, z0.b
+sabdlt z0.h, z0.b, z32.b
+
+sadalp z0.b, p0/m, z0.b
+sadalp z0.h, p0/z, z0.b
+sadalp z0.h, p8/m, z0.b
+sadalp z32.h, p0/m, z0.b
+sadalp z0.h, p0/m, z32.b
+
+saddlb z0.b, z0.b, z0.b
+saddlb z32.h, z0.b, z0.b
+saddlb z0.h, z32.b, z0.b
+saddlb z0.h, z0.b, z32.b
+
+saddlbt z0.b, z0.b, z0.b
+saddlbt z32.h, z0.b, z0.b
+saddlbt z0.h, z32.b, z0.b
+saddlbt z0.h, z0.b, z32.b
+
+saddlt z0.b, z0.b, z0.b
+saddlt z32.h, z0.b, z0.b
+saddlt z0.h, z32.b, z0.b
+saddlt z0.h, z0.b, z32.b
+
+saddwb z0.b, z0.h, z0.b
+saddwb z32.h, z0.h, z0.b
+saddwb z0.h, z32.h, z0.b
+saddwb z0.h, z0.h, z32.b
+
+saddwt z0.b, z0.h, z0.b
+saddwt z32.h, z0.h, z0.b
+saddwt z0.h, z32.h, z0.b
+saddwt z0.h, z0.h, z32.b
+
+sbclb z0.d, z0.s, z0.s
+sbclb z32.s, z0.s, z0.s
+sbclb z0.s, z32.s, z0.s
+sbclb z0.s, z0.s, z32.s
+
+sbclt z0.d, z0.s, z0.s
+sbclt z32.s, z0.s, z0.s
+sbclt z0.s, z32.s, z0.s
+sbclt z0.s, z0.s, z32.s
+
+shadd z0.b, p0/m, z1.b, z0.b
+shadd z32.b, p0/m, z0.b, z0.b
+shadd z0.b, p8/m, z0.b, z0.b
+shadd z0.b, p0/m, z32.b, z0.b
+shadd z0.b, p0/m, z0.b, z32.b
+shadd z0.h, p0/m, z0.b, z0.b
+shadd z0.b, p0/z, z0.b, z0.b
+
+shrnb z32.b, z0.h, #8
+shrnb z0.b, z32.h, #8
+shrnb z0.b, z0.h, #9
+shrnb z0.b, z0.h, #0
+shrnb z0.h, z0.h, #8
+shrnb z0.h, z0.s, #0
+shrnb z0.h, z0.s, #17
+shrnb z0.s, z0.d, #0
+shrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+shrnt z0.b, z1.h, #8
+
+shrnt z32.b, z0.h, #8
+shrnt z0.b, z32.h, #8
+shrnt z0.b, z0.h, #9
+shrnt z0.b, z0.h, #0
+shrnt z0.h, z0.h, #8
+shrnt z0.h, z0.s, #0
+shrnt z0.h, z0.s, #17
+shrnt z0.s, z0.d, #0
+shrnt z0.s, z0.d, #33
+
+shsub z0.b, p0/m, z1.b, z0.b
+shsub z32.b, p0/m, z0.b, z0.b
+shsub z0.b, p8/m, z0.b, z0.b
+shsub z0.b, p0/m, z32.b, z0.b
+shsub z0.b, p0/m, z0.b, z32.b
+shsub z0.h, p0/m, z0.b, z0.b
+shsub z0.b, p0/z, z0.b, z0.b
+
+shsubr z0.b, p0/m, z1.b, z0.b
+shsubr z32.b, p0/m, z0.b, z0.b
+shsubr z0.b, p8/m, z0.b, z0.b
+shsubr z0.b, p0/m, z32.b, z0.b
+shsubr z0.b, p0/m, z0.b, z32.b
+shsubr z0.h, p0/m, z0.b, z0.b
+shsubr z0.b, p0/z, z0.b, z0.b
+
+sli z0.h, z0.b, #0
+sli z32.b, z0.b, #0
+sli z0.b, z32.b, #0
+sli z0.b, z0.b, #8
+sli z0.h, z0.h, #16
+sli z0.s, z0.s, #32
+sli z0.d, z0.d, #64
+
+movprfx z0, z1
+sm4e z0.s, z0.s, z1.s
+
+sm4e z1.s, z0.s, z0.s
+sm4e z32.s, z0.s, z0.s
+sm4e z0.s, z32.s, z0.s
+sm4e z0.s, z0.s, z32.s
+sm4e z0.s, z0.s, z0.d
+
+sm4ekey z32.s, z0.s, z0.s
+sm4ekey z0.s, z32.s, z0.s
+sm4ekey z0.s, z0.s, z32.s
+sm4ekey z0.s, z0.s, z0.h
+
+smaxp z0.h, p0/m, z0.b, z0.b
+smaxp z0.b, p0/z, z0.b, z0.b
+smaxp z32.b, p0/m, z0.b, z0.b
+smaxp z0.b, p0/m, z32.b, z0.b
+smaxp z0.b, p0/m, z0.b, z32.b
+smaxp z0.b, p8/m, z0.b, z0.b
+
+sminp z0.h, p0/m, z0.b, z0.b
+sminp z0.b, p0/z, z0.b, z0.b
+sminp z32.b, p0/m, z0.b, z0.b
+sminp z0.b, p0/m, z32.b, z0.b
+sminp z0.b, p0/m, z0.b, z32.b
+sminp z0.b, p8/m, z0.b, z0.b
+
+smlalb z32.s, z0.h, z0.h[0]
+smlalb z0.s, z32.h, z0.h[0]
+smlalb z0.s, z0.h, z8.h[0]
+smlalb z0.s, z0.h, z0.h[8]
+smlalb z0.h, z0.h, z0.h[0]
+
+smlalb z32.d, z0.s, z0.s[0]
+smlalb z0.d, z32.s, z0.s[0]
+smlalb z0.d, z0.s, z16.s[0]
+smlalb z0.d, z0.s, z0.s[4]
+smlalb z0.s, z0.s, z0.s[0]
+
+smlalb z32.h, z0.b, z0.b
+smlalb z0.h, z32.b, z0.b
+smlalb z0.h, z0.b, z32.b
+smlalb z0.s, z0.h, z0.x
+smlalb z0.h, z0.b, z0.h
+
+smlalt z32.s, z0.h, z0.h[0]
+smlalt z0.s, z32.h, z0.h[0]
+smlalt z0.s, z0.h, z8.h[0]
+smlalt z0.s, z0.h, z0.h[8]
+smlalt z0.h, z0.h, z0.h[0]
+
+smlalt z32.d, z0.s, z0.s[0]
+smlalt z0.d, z32.s, z0.s[0]
+smlalt z0.d, z0.s, z16.s[0]
+smlalt z0.d, z0.s, z0.s[4]
+smlalt z0.s, z0.s, z0.s[0]
+
+smlalt z32.h, z0.b, z0.b
+smlalt z0.h, z32.b, z0.b
+smlalt z0.h, z0.b, z32.b
+smlalt z0.s, z0.h, z0.x
+smlalt z0.h, z0.b, z0.h
+
+smlslb z32.s, z0.h, z0.h[0]
+smlslb z0.s, z32.h, z0.h[0]
+smlslb z0.s, z0.h, z8.h[0]
+smlslb z0.s, z0.h, z0.h[8]
+smlslb z0.h, z0.h, z0.h[0]
+
+smlslb z32.d, z0.s, z0.s[0]
+smlslb z0.d, z32.s, z0.s[0]
+smlslb z0.d, z0.s, z16.s[0]
+smlslb z0.d, z0.s, z0.s[4]
+smlslb z0.s, z0.s, z0.s[0]
+
+smlslb z32.h, z0.b, z0.b
+smlslb z0.h, z32.b, z0.b
+smlslb z0.h, z0.b, z32.b
+smlslb z0.s, z0.h, z0.x
+smlslb z0.h, z0.b, z0.h
+
+smlslt z32.s, z0.h, z0.h[0]
+smlslt z0.s, z32.h, z0.h[0]
+smlslt z0.s, z0.h, z8.h[0]
+smlslt z0.s, z0.h, z0.h[8]
+smlslt z0.h, z0.h, z0.h[0]
+
+smlslt z32.d, z0.s, z0.s[0]
+smlslt z0.d, z32.s, z0.s[0]
+smlslt z0.d, z0.s, z16.s[0]
+smlslt z0.d, z0.s, z0.s[4]
+smlslt z0.s, z0.s, z0.s[0]
+
+smlslt z32.h, z0.b, z0.b
+smlslt z0.h, z32.b, z0.b
+smlslt z0.h, z0.b, z32.b
+smlslt z0.s, z0.h, z0.x
+smlslt z0.h, z0.b, z0.h
+
+smulh z0.h, z0.b, z0.b
+smulh z32.b, z0.b, z0.b
+smulh z0.b, z32.b, z0.b
+smulh z0.b, z0.b, z32.b
+
+smullb z32.s, z0.h, z0.h[0]
+smullb z0.s, z32.h, z0.h[0]
+smullb z0.s, z0.h, z8.h[0]
+smullb z0.s, z0.h, z0.h[8]
+smullb z0.h, z0.h, z0.h[0]
+
+smullb z32.d, z0.s, z0.s[0]
+smullb z0.d, z32.s, z0.s[0]
+smullb z0.d, z0.s, z16.s[0]
+smullb z0.d, z0.s, z0.s[4]
+smullb z0.s, z0.s, z0.s[0]
+
+smullb z32.h, z0.b, z0.b
+smullb z0.h, z32.b, z0.b
+smullb z0.h, z0.b, z32.b
+smullb z0.s, z0.h, z0.x
+smullb z0.h, z0.b, z0.h
+
+smullt z32.s, z0.h, z0.h[0]
+smullt z0.s, z32.h, z0.h[0]
+smullt z0.s, z0.h, z8.h[0]
+smullt z0.s, z0.h, z0.h[8]
+smullt z0.h, z0.h, z0.h[0]
+
+smullt z32.d, z0.s, z0.s[0]
+smullt z0.d, z32.s, z0.s[0]
+smullt z0.d, z0.s, z16.s[0]
+smullt z0.d, z0.s, z0.s[4]
+smullt z0.s, z0.s, z0.s[0]
+
+smullt z32.h, z0.b, z0.b
+smullt z0.h, z32.b, z0.b
+smullt z0.h, z0.b, z32.b
+smullt z0.s, z0.h, z0.x
+smullt z0.h, z0.b, z0.h
+
+splice z0.b, p0, { z0.b, z2.b }
+splice z0.h, p0, { z0.b, z1.b }
+splice z0.b, p0, { z0.h, z1.b }
+splice z0.b, p0, { z0.b, z1.h }
+splice z32.b, p0, { z0.b, z1.b }
+splice z0.b, p8, { z0.b, z1.b }
+splice z0.b, p0, { z31.b, z1.b }
+splice z0.b, p0, { z31.b, z32.b }
+splice z0.b, p0, { z32.b, z1.b }
+
+sqabs z32.b, p0/m, z0.b
+sqabs z0.b, p8/m, z0.b
+sqabs z0.b, p0/m, z32.b
+sqabs z0.b, p0/m, z0.h
+sqabs z0.b, p0/z, z0.b
+
+sqadd z32.b, p0/m, z0.b, z0.b
+sqadd z0.b, p0/m, z32.b, z0.b
+sqadd z0.b, p0/m, z0.b, z32.b
+sqadd z0.b, p0/m, z1.b, z0.b
+sqadd z0.b, p8/m, z0.b, z0.b
+sqadd z0.h, p0/m, z0.b, z0.b
+sqadd z0.b, p0/z, z0.b, z0.b
+
+sqcadd z0.b, z0.b, z0.b, #180
+sqcadd z0.b, z1.b, z0.b, #90
+sqcadd z32.b, z0.b, z0.b, #90
+sqcadd z0.b, z32.b, z0.b, #90
+sqcadd z0.b, z0.b, z32.b, #90
+sqcadd z0.b, z0.b, z0.h, #90
+
+sqdmlalb z32.s, z0.h, z0.h[0]
+sqdmlalb z0.s, z32.h, z0.h[0]
+sqdmlalb z0.s, z0.h, z8.h[0]
+sqdmlalb z0.s, z0.h, z0.h[8]
+sqdmlalb z0.h, z0.h, z0.h[0]
+
+sqdmlalb z32.d, z0.s, z0.s[0]
+sqdmlalb z0.d, z32.s, z0.s[0]
+sqdmlalb z0.d, z0.s, z16.s[0]
+sqdmlalb z0.d, z0.s, z0.s[4]
+sqdmlalb z0.s, z0.s, z0.s[0]
+
+sqdmlalb z32.h, z0.b, z0.b
+sqdmlalb z0.h, z32.b, z0.b
+sqdmlalb z0.h, z0.b, z32.b
+sqdmlalb z0.s, z0.h, z0.x
+sqdmlalb z0.h, z0.b, z0.h
+
+sqdmlalbt z32.h, z0.b, z0.b
+sqdmlalbt z0.h, z32.b, z0.b
+sqdmlalbt z0.h, z0.b, z32.b
+sqdmlalbt z0.s, z0.h, z0.x
+sqdmlalbt z0.h, z0.b, z0.h
+
+sqdmlalt z32.s, z0.h, z0.h[0]
+sqdmlalt z0.s, z32.h, z0.h[0]
+sqdmlalt z0.s, z0.h, z8.h[0]
+sqdmlalt z0.s, z0.h, z0.h[8]
+sqdmlalt z0.h, z0.h, z0.h[0]
+
+sqdmlalt z32.d, z0.s, z0.s[0]
+sqdmlalt z0.d, z32.s, z0.s[0]
+sqdmlalt z0.d, z0.s, z16.s[0]
+sqdmlalt z0.d, z0.s, z0.s[4]
+sqdmlalt z0.s, z0.s, z0.s[0]
+
+sqdmlalt z32.h, z0.b, z0.b
+sqdmlalt z0.h, z32.b, z0.b
+sqdmlalt z0.h, z0.b, z32.b
+sqdmlalt z0.s, z0.h, z0.x
+sqdmlalt z0.h, z0.b, z0.h
+
+sqdmlslb z32.s, z0.h, z0.h[0]
+sqdmlslb z0.s, z32.h, z0.h[0]
+sqdmlslb z0.s, z0.h, z8.h[0]
+sqdmlslb z0.s, z0.h, z0.h[8]
+sqdmlslb z0.h, z0.h, z0.h[0]
+
+sqdmlslb z32.d, z0.s, z0.s[0]
+sqdmlslb z0.d, z32.s, z0.s[0]
+sqdmlslb z0.d, z0.s, z16.s[0]
+sqdmlslb z0.d, z0.s, z0.s[4]
+sqdmlslb z0.s, z0.s, z0.s[0]
+
+sqdmlslb z32.h, z0.b, z0.b
+sqdmlslb z0.h, z32.b, z0.b
+sqdmlslb z0.h, z0.b, z32.b
+sqdmlslb z0.s, z0.h, z0.x
+sqdmlslb z0.h, z0.b, z0.h
+
+sqdmlslbt z32.h, z0.b, z0.b
+sqdmlslbt z0.h, z32.b, z0.b
+sqdmlslbt z0.h, z0.b, z32.b
+sqdmlslbt z0.s, z0.h, z0.x
+sqdmlslbt z0.h, z0.b, z0.h
+
+sqdmlslt z32.s, z0.h, z0.h[0]
+sqdmlslt z0.s, z32.h, z0.h[0]
+sqdmlslt z0.s, z0.h, z8.h[0]
+sqdmlslt z0.s, z0.h, z0.h[8]
+sqdmlslt z0.h, z0.h, z0.h[0]
+
+sqdmlslt z32.d, z0.s, z0.s[0]
+sqdmlslt z0.d, z32.s, z0.s[0]
+sqdmlslt z0.d, z0.s, z16.s[0]
+sqdmlslt z0.d, z0.s, z0.s[4]
+sqdmlslt z0.s, z0.s, z0.s[0]
+
+sqdmlslt z32.h, z0.b, z0.b
+sqdmlslt z0.h, z32.b, z0.b
+sqdmlslt z0.h, z0.b, z32.b
+sqdmlslt z0.s, z0.h, z0.x
+sqdmlslt z0.h, z0.b, z0.h
+
+sqdmulh z32.h, z0.h, z0.h[0]
+sqdmulh z0.h, z32.h, z0.h[0]
+sqdmulh z0.h, z0.h, z8.h[0]
+sqdmulh z0.h, z0.h, z0.h[8]
+sqdmulh z0.s, z0.h, z0.h[0]
+sqdmulh z0.h, z0.h, z0.s[0]
+
+sqdmulh z32.s, z0.s, z0.s[0]
+sqdmulh z0.s, z32.s, z0.s[0]
+sqdmulh z0.s, z0.s, z8.s[0]
+sqdmulh z0.s, z0.s, z0.s[4]
+sqdmulh z0.s, z0.h, z0.s[0]
+sqdmulh z0.s, z0.s, z0.h[0]
+
+sqdmulh z32.d, z0.d, z0.d[0]
+sqdmulh z0.d, z32.d, z0.d[0]
+sqdmulh z0.d, z0.d, z16.d[0]
+sqdmulh z0.d, z0.d, z0.d[2]
+sqdmulh z0.d, z0.h, z0.d[0]
+sqdmulh z0.d, z0.d, z0.h[0]
+
+sqdmulh z32.h, z0.b, z0.b
+sqdmulh z0.h, z32.b, z0.b
+sqdmulh z0.h, z0.b, z32.b
+sqdmulh z0.s, z0.h, z0.x
+sqdmulh z0.h, z0.b, z0.h
+
+sqdmullb z32.s, z0.h, z0.h[0]
+sqdmullb z0.s, z32.h, z0.h[0]
+sqdmullb z0.s, z0.h, z8.h[0]
+sqdmullb z0.s, z0.h, z0.h[8]
+sqdmullb z0.h, z0.h, z0.h[0]
+
+sqdmullb z32.d, z0.s, z0.s[0]
+sqdmullb z0.d, z32.s, z0.s[0]
+sqdmullb z0.d, z0.s, z16.s[0]
+sqdmullb z0.d, z0.s, z0.s[4]
+sqdmullb z0.s, z0.s, z0.s[0]
+
+sqdmullb z32.h, z0.b, z0.b
+sqdmullb z0.h, z32.b, z0.b
+sqdmullb z0.h, z0.b, z32.b
+sqdmullb z0.s, z0.h, z0.x
+sqdmullb z0.h, z0.b, z0.h
+
+sqdmullt z32.s, z0.h, z0.h[0]
+sqdmullt z0.s, z32.h, z0.h[0]
+sqdmullt z0.s, z0.h, z8.h[0]
+sqdmullt z0.s, z0.h, z0.h[8]
+sqdmullt z0.h, z0.h, z0.h[0]
+
+sqdmullt z32.d, z0.s, z0.s[0]
+sqdmullt z0.d, z32.s, z0.s[0]
+sqdmullt z0.d, z0.s, z16.s[0]
+sqdmullt z0.d, z0.s, z0.s[4]
+sqdmullt z0.s, z0.s, z0.s[0]
+
+sqdmullt z32.h, z0.b, z0.b
+sqdmullt z0.h, z32.b, z0.b
+sqdmullt z0.h, z0.b, z32.b
+sqdmullt z0.s, z0.h, z0.x
+sqdmullt z0.h, z0.b, z0.h
+
+sqneg z32.b, p0/m, z0.b
+sqneg z0.b, p8/m, z0.b
+sqneg z0.b, p0/m, z32.b
+sqneg z0.b, p0/m, z0.h
+sqneg z0.b, p0/z, z0.b
+
+sqrdcmlah z32.h, z0.h, z0.h[0], #0
+sqrdcmlah z0.h, z32.h, z0.h[0], #0
+sqrdcmlah z0.h, z0.h, z8.h[0], #0
+sqrdcmlah z0.h, z0.h, z0.h[4], #0
+sqrdcmlah z0.h, z0.h, z0.h[0], #1
+sqrdcmlah z0.h, z0.h, z0.h[0], #360
+sqrdcmlah z0.h, z0.h, z0.s[0], #0
+sqrdcmlah z0.h, z0.s, z0.h[0], #0
+
+sqrdcmlah z32.s, z0.s, z0.s[0], #0
+sqrdcmlah z0.s, z32.s, z0.s[0], #0
+sqrdcmlah z0.s, z0.s, z16.s[0], #0
+sqrdcmlah z0.s, z0.s, z0.s[2], #0
+sqrdcmlah z0.s, z0.s, z0.s[0], #1
+sqrdcmlah z0.s, z0.s, z0.s[0], #360
+sqrdcmlah z0.s, z0.s, z0.h[0], #0
+sqrdcmlah z0.s, z0.h, z0.s[0], #0
+
+sqrdcmlah z32.b, z0.b, z0.b, #0
+sqrdcmlah z0.b, z32.b, z0.b, #0
+sqrdcmlah z0.b, z0.b, z32.b, #0
+sqrdcmlah z0.b, z0.b, z0.b, #1
+sqrdcmlah z0.b, z0.b, z0.b, #360
+sqrdcmlah z0.b, z0.b, z0.h, #0
+
+sqrdmlah z32.h, z0.h, z0.h[0]
+sqrdmlah z0.h, z32.h, z0.h[0]
+sqrdmlah z0.h, z0.h, z8.h[0]
+sqrdmlah z0.h, z0.h, z0.h[8]
+sqrdmlah z0.s, z0.h, z0.h[0]
+sqrdmlah z0.h, z0.h, z0.s[0]
+
+sqrdmlah z32.s, z0.s, z0.s[0]
+sqrdmlah z0.s, z32.s, z0.s[0]
+sqrdmlah z0.s, z0.s, z8.s[0]
+sqrdmlah z0.s, z0.s, z0.s[4]
+sqrdmlah z0.s, z0.h, z0.s[0]
+sqrdmlah z0.s, z0.s, z0.h[0]
+
+sqrdmlah z32.d, z0.d, z0.d[0]
+sqrdmlah z0.d, z32.d, z0.d[0]
+sqrdmlah z0.d, z0.d, z16.d[0]
+sqrdmlah z0.d, z0.d, z0.d[2]
+sqrdmlah z0.d, z0.h, z0.d[0]
+sqrdmlah z0.d, z0.d, z0.h[0]
+
+sqrdmlah z32.h, z0.b, z0.b
+sqrdmlah z0.h, z32.b, z0.b
+sqrdmlah z0.h, z0.b, z32.b
+sqrdmlah z0.s, z0.h, z0.x
+sqrdmlah z0.h, z0.b, z0.h
+
+sqrdmlsh z32.h, z0.h, z0.h[0]
+sqrdmlsh z0.h, z32.h, z0.h[0]
+sqrdmlsh z0.h, z0.h, z8.h[0]
+sqrdmlsh z0.h, z0.h, z0.h[8]
+sqrdmlsh z0.s, z0.h, z0.h[0]
+sqrdmlsh z0.h, z0.h, z0.s[0]
+
+sqrdmlsh z32.s, z0.s, z0.s[0]
+sqrdmlsh z0.s, z32.s, z0.s[0]
+sqrdmlsh z0.s, z0.s, z8.s[0]
+sqrdmlsh z0.s, z0.s, z0.s[4]
+sqrdmlsh z0.s, z0.h, z0.s[0]
+sqrdmlsh z0.s, z0.s, z0.h[0]
+
+sqrdmlsh z32.d, z0.d, z0.d[0]
+sqrdmlsh z0.d, z32.d, z0.d[0]
+sqrdmlsh z0.d, z0.d, z16.d[0]
+sqrdmlsh z0.d, z0.d, z0.d[2]
+sqrdmlsh z0.d, z0.h, z0.d[0]
+sqrdmlsh z0.d, z0.d, z0.h[0]
+
+sqrdmlsh z32.h, z0.b, z0.b
+sqrdmlsh z0.h, z32.b, z0.b
+sqrdmlsh z0.h, z0.b, z32.b
+sqrdmlsh z0.s, z0.h, z0.x
+sqrdmlsh z0.h, z0.b, z0.h
+
+sqrdmulh z32.h, z0.h, z0.h[0]
+sqrdmulh z0.h, z32.h, z0.h[0]
+sqrdmulh z0.h, z0.h, z8.h[0]
+sqrdmulh z0.h, z0.h, z0.h[8]
+sqrdmulh z0.s, z0.h, z0.h[0]
+sqrdmulh z0.h, z0.h, z0.s[0]
+
+sqrdmulh z32.s, z0.s, z0.s[0]
+sqrdmulh z0.s, z32.s, z0.s[0]
+sqrdmulh z0.s, z0.s, z8.s[0]
+sqrdmulh z0.s, z0.s, z0.s[4]
+sqrdmulh z0.s, z0.h, z0.s[0]
+sqrdmulh z0.s, z0.s, z0.h[0]
+
+sqrdmulh z32.d, z0.d, z0.d[0]
+sqrdmulh z0.d, z32.d, z0.d[0]
+sqrdmulh z0.d, z0.d, z16.d[0]
+sqrdmulh z0.d, z0.d, z0.d[2]
+sqrdmulh z0.d, z0.h, z0.d[0]
+sqrdmulh z0.d, z0.d, z0.h[0]
+
+sqrdmulh z32.h, z0.b, z0.b
+sqrdmulh z0.h, z32.b, z0.b
+sqrdmulh z0.h, z0.b, z32.b
+sqrdmulh z0.s, z0.h, z0.x
+sqrdmulh z0.h, z0.b, z0.h
+
+sqrshl z32.b, p0/m, z0.b, z0.b
+sqrshl z0.b, p0/m, z32.b, z0.b
+sqrshl z0.b, p0/m, z0.b, z32.b
+sqrshl z0.b, p0/m, z1.b, z0.b
+sqrshl z0.b, p8/m, z0.b, z0.b
+sqrshl z0.h, p0/m, z0.b, z0.b
+sqrshl z0.b, p0/z, z0.b, z0.b
+
+sqrshlr z32.b, p0/m, z0.b, z0.b
+sqrshlr z0.b, p0/m, z32.b, z0.b
+sqrshlr z0.b, p0/m, z0.b, z32.b
+sqrshlr z0.b, p0/m, z1.b, z0.b
+sqrshlr z0.b, p8/m, z0.b, z0.b
+sqrshlr z0.h, p0/m, z0.b, z0.b
+sqrshlr z0.b, p0/z, z0.b, z0.b
+
+sqrshrnb z32.b, z0.h, #8
+sqrshrnb z0.b, z32.h, #8
+sqrshrnb z0.b, z0.h, #9
+sqrshrnb z0.b, z0.h, #0
+sqrshrnb z0.h, z0.h, #8
+sqrshrnb z0.h, z0.s, #0
+sqrshrnb z0.h, z0.s, #17
+sqrshrnb z0.s, z0.d, #0
+sqrshrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+sqrshrnt z0.b, z0.h, #1
+
+sqrshrnt z32.b, z0.h, #8
+sqrshrnt z0.b, z32.h, #8
+sqrshrnt z0.b, z0.h, #9
+sqrshrnt z0.b, z0.h, #0
+sqrshrnt z0.h, z0.h, #8
+sqrshrnt z0.h, z0.s, #0
+sqrshrnt z0.h, z0.s, #17
+sqrshrnt z0.s, z0.d, #0
+sqrshrnt z0.s, z0.d, #33
+
+sqrshrunb z32.b, z0.h, #8
+sqrshrunb z0.b, z32.h, #8
+sqrshrunb z0.b, z0.h, #9
+sqrshrunb z0.b, z0.h, #0
+sqrshrunb z0.h, z0.h, #8
+sqrshrunb z0.h, z0.s, #0
+sqrshrunb z0.h, z0.s, #17
+sqrshrunb z0.s, z0.d, #0
+sqrshrunb z0.s, z0.d, #33
+
+movprfx z0, z1
+sqrshrunt z0.b, z0.h, #1
+
+sqrshrunt z32.b, z0.h, #8
+sqrshrunt z0.b, z32.h, #8
+sqrshrunt z0.b, z0.h, #9
+sqrshrunt z0.b, z0.h, #0
+sqrshrunt z0.h, z0.h, #8
+sqrshrunt z0.h, z0.s, #0
+sqrshrunt z0.h, z0.s, #17
+sqrshrunt z0.s, z0.d, #0
+sqrshrunt z0.s, z0.d, #33
+
+sqshl z0.h, p0/m, z0.b, #0
+sqshl z32.b, p0/m, z32.b, #0
+sqshl z0.b, p0/m, z1.b, #0
+sqshl z0.b, p8/m, z0.b, #0
+sqshl z0.b, p0/m, z0.b, #8
+sqshl z0.h, p0/m, z0.h, #16
+sqshl z0.s, p0/m, z0.s, #32
+sqshl z0.d, p0/m, z0.d, #64
+
+sqshl z32.b, p0/m, z0.b, z0.b
+sqshl z0.b, p0/m, z32.b, z0.b
+sqshl z0.b, p0/m, z0.b, z32.b
+sqshl z0.b, p0/m, z1.b, z0.b
+sqshl z0.b, p8/m, z0.b, z0.b
+sqshl z0.h, p0/m, z0.b, z0.b
+sqshl z0.b, p0/z, z0.b, z0.b
+
+sqshlr z32.b, p0/m, z0.b, z0.b
+sqshlr z0.b, p0/m, z32.b, z0.b
+sqshlr z0.b, p0/m, z0.b, z32.b
+sqshlr z0.b, p0/m, z1.b, z0.b
+sqshlr z0.b, p8/m, z0.b, z0.b
+sqshlr z0.h, p0/m, z0.b, z0.b
+sqshlr z0.b, p0/z, z0.b, z0.b
+
+sqshlu z0.h, p0/m, z0.b, #0
+sqshlu z32.b, p0/m, z32.b, #0
+sqshlu z0.b, p0/m, z1.b, #0
+sqshlu z0.b, p8/m, z0.b, #0
+sqshlu z0.b, p0/m, z0.b, #8
+sqshlu z0.h, p0/m, z0.h, #16
+sqshlu z0.s, p0/m, z0.s, #32
+sqshlu z0.d, p0/m, z0.d, #64
+
+sqshrnb z32.b, z0.h, #8
+sqshrnb z0.b, z32.h, #8
+sqshrnb z0.b, z0.h, #9
+sqshrnb z0.b, z0.h, #0
+sqshrnb z0.h, z0.h, #8
+sqshrnb z0.h, z0.s, #0
+sqshrnb z0.h, z0.s, #17
+sqshrnb z0.s, z0.d, #0
+sqshrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+sqshrnt z0.b, z0.h, #1
+
+sqshrnt z32.b, z0.h, #8
+sqshrnt z0.b, z32.h, #8
+sqshrnt z0.b, z0.h, #9
+sqshrnt z0.b, z0.h, #0
+sqshrnt z0.h, z0.h, #8
+sqshrnt z0.h, z0.s, #0
+sqshrnt z0.h, z0.s, #17
+sqshrnt z0.s, z0.d, #0
+sqshrnt z0.s, z0.d, #33
+
+sqshrunb z32.b, z0.h, #8
+sqshrunb z0.b, z32.h, #8
+sqshrunb z0.b, z0.h, #9
+sqshrunb z0.b, z0.h, #0
+sqshrunb z0.h, z0.h, #8
+sqshrunb z0.h, z0.s, #0
+sqshrunb z0.h, z0.s, #17
+sqshrunb z0.s, z0.d, #0
+sqshrunb z0.s, z0.d, #33
+
+movprfx z0, z1
+sqshrunt z0.b, z0.h, #1
+
+sqshrunt z32.b, z0.h, #8
+sqshrunt z0.b, z32.h, #8
+sqshrunt z0.b, z0.h, #9
+sqshrunt z0.b, z0.h, #0
+sqshrunt z0.h, z0.h, #8
+sqshrunt z0.h, z0.s, #0
+sqshrunt z0.h, z0.s, #17
+sqshrunt z0.s, z0.d, #0
+sqshrunt z0.s, z0.d, #33
+
+sqsub z32.b, p0/m, z0.b, z0.b
+sqsub z0.b, p0/m, z32.b, z0.b
+sqsub z0.b, p0/m, z0.b, z32.b
+sqsub z0.b, p0/m, z1.b, z0.b
+sqsub z0.b, p8/m, z0.b, z0.b
+sqsub z0.h, p0/m, z0.b, z0.b
+sqsub z0.b, p0/z, z0.b, z0.b
+
+sqsubr z32.b, p0/m, z0.b, z0.b
+sqsubr z0.b, p0/m, z32.b, z0.b
+sqsubr z0.b, p0/m, z0.b, z32.b
+sqsubr z0.b, p0/m, z1.b, z0.b
+sqsubr z0.b, p8/m, z0.b, z0.b
+sqsubr z0.h, p0/m, z0.b, z0.b
+sqsubr z0.b, p0/z, z0.b, z0.b
+
+sqxtnb z32.b, z0.h
+sqxtnb z0.b, z32.h
+sqxtnb z0.b, z0.s
+
+sqxtnt z32.b, z0.h
+sqxtnt z0.b, z32.h
+sqxtnt z0.b, z0.s
+
+sqxtunb z32.b, z0.h
+sqxtunb z0.b, z32.h
+sqxtunb z0.b, z0.s
+
+sqxtunt z32.b, z0.h
+sqxtunt z0.b, z32.h
+sqxtunt z0.b, z0.s
+
+srhadd z32.b, p0/m, z0.b, z0.b
+srhadd z0.b, p0/m, z32.b, z0.b
+srhadd z0.b, p0/m, z0.b, z32.b
+srhadd z0.b, p0/m, z1.b, z0.b
+srhadd z0.b, p8/m, z0.b, z0.b
+srhadd z0.h, p0/m, z0.b, z0.b
+srhadd z0.b, p0/z, z0.b, z0.b
+
+sri z0.h, z0.b, #1
+sri z32.b, z0.b, #1
+sri z0.b, z32.b, #1
+sri z0.b, z0.b, #0
+sri z0.b, z0.b, #9
+sri z0.h, z0.h, #0
+sri z0.h, z0.h, #17
+sri z0.s, z0.s, #0
+sri z0.s, z0.s, #33
+sri z0.d, z0.d, #0
+sri z0.d, z0.d, #64
+
+srshl z32.b, p0/m, z0.b, z0.b
+srshl z0.b, p0/m, z32.b, z0.b
+srshl z0.b, p0/m, z0.b, z32.b
+srshl z0.b, p0/m, z1.b, z0.b
+srshl z0.b, p8/m, z0.b, z0.b
+srshl z0.h, p0/m, z0.b, z0.b
+srshl z0.b, p0/z, z0.b, z0.b
+
+srshlr z32.b, p0/m, z0.b, z0.b
+srshlr z0.b, p0/m, z32.b, z0.b
+srshlr z0.b, p0/m, z0.b, z32.b
+srshlr z0.b, p0/m, z1.b, z0.b
+srshlr z0.b, p8/m, z0.b, z0.b
+srshlr z0.h, p0/m, z0.b, z0.b
+srshlr z0.b, p0/z, z0.b, z0.b
+
+srshr z0.h, p0/m, z0.b, #1
+srshr z32.b, p0/m, z32.b, #1
+srshr z0.b, p0/m, z1.b, #1
+srshr z0.b, p8/m, z0.b, #1
+srshr z0.b, p0/m, z0.b, #0
+srshr z0.b, p0/m, z0.b, #9
+srshr z0.h, p0/m, z0.h, #0
+srshr z0.h, p0/m, z0.h, #17
+srshr z0.s, p0/m, z0.s, #0
+srshr z0.s, p0/m, z0.s, #33
+srshr z0.d, p0/m, z0.d, #0
+srshr z0.d, p0/m, z0.d, #65
+
+srsra z0.h, z0.b, #1
+srsra z32.b, z0.b, #1
+srsra z0.b, z32.b, #1
+srsra z0.b, z0.b, #0
+srsra z0.b, z0.b, #9
+srsra z0.h, z0.h, #0
+srsra z0.h, z0.h, #17
+srsra z0.s, z0.s, #0
+srsra z0.s, z0.s, #33
+srsra z0.d, z0.d, #0
+srsra z0.d, z0.d, #64
+
+sshllb z0.b, z0.b, #0
+sshllb z32.h, z0.b, #0
+sshllb z0.h, z32.b, #0
+sshllb z0.h, z0.b, #8
+sshllb z0.s, z0.h, #16
+sshllb z0.d, z0.s, #32
+
+sshllt z0.b, z0.b, #0
+sshllt z32.h, z0.b, #0
+sshllt z0.h, z32.b, #0
+sshllt z0.h, z0.b, #8
+sshllt z0.s, z0.h, #16
+sshllt z0.d, z0.s, #32
+
+ssra z0.h, z0.b, #1
+ssra z32.b, z0.b, #1
+ssra z0.b, z32.b, #1
+ssra z0.b, z0.b, #0
+ssra z0.b, z0.b, #9
+ssra z0.h, z0.h, #0
+ssra z0.h, z0.h, #17
+ssra z0.s, z0.s, #0
+ssra z0.s, z0.s, #33
+ssra z0.d, z0.d, #0
+ssra z0.d, z0.d, #64
+
+ssublb z32.h, z0.b, z0.b
+ssublb z0.h, z32.b, z0.b
+ssublb z0.h, z0.b, z32.b
+ssublb z0.s, z0.h, z0.x
+ssublb z0.h, z0.b, z0.h
+
+ssublbt z32.h, z0.b, z0.b
+ssublbt z0.h, z32.b, z0.b
+ssublbt z0.h, z0.b, z32.b
+ssublbt z0.s, z0.h, z0.x
+ssublbt z0.h, z0.b, z0.h
+
+ssublt z32.h, z0.b, z0.b
+ssublt z0.h, z32.b, z0.b
+ssublt z0.h, z0.b, z32.b
+ssublt z0.s, z0.h, z0.x
+ssublt z0.h, z0.b, z0.h
+
+ssubltb z32.h, z0.b, z0.b
+ssubltb z0.h, z32.b, z0.b
+ssubltb z0.h, z0.b, z32.b
+ssubltb z0.s, z0.h, z0.x
+ssubltb z0.h, z0.b, z0.h
+
+ssubwb z32.h, z0.h, z0.b
+ssubwb z0.h, z32.h, z0.b
+ssubwb z0.h, z0.h, z32.b
+ssubwb z0.s, z0.s, z0.x
+ssubwb z0.h, z0.h, z0.h
+
+ssubwt z32.h, z0.h, z0.b
+ssubwt z0.h, z32.h, z0.b
+ssubwt z0.h, z0.h, z32.b
+ssubwt z0.s, z0.s, z0.x
+ssubwt z0.h, z0.h, z0.h
+
+stnt1b { z0.d, z1.d }, p0, [z0.d, x0]
+stnt1b { z0.d }, p0/m, [z0.d]
+stnt1b { z32.d }, p0, [z0.d]
+stnt1b { z0.d }, p8, [z0.d]
+stnt1b { z0.d }, p0, [z32.d]
+stnt1b { z0.d }, p0, [z0.d, sp]
+stnt1b { z0.d }, p0, [z0.d, x32]
+stnt1b { z0.d }, p0, [z0.d, w16]
+stnt1b { z0.d }, p0, [z0.d, z0.d]
+stnt1b { z0.s }, p0, [z0.d]
+stnt1b { z0.s, z1.d }, p0, [z0.s, x0]
+stnt1b { z32.s }, p0, [z0.s]
+stnt1b { z0.s }, p8, [z0.s]
+stnt1b { z0.s }, p0, [z32.s]
+stnt1b { z0.s }, p0, [z0.s, sp]
+stnt1b { z0.s }, p0, [z0.s, x32]
+stnt1b { z0.s }, p0, [z0.s, z0.s]
+
+stnt1d { z0.d, z1.d }, p0, [z0.d, x0]
+stnt1d { z0.d }, p0/m, [z0.d]
+stnt1d { z32.d }, p0, [z0.d]
+stnt1d { z0.d }, p8, [z0.d]
+stnt1d { z0.d }, p0, [z32.d]
+stnt1d { z0.d }, p0, [z0.d, sp]
+stnt1d { z0.d }, p0, [z0.d, x32]
+stnt1d { z0.d }, p0, [z0.d, w16]
+stnt1d { z0.d }, p0, [z0.d, z0.d]
+stnt1d { z0.s }, p0, [z0.d]
+
+stnt1h { z0.d, z1.d }, p0, [z0.d, x0]
+stnt1h { z0.d }, p0/m, [z0.d]
+stnt1h { z32.d }, p0, [z0.d]
+stnt1h { z0.d }, p8, [z0.d]
+stnt1h { z0.d }, p0, [z32.d]
+stnt1h { z0.d }, p0, [z0.d, sp]
+stnt1h { z0.d }, p0, [z0.d, x32]
+stnt1h { z0.d }, p0, [z0.d, w16]
+stnt1h { z0.d }, p0, [z0.d, z0.d]
+stnt1h { z0.s }, p0, [z0.d]
+stnt1h { z0.s, z1.d }, p0, [z0.s, x0]
+stnt1h { z32.s }, p0, [z0.s]
+stnt1h { z0.s }, p8, [z0.s]
+stnt1h { z0.s }, p0, [z32.s]
+stnt1h { z0.s }, p0, [z0.s, sp]
+stnt1h { z0.s }, p0, [z0.s, x32]
+stnt1h { z0.s }, p0, [z0.s, z0.s]
+
+stnt1w { z0.d, z1.d }, p0, [z0.d, x0]
+stnt1w { z0.d }, p0/m, [z0.d]
+stnt1w { z32.d }, p0, [z0.d]
+stnt1w { z0.d }, p8, [z0.d]
+stnt1w { z0.d }, p0, [z32.d]
+stnt1w { z0.d }, p0, [z0.d, sp]
+stnt1w { z0.d }, p0, [z0.d, x32]
+stnt1w { z0.d }, p0, [z0.d, w16]
+stnt1w { z0.d }, p0, [z0.d, z0.d]
+stnt1w { z0.s }, p0, [z0.d]
+stnt1w { z0.s, z1.d }, p0, [z0.s, x0]
+stnt1w { z32.s }, p0, [z0.s]
+stnt1w { z0.s }, p8, [z0.s]
+stnt1w { z0.s }, p0, [z32.s]
+stnt1w { z0.s }, p0, [z0.s, sp]
+stnt1w { z0.s }, p0, [z0.s, x32]
+stnt1w { z0.s }, p0, [z0.s, z0.s]
+
+subhnb z0.h, z0.h, z0.h
+subhnb z32.b, z0.h, z0.h
+subhnb z0.b, z32.h, z0.h
+subhnb z0.b, z0.h, z32.h
+
+subhnt z0.h, z0.h, z0.h
+subhnt z32.b, z0.h, z0.h
+subhnt z0.b, z32.h, z0.h
+subhnt z0.b, z0.h, z32.h
+
+suqadd z32.b, p0/m, z0.b, z0.b
+suqadd z0.b, p0/m, z32.b, z0.b
+suqadd z0.b, p0/m, z0.b, z32.b
+suqadd z0.b, p0/m, z1.b, z0.b
+suqadd z0.b, p8/m, z0.b, z0.b
+suqadd z0.h, p0/m, z0.b, z0.b
+suqadd z0.b, p0/z, z0.b, z0.b
+
+tbl z32.b, { z0.b, z1.b }, z0.b
+tbl z0.b, { z31.b, z32.b }, z0.b
+tbl z0.b, { z31.b, z1.b }, z0.b
+tbl z0.b, { z0.b, z1.b }, z32.b
+tbl z0.b, { z0.b, z1.b }, z0.h
+tbl z0.b, { z0.b, z1.h }, z0.b
+tbl z0.b, { z0.h, z0.b }, z0.b
+tbl z0.h, { z0.b, z0.b }, z0.b
+
+tbx z32.h, z0.b, z0.b
+tbx z0.h, z32.b, z0.b
+tbx z0.h, z0.b, z32.b
+tbx z0.s, z0.h, z0.x
+tbx z0.h, z0.b, z0.h
+
+uaba z32.h, z0.b, z0.b
+uaba z0.h, z32.b, z0.b
+uaba z0.h, z0.b, z32.b
+uaba z0.s, z0.h, z0.x
+uaba z0.h, z0.b, z0.h
+
+uabalb z32.h, z0.b, z0.b
+uabalb z0.h, z32.b, z0.b
+uabalb z0.h, z0.b, z32.b
+uabalb z0.s, z0.h, z0.x
+uabalb z0.h, z0.b, z0.h
+
+uabalt z32.h, z0.b, z0.b
+uabalt z0.h, z32.b, z0.b
+uabalt z0.h, z0.b, z32.b
+uabalt z0.s, z0.h, z0.x
+uabalt z0.h, z0.b, z0.h
+
+uabdlb z32.h, z0.b, z0.b
+uabdlb z0.h, z32.b, z0.b
+uabdlb z0.h, z0.b, z32.b
+uabdlb z0.s, z0.h, z0.x
+uabdlb z0.h, z0.b, z0.h
+
+uabdlt z32.h, z0.b, z0.b
+uabdlt z0.h, z32.b, z0.b
+uabdlt z0.h, z0.b, z32.b
+uabdlt z0.s, z0.h, z0.x
+uabdlt z0.h, z0.b, z0.h
+
+uadalp z0.b, p0/m, z0.b
+uadalp z0.h, p0/z, z0.b
+uadalp z0.h, p8/m, z0.b
+uadalp z32.h, p0/m, z0.b
+uadalp z0.h, p0/m, z32.b
+
+uaddlb z32.h, z0.b, z0.b
+uaddlb z0.h, z32.b, z0.b
+uaddlb z0.h, z0.b, z32.b
+uaddlb z0.s, z0.h, z0.x
+uaddlb z0.h, z0.b, z0.h
+
+uaddlt z32.h, z0.b, z0.b
+uaddlt z0.h, z32.b, z0.b
+uaddlt z0.h, z0.b, z32.b
+uaddlt z0.s, z0.h, z0.x
+uaddlt z0.h, z0.b, z0.h
+
+uaddwb z32.h, z0.h, z0.b
+uaddwb z0.h, z32.h, z0.b
+uaddwb z0.h, z0.h, z32.b
+uaddwb z0.s, z0.s, z0.x
+uaddwb z0.h, z0.h, z0.h
+
+uaddwt z32.h, z0.h, z0.b
+uaddwt z0.h, z32.h, z0.b
+uaddwt z0.h, z0.h, z32.b
+uaddwt z0.s, z0.s, z0.x
+uaddwt z0.h, z0.h, z0.h
+
+uhadd z32.b, p0/m, z0.b, z0.b
+uhadd z0.b, p0/m, z32.b, z0.b
+uhadd z0.b, p0/m, z0.b, z32.b
+uhadd z0.b, p0/m, z1.b, z0.b
+uhadd z0.b, p8/m, z0.b, z0.b
+uhadd z0.h, p0/m, z0.b, z0.b
+uhadd z0.b, p0/z, z0.b, z0.b
+
+uhsub z32.b, p0/m, z0.b, z0.b
+uhsub z0.b, p0/m, z32.b, z0.b
+uhsub z0.b, p0/m, z0.b, z32.b
+uhsub z0.b, p0/m, z1.b, z0.b
+uhsub z0.b, p8/m, z0.b, z0.b
+uhsub z0.h, p0/m, z0.b, z0.b
+uhsub z0.b, p0/z, z0.b, z0.b
+
+uhsubr z32.b, p0/m, z0.b, z0.b
+uhsubr z0.b, p0/m, z32.b, z0.b
+uhsubr z0.b, p0/m, z0.b, z32.b
+uhsubr z0.b, p0/m, z1.b, z0.b
+uhsubr z0.b, p8/m, z0.b, z0.b
+uhsubr z0.h, p0/m, z0.b, z0.b
+uhsubr z0.b, p0/z, z0.b, z0.b
+
+umaxp z32.b, p0/m, z0.b, z0.b
+umaxp z0.b, p0/m, z32.b, z0.b
+umaxp z0.b, p0/m, z0.b, z32.b
+umaxp z0.b, p0/m, z1.b, z0.b
+umaxp z0.b, p8/m, z0.b, z0.b
+umaxp z0.h, p0/m, z0.b, z0.b
+umaxp z0.b, p0/z, z0.b, z0.b
+
+uminp z32.b, p0/m, z0.b, z0.b
+uminp z0.b, p0/m, z32.b, z0.b
+uminp z0.b, p0/m, z0.b, z32.b
+uminp z0.b, p0/m, z1.b, z0.b
+uminp z0.b, p8/m, z0.b, z0.b
+uminp z0.h, p0/m, z0.b, z0.b
+uminp z0.b, p0/z, z0.b, z0.b
+
+umlalb z32.s, z0.h, z0.h[0]
+umlalb z0.s, z32.h, z0.h[0]
+umlalb z0.s, z0.h, z8.h[0]
+umlalb z0.s, z0.h, z0.h[8]
+umlalb z0.h, z0.h, z0.h[0]
+
+umlalb z32.d, z0.s, z0.s[0]
+umlalb z0.d, z32.s, z0.s[0]
+umlalb z0.d, z0.s, z16.s[0]
+umlalb z0.d, z0.s, z0.s[4]
+umlalb z0.s, z0.s, z0.s[0]
+
+umlalb z32.h, z0.b, z0.b
+umlalb z0.h, z32.b, z0.b
+umlalb z0.h, z0.b, z32.b
+umlalb z0.s, z0.h, z0.x
+umlalb z0.h, z0.b, z0.h
+
+umlalt z32.s, z0.h, z0.h[0]
+umlalt z0.s, z32.h, z0.h[0]
+umlalt z0.s, z0.h, z8.h[0]
+umlalt z0.s, z0.h, z0.h[8]
+umlalt z0.h, z0.h, z0.h[0]
+
+umlalt z32.d, z0.s, z0.s[0]
+umlalt z0.d, z32.s, z0.s[0]
+umlalt z0.d, z0.s, z16.s[0]
+umlalt z0.d, z0.s, z0.s[4]
+umlalt z0.s, z0.s, z0.s[0]
+
+umlalt z32.h, z0.b, z0.b
+umlalt z0.h, z32.b, z0.b
+umlalt z0.h, z0.b, z32.b
+umlalt z0.s, z0.h, z0.x
+umlalt z0.h, z0.b, z0.h
+
+umlslb z32.s, z0.h, z0.h[0]
+umlslb z0.s, z32.h, z0.h[0]
+umlslb z0.s, z0.h, z8.h[0]
+umlslb z0.s, z0.h, z0.h[8]
+umlslb z0.h, z0.h, z0.h[0]
+
+umlslb z32.d, z0.s, z0.s[0]
+umlslb z0.d, z32.s, z0.s[0]
+umlslb z0.d, z0.s, z16.s[0]
+umlslb z0.d, z0.s, z0.s[4]
+umlslb z0.s, z0.s, z0.s[0]
+
+umlslb z32.h, z0.b, z0.b
+umlslb z0.h, z32.b, z0.b
+umlslb z0.h, z0.b, z32.b
+umlslb z0.s, z0.h, z0.x
+umlslb z0.h, z0.b, z0.h
+
+umlslt z32.s, z0.h, z0.h[0]
+umlslt z0.s, z32.h, z0.h[0]
+umlslt z0.s, z0.h, z8.h[0]
+umlslt z0.s, z0.h, z0.h[8]
+umlslt z0.h, z0.h, z0.h[0]
+
+umlslt z32.d, z0.s, z0.s[0]
+umlslt z0.d, z32.s, z0.s[0]
+umlslt z0.d, z0.s, z16.s[0]
+umlslt z0.d, z0.s, z0.s[4]
+umlslt z0.s, z0.s, z0.s[0]
+
+umlslt z32.h, z0.b, z0.b
+umlslt z0.h, z32.b, z0.b
+umlslt z0.h, z0.b, z32.b
+umlslt z0.s, z0.h, z0.x
+umlslt z0.h, z0.b, z0.h
+
+umulh z32.h, z0.b, z0.b
+umulh z0.h, z32.b, z0.b
+umulh z0.h, z0.b, z32.b
+umulh z0.s, z0.h, z0.x
+umulh z0.h, z0.b, z0.h
+
+umullb z32.s, z0.h, z0.h[0]
+umullb z0.s, z32.h, z0.h[0]
+umullb z0.s, z0.h, z8.h[0]
+umullb z0.s, z0.h, z0.h[8]
+umullb z0.h, z0.h, z0.h[0]
+
+umullb z32.d, z0.s, z0.s[0]
+umullb z0.d, z32.s, z0.s[0]
+umullb z0.d, z0.s, z16.s[0]
+umullb z0.d, z0.s, z0.s[4]
+umullb z0.s, z0.s, z0.s[0]
+
+umullb z32.h, z0.b, z0.b
+umullb z0.h, z32.b, z0.b
+umullb z0.h, z0.b, z32.b
+umullb z0.s, z0.h, z0.x
+umullb z0.h, z0.b, z0.h
+
+umullt z32.s, z0.h, z0.h[0]
+umullt z0.s, z32.h, z0.h[0]
+umullt z0.s, z0.h, z8.h[0]
+umullt z0.s, z0.h, z0.h[8]
+umullt z0.h, z0.h, z0.h[0]
+
+umullt z32.d, z0.s, z0.s[0]
+umullt z0.d, z32.s, z0.s[0]
+umullt z0.d, z0.s, z16.s[0]
+umullt z0.d, z0.s, z0.s[4]
+umullt z0.s, z0.s, z0.s[0]
+
+umullt z32.h, z0.b, z0.b
+umullt z0.h, z32.b, z0.b
+umullt z0.h, z0.b, z32.b
+umullt z0.s, z0.h, z0.x
+umullt z0.h, z0.b, z0.h
+
+uqadd z32.b, p0/m, z0.b, z0.b
+uqadd z0.b, p0/m, z32.b, z0.b
+uqadd z0.b, p0/m, z0.b, z32.b
+uqadd z0.b, p0/m, z1.b, z0.b
+uqadd z0.b, p8/m, z0.b, z0.b
+uqadd z0.h, p0/m, z0.b, z0.b
+uqadd z0.b, p0/z, z0.b, z0.b
+
+uqrshl z32.b, p0/m, z0.b, z0.b
+uqrshl z0.b, p0/m, z32.b, z0.b
+uqrshl z0.b, p0/m, z0.b, z32.b
+uqrshl z0.b, p0/m, z1.b, z0.b
+uqrshl z0.b, p8/m, z0.b, z0.b
+uqrshl z0.h, p0/m, z0.b, z0.b
+uqrshl z0.b, p0/z, z0.b, z0.b
+
+uqrshlr z32.b, p0/m, z0.b, z0.b
+uqrshlr z0.b, p0/m, z32.b, z0.b
+uqrshlr z0.b, p0/m, z0.b, z32.b
+uqrshlr z0.b, p0/m, z1.b, z0.b
+uqrshlr z0.b, p8/m, z0.b, z0.b
+uqrshlr z0.h, p0/m, z0.b, z0.b
+uqrshlr z0.b, p0/z, z0.b, z0.b
+
+uqrshrnb z32.b, z0.h, #8
+uqrshrnb z0.b, z32.h, #8
+uqrshrnb z0.b, z0.h, #9
+uqrshrnb z0.b, z0.h, #0
+uqrshrnb z0.h, z0.h, #8
+uqrshrnb z0.h, z0.s, #0
+uqrshrnb z0.h, z0.s, #17
+uqrshrnb z0.s, z0.d, #0
+uqrshrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+uqrshrnt z0.b, z0.h, #1
+
+uqrshrnt z32.b, z0.h, #8
+uqrshrnt z0.b, z32.h, #8
+uqrshrnt z0.b, z0.h, #9
+uqrshrnt z0.b, z0.h, #0
+uqrshrnt z0.h, z0.h, #8
+uqrshrnt z0.h, z0.s, #0
+uqrshrnt z0.h, z0.s, #17
+uqrshrnt z0.s, z0.d, #0
+uqrshrnt z0.s, z0.d, #33
+
+uqshl z0.h, p0/m, z0.b, #0
+uqshl z32.b, p0/m, z32.b, #0
+uqshl z0.b, p0/m, z1.b, #0
+uqshl z0.b, p8/m, z0.b, #0
+uqshl z0.b, p0/m, z0.b, #8
+uqshl z0.h, p0/m, z0.h, #16
+uqshl z0.s, p0/m, z0.s, #32
+uqshl z0.d, p0/m, z0.d, #64
+
+uqshl z32.b, p0/m, z0.b, z0.b
+uqshl z0.b, p0/m, z32.b, z0.b
+uqshl z0.b, p0/m, z0.b, z32.b
+uqshl z0.b, p0/m, z1.b, z0.b
+uqshl z0.b, p8/m, z0.b, z0.b
+uqshl z0.h, p0/m, z0.b, z0.b
+uqshl z0.b, p0/z, z0.b, z0.b
+
+uqshlr z32.b, p0/m, z0.b, z0.b
+uqshlr z0.b, p0/m, z32.b, z0.b
+uqshlr z0.b, p0/m, z0.b, z32.b
+uqshlr z0.b, p0/m, z1.b, z0.b
+uqshlr z0.b, p8/m, z0.b, z0.b
+uqshlr z0.h, p0/m, z0.b, z0.b
+uqshlr z0.b, p0/z, z0.b, z0.b
+
+uqshrnb z32.b, z0.h, #8
+uqshrnb z0.b, z32.h, #8
+uqshrnb z0.b, z0.h, #9
+uqshrnb z0.b, z0.h, #0
+uqshrnb z0.h, z0.h, #8
+uqshrnb z0.h, z0.s, #0
+uqshrnb z0.h, z0.s, #17
+uqshrnb z0.s, z0.d, #0
+uqshrnb z0.s, z0.d, #33
+
+movprfx z0, z1
+uqshrnt z0.b, z0.h, #1
+
+uqshrnt z32.b, z0.h, #8
+uqshrnt z0.b, z32.h, #8
+uqshrnt z0.b, z0.h, #9
+uqshrnt z0.b, z0.h, #0
+uqshrnt z0.h, z0.h, #8
+uqshrnt z0.h, z0.s, #0
+uqshrnt z0.h, z0.s, #17
+uqshrnt z0.s, z0.d, #0
+uqshrnt z0.s, z0.d, #33
+
+uqsub z32.b, p0/m, z0.b, z0.b
+uqsub z0.b, p0/m, z32.b, z0.b
+uqsub z0.b, p0/m, z0.b, z32.b
+uqsub z0.b, p0/m, z1.b, z0.b
+uqsub z0.b, p8/m, z0.b, z0.b
+uqsub z0.h, p0/m, z0.b, z0.b
+uqsub z0.b, p0/z, z0.b, z0.b
+
+uqsubr z32.b, p0/m, z0.b, z0.b
+uqsubr z0.b, p0/m, z32.b, z0.b
+uqsubr z0.b, p0/m, z0.b, z32.b
+uqsubr z0.b, p0/m, z1.b, z0.b
+uqsubr z0.b, p8/m, z0.b, z0.b
+uqsubr z0.h, p0/m, z0.b, z0.b
+uqsubr z0.b, p0/z, z0.b, z0.b
+
+uqxtnb z32.b, z0.h
+uqxtnb z0.b, z32.h
+uqxtnb z0.b, z0.s
+
+uqxtnt z32.b, z0.h
+uqxtnt z0.b, z32.h
+uqxtnt z0.b, z0.s
+
+urecpe z32.s, p0/m, z0.s
+urecpe z0.s, p0/m, z32.s
+urecpe z0.s, p8/m, z0.s
+urecpe z0.d, p0/m, z0.s
+
+urhadd z32.b, p0/m, z0.b, z0.b
+urhadd z0.b, p0/m, z32.b, z0.b
+urhadd z0.b, p0/m, z0.b, z32.b
+urhadd z0.b, p0/m, z1.b, z0.b
+urhadd z0.b, p8/m, z0.b, z0.b
+urhadd z0.h, p0/m, z0.b, z0.b
+urhadd z0.b, p0/z, z0.b, z0.b
+
+urshl z32.b, p0/m, z0.b, z0.b
+urshl z0.b, p0/m, z32.b, z0.b
+urshl z0.b, p0/m, z0.b, z32.b
+urshl z0.b, p0/m, z1.b, z0.b
+urshl z0.b, p8/m, z0.b, z0.b
+urshl z0.h, p0/m, z0.b, z0.b
+urshl z0.b, p0/z, z0.b, z0.b
+
+urshlr z32.b, p0/m, z0.b, z0.b
+urshlr z0.b, p0/m, z32.b, z0.b
+urshlr z0.b, p0/m, z0.b, z32.b
+urshlr z0.b, p0/m, z1.b, z0.b
+urshlr z0.b, p8/m, z0.b, z0.b
+urshlr z0.h, p0/m, z0.b, z0.b
+urshlr z0.b, p0/z, z0.b, z0.b
+
+urshr z0.h, p0/m, z0.b, #1
+urshr z32.b, p0/m, z32.b, #1
+urshr z0.b, p0/m, z1.b, #1
+urshr z0.b, p8/m, z0.b, #1
+urshr z0.b, p0/m, z0.b, #0
+urshr z0.b, p0/m, z0.b, #9
+urshr z0.h, p0/m, z0.h, #0
+urshr z0.h, p0/m, z0.h, #17
+urshr z0.s, p0/m, z0.s, #0
+urshr z0.s, p0/m, z0.s, #33
+urshr z0.d, p0/m, z0.d, #0
+urshr z0.d, p0/m, z0.d, #65
+
+ursqrte z32.s, p0/m, z0.s
+ursqrte z0.s, p0/m, z32.s
+ursqrte z0.s, p8/m, z0.s
+ursqrte z0.d, p0/m, z0.s
+
+ursra z0.h, z0.b, #1
+ursra z32.b, z0.b, #1
+ursra z0.b, z32.b, #1
+ursra z0.b, z0.b, #0
+ursra z0.b, z0.b, #9
+ursra z0.h, z0.h, #0
+ursra z0.h, z0.h, #17
+ursra z0.s, z0.s, #0
+ursra z0.s, z0.s, #33
+ursra z0.d, z0.d, #0
+ursra z0.d, z0.d, #64
+
+ushllb z0.b, z0.b, #0
+ushllb z32.h, z0.b, #0
+ushllb z0.h, z32.b, #0
+ushllb z0.h, z0.b, #8
+ushllb z0.s, z0.h, #16
+ushllb z0.d, z0.s, #32
+
+ushllt z0.b, z0.b, #0
+ushllt z32.h, z0.b, #0
+ushllt z0.h, z32.b, #0
+ushllt z0.h, z0.b, #8
+ushllt z0.s, z0.h, #16
+ushllt z0.d, z0.s, #32
+
+usqadd z32.b, p0/m, z0.b, z0.b
+usqadd z0.b, p0/m, z32.b, z0.b
+usqadd z0.b, p0/m, z0.b, z32.b
+usqadd z0.b, p0/m, z1.b, z0.b
+usqadd z0.b, p8/m, z0.b, z0.b
+usqadd z0.h, p0/m, z0.b, z0.b
+usqadd z0.b, p0/z, z0.b, z0.b
+
+usra z0.h, z0.b, #1
+usra z32.b, z0.b, #1
+usra z0.b, z32.b, #1
+usra z0.b, z0.b, #0
+usra z0.b, z0.b, #9
+usra z0.h, z0.h, #0
+usra z0.h, z0.h, #17
+usra z0.s, z0.s, #0
+usra z0.s, z0.s, #33
+usra z0.d, z0.d, #0
+usra z0.d, z0.d, #64
+
+usublb z32.h, z0.b, z0.b
+usublb z0.h, z32.b, z0.b
+usublb z0.h, z0.b, z32.b
+usublb z0.s, z0.h, z0.x
+usublb z0.h, z0.b, z0.h
+
+usublt z32.h, z0.b, z0.b
+usublt z0.h, z32.b, z0.b
+usublt z0.h, z0.b, z32.b
+usublt z0.s, z0.h, z0.x
+usublt z0.h, z0.b, z0.h
+
+usubwb z32.h, z0.h, z0.b
+usubwb z0.h, z32.h, z0.b
+usubwb z0.h, z0.h, z32.b
+usubwb z0.s, z0.s, z0.x
+usubwb z0.h, z0.h, z0.h
+
+usubwt z32.h, z0.h, z0.b
+usubwt z0.h, z32.h, z0.b
+usubwt z0.h, z0.h, z32.b
+usubwt z0.s, z0.s, z0.x
+usubwt z0.h, z0.h, z0.h
+
+whilege p16.b, x0, x0
+whilege p0.b, x32, x0
+whilege p0.b, x0, x32
+whilege p0/m, x0, x0
+whilege p0.b, x31, x0
+whilege p0.b, x0, x31
+
+whilege p0.b, x0, w0
+whilege p0.b, w0, x0
+
+whilege p16.b, w0, w0
+whilege p0.b, w32, w0
+whilege p0.b, w0, w32
+whilege p0/m, w0, w0
+whilege p0.b, w31, w0
+whilege p0.b, w0, w31
+
+whilegt p16.b, x0, x0
+whilegt p0.b, x32, x0
+whilegt p0.b, x0, x32
+whilegt p0/m, x0, x0
+whilegt p0.b, x31, x0
+whilegt p0.b, x0, x31
+
+whilegt p0.b, x0, w0
+whilegt p0.b, w0, x0
+
+whilegt p16.b, w0, w0
+whilegt p0.b, w32, w0
+whilegt p0.b, w0, w32
+whilegt p0/m, w0, w0
+whilegt p0.b, w31, w0
+whilegt p0.b, w0, w31
+
+whilehi p16.b, x0, x0
+whilehi p0.b, x32, x0
+whilehi p0.b, x0, x32
+whilehi p0/m, x0, x0
+whilehi p0.b, x31, x0
+whilehi p0.b, x0, x31
+
+whilehi p0.b, x0, w0
+whilehi p0.b, w0, x0
+
+whilehi p16.b, w0, w0
+whilehi p0.b, w32, w0
+whilehi p0.b, w0, w32
+whilehi p0/m, w0, w0
+whilehi p0.b, w31, w0
+whilehi p0.b, w0, w31
+
+whilehs p16.b, x0, x0
+whilehs p0.b, x32, x0
+whilehs p0.b, x0, x32
+whilehs p0/m, x0, x0
+whilehs p0.b, x31, x0
+whilehs p0.b, x0, x31
+
+whilehs p0.b, x0, w0
+whilehs p0.b, w0, x0
+
+whilehs p16.b, w0, w0
+whilehs p0.b, w32, w0
+whilehs p0.b, w0, w32
+whilehs p0/m, w0, w0
+whilehs p0.b, w31, w0
+whilehs p0.b, w0, w31
+
+whilerw p0.b, w0, x0
+whilerw p0/m, x0, x0
+whilerw p0.b, x32, x0
+whilerw p16.b, x0, x0
+
+whilewr p0.b, w0, x0
+whilewr p0/m, x0, x0
+whilewr p0.b, x32, x0
+whilewr p16.b, x0, x0
+
+xar z0.h, z0.b, z0.b, #1
+xar z0.b, z1.b, z0.b, #1
+xar z32.b, z32.b, z0.b, #1
+xar z0.b, z0.b, z32.b, #1
+xar z0.b, z0.b, z0.b, #0
+xar z0.b, z0.b, z0.b, #9
+xar z0.h, z0.h, z0.h, #0
+xar z0.h, z0.h, z0.h, #17
+xar z0.s, z0.s, z0.s, #0
+xar z0.s, z0.s, z0.s, #33
+xar z0.d, z0.d, z0.d, #0
+xar z0.d, z0.d, z0.d, #64
diff --git a/gas/testsuite/gas/aarch64/sve1-extended-sve2.s b/gas/testsuite/gas/aarch64/sve1-extended-sve2.s
new file mode 100644
index 0000000..8eec458
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve1-extended-sve2.s
@@ -0,0 +1,137 @@
+/*
+   Those instructions from the sve2.s file that share mnemonics with
+   instructions in SVE.
+   Created with the below command
+`grep -E '^(ext|ldnt1b|ldnt1d|ldnt1h|ldnt1w|mla|mls|mul|smulh|splice|sqadd|sqsub|stnt1b|stnt1d|stnt1h|stnt1w|tbl|umulh|uqadd|uqsub)\b' sve2.s`
+
+   This test file is here to ensure those instructions with shared mnemonics do
+   not work when assembled with only +sve enabled.
+*/
+
+ext z17.b, { z21.b, z22.b }, #221
+ext z0.b, { z0.b, z1.b }, #0
+ext z0.b, { z31.b, z0.b }, #0
+ldnt1b { z17.d }, p5/z, [z21.d, x27]
+ldnt1b { z0.d }, p0/z, [z0.d, x0]
+ldnt1b { z0.d }, p0/z, [z0.d]
+ldnt1b { z0.d }, p0/z, [z0.d, xzr]
+ldnt1b { z17.s }, p5/z, [z21.s, x27]
+ldnt1b { z0.s }, p0/z, [z0.s, x0]
+ldnt1b { z0.s }, p0/z, [z0.s]
+ldnt1b { z0.s }, p0/z, [z0.s, xzr]
+ldnt1d { z17.d }, p5/z, [z21.d, x27]
+ldnt1d { z0.d }, p0/z, [z0.d, x0]
+ldnt1d { z0.d }, p0/z, [z0.d]
+ldnt1d { z0.d }, p0/z, [z0.d, xzr]
+ldnt1h { z17.d }, p5/z, [z21.d, x27]
+ldnt1h { z0.d }, p0/z, [z0.d, x0]
+ldnt1h { z0.d }, p0/z, [z0.d]
+ldnt1h { z0.d }, p0/z, [z0.d, xzr]
+ldnt1h { z17.s }, p5/z, [z21.s, x27]
+ldnt1h { z0.s }, p0/z, [z0.s, x0]
+ldnt1h { z0.s }, p0/z, [z0.s]
+ldnt1h { z0.s }, p0/z, [z0.s, xzr]
+ldnt1w { z17.s }, p5/z, [z21.s, x27]
+ldnt1w { z0.s }, p0/z, [z0.s, x0]
+ldnt1w { z0.s }, p0/z, [z0.s]
+ldnt1w { z0.s }, p0/z, [z0.s, xzr]
+ldnt1w { z17.d }, p5/z, [z21.d, x27]
+ldnt1w { z0.d }, p0/z, [z0.d, x0]
+ldnt1w { z0.d }, p0/z, [z0.d]
+ldnt1w { z0.d }, p0/z, [z0.d, xzr]
+mla z17.h, z21.h, z3.h[3]
+mla z0.h, z0.h, z0.h[4]
+mla z0.h, z0.h, z0.h[0]
+mla z17.s, z21.s, z3.s[3]
+mla z0.s, z0.s, z0.s[0]
+mla z17.d, z21.d, z11.d[1]
+mla z0.d, z0.d, z0.d[0]
+mls z17.h, z21.h, z3.h[3]
+mls z0.h, z0.h, z0.h[4]
+mls z0.h, z0.h, z0.h[0]
+mls z17.s, z21.s, z3.s[3]
+mls z0.s, z0.s, z0.s[0]
+mls z17.d, z21.d, z11.d[1]
+mls z0.d, z0.d, z0.d[0]
+mul z17.h, z21.h, z3.h[3]
+mul z0.h, z0.h, z0.h[4]
+mul z0.h, z0.h, z0.h[0]
+mul z17.s, z21.s, z3.s[3]
+mul z0.s, z0.s, z0.s[0]
+mul z17.d, z21.d, z11.d[1]
+mul z0.d, z0.d, z0.d[0]
+mul z17.b, z21.b, z27.b
+mul z0.b, z0.b, z0.b
+mul z0.h, z0.h, z0.h
+mul z0.s, z0.s, z0.s
+mul z0.d, z0.d, z0.d
+smulh z17.b, z21.b, z27.b
+smulh z0.b, z0.b, z0.b
+smulh z0.h, z0.h, z0.h
+smulh z0.s, z0.s, z0.s
+smulh z0.d, z0.d, z0.d
+splice z17.b, p5, { z21.b, z22.b }
+splice z0.b, p0, { z0.b, z1.b }
+splice z0.h, p0, { z0.h, z1.h }
+splice z0.s, p0, { z0.s, z1.s }
+splice z0.d, p0, { z0.d, z1.d }
+splice z0.b, p0, { z31.b, z0.b }
+sqadd z17.b, p5/m, z17.b, z21.b
+sqadd z0.b, p0/m, z0.b, z0.b
+sqadd z0.h, p0/m, z0.h, z0.h
+sqadd z0.s, p0/m, z0.s, z0.s
+sqadd z0.d, p0/m, z0.d, z0.d
+sqsub z17.b, p5/m, z17.b, z21.b
+sqsub z0.b, p0/m, z0.b, z0.b
+sqsub z0.h, p0/m, z0.h, z0.h
+sqsub z0.s, p0/m, z0.s, z0.s
+sqsub z0.d, p0/m, z0.d, z0.d
+stnt1b { z17.s }, p5, [z21.s, x27]
+stnt1b { z0.s }, p0, [z0.s, x0]
+stnt1b { z0.s }, p0, [z0.s]
+stnt1b { z0.s }, p0, [z0.s, xzr]
+stnt1b { z17.d }, p5, [z21.d, x27]
+stnt1b { z0.d }, p0, [z0.d, x0]
+stnt1b { z0.d }, p0, [z0.d]
+stnt1b { z0.d }, p0, [z0.d, xzr]
+stnt1d { z17.d }, p5, [z21.d, x27]
+stnt1d { z0.d }, p0, [z0.d, x0]
+stnt1d { z0.d }, p0, [z0.d]
+stnt1d { z0.d }, p0, [z0.d, xzr]
+stnt1h { z17.s }, p5, [z21.s, x27]
+stnt1h { z0.s }, p0, [z0.s, x0]
+stnt1h { z0.s }, p0, [z0.s]
+stnt1h { z0.s }, p0, [z0.s, xzr]
+stnt1h { z17.d }, p5, [z21.d, x27]
+stnt1h { z0.d }, p0, [z0.d, x0]
+stnt1h { z0.d }, p0, [z0.d]
+stnt1h { z0.d }, p0, [z0.d, xzr]
+stnt1w { z17.s }, p5, [z21.s, x27]
+stnt1w { z0.s }, p0, [z0.s, x0]
+stnt1w { z0.s }, p0, [z0.s]
+stnt1w { z0.s }, p0, [z0.s, xzr]
+stnt1w { z17.d }, p5, [z21.d, x27]
+stnt1w { z0.d }, p0, [z0.d, x0]
+stnt1w { z0.d }, p0, [z0.d]
+stnt1w { z0.d }, p0, [z0.d, xzr]
+tbl z17.b, { z21.b, z22.b }, z27.b
+tbl z0.b, { z0.b, z1.b }, z0.b
+tbl z0.h, { z0.h, z1.h }, z0.h
+tbl z0.s, { z0.s, z1.s }, z0.s
+tbl z0.d, { z0.d, z1.d }, z0.d
+tbl z0.b, { z31.b, z0.b }, z0.b
+umulh z17.b, z21.b, z27.b
+umulh z0.b, z0.b, z0.b
+umulh z0.h, z0.h, z0.h
+umulh z0.s, z0.s, z0.s
+umulh z0.d, z0.d, z0.d
+uqadd z17.b, p5/m, z17.b, z21.b
+uqadd z0.b, p0/m, z0.b, z0.b
+uqadd z0.h, p0/m, z0.h, z0.h
+uqadd z0.s, p0/m, z0.s, z0.s
+uqadd z0.d, p0/m, z0.d, z0.d
+uqsub z17.b, p5/m, z17.b, z21.b
+uqsub z0.b, p0/m, z0.b, z0.b
+uqsub z0.h, p0/m, z0.h, z0.h
+uqsub z0.s, p0/m, z0.s, z0.s
+uqsub z0.d, p0/m, z0.d, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/sve2.d
new file mode 100644
index 0000000..d7c56c0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2.d
@@ -0,0 +1,1301 @@
+#as: -march=armv8-a+sve2+sve2-aes+sve2-sm4+sve2-sha3+bitperm
+#objdump: -dr
+
+[^:]+:     file format elf64-littleaarch64
+
+
+Disassembly of section \.text:
+
+0000000000000000 <\.text>:
+ *[0-9a-f]+:	0420bc20 	movprfx	z0, z1
+ *[0-9a-f]+:	4542d020 	adclb	z0\.d, z1\.d, z2\.d
+ *[0-9a-f]+:	451bd2b1 	adclb	z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+:	4500d000 	adclb	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	4540d000 	adclb	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451bd6b1 	adclt	z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+:	4500d400 	adclt	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	4540d400 	adclt	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	457b62b1 	addhnb	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45606000 	addhnb	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a06000 	addhnb	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e06000 	addhnb	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	457b66b1 	addhnt	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45606400 	addhnt	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a06400 	addhnt	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e06400 	addhnt	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	04d12020 	movprfx	z0\.d, p0/m, z1\.d
+ *[0-9a-f]+:	44d1a020 	addp	z0\.d, p0/m, z0\.d, z1\.d
+ *[0-9a-f]+:	4411b6b1 	addp	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	4411a000 	addp	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	4451a000 	addp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	4491a000 	addp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d1a000 	addp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4522e6b1 	aesd	z17\.b, z17\.b, z21\.b
+ *[0-9a-f]+:	4522e400 	aesd	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4522e2b1 	aese	z17\.b, z17\.b, z21\.b
+ *[0-9a-f]+:	4522e000 	aese	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4520e411 	aesimc	z17\.b, z17\.b
+ *[0-9a-f]+:	4520e400 	aesimc	z0\.b, z0\.b
+ *[0-9a-f]+:	4520e011 	aesmc	z17\.b, z17\.b
+ *[0-9a-f]+:	4520e000 	aesmc	z0\.b, z0\.b
+ *[0-9a-f]+:	04753b71 	bcax	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04603800 	bcax	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	04353f71 	bsl	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04203c00 	bsl	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	04753f71 	bsl1n	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04603c00 	bsl1n	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	04b53f71 	bsl2n	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04a03c00 	bsl2n	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451bb6b1 	bdep	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4500b400 	bdep	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4540b400 	bdep	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	4580b400 	bdep	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0b400 	bdep	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451bb2b1 	bext	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4500b000 	bext	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4540b000 	bext	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	4580b000 	bext	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0b000 	bext	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451bbab1 	bgrp	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4500b800 	bgrp	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4540b800 	bgrp	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	4580b800 	bgrp	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0b800 	bgrp	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	4500dab1 	cadd	z17\.b, z17\.b, z21\.b, #90
+ *[0-9a-f]+:	4500d800 	cadd	z0\.b, z0\.b, z0\.b, #90
+ *[0-9a-f]+:	4540d800 	cadd	z0\.h, z0\.h, z0\.h, #90
+ *[0-9a-f]+:	4580d800 	cadd	z0\.s, z0\.s, z0\.s, #90
+ *[0-9a-f]+:	45c0d800 	cadd	z0\.d, z0\.d, z0\.d, #90
+ *[0-9a-f]+:	4500dc00 	cadd	z0\.b, z0\.b, z0\.b, #270
+ *[0-9a-f]+:	44bb42b1 	cdot	z17\.s, z21\.b, z3\.b\[3\], #0
+ *[0-9a-f]+:	44a04000 	cdot	z0\.s, z0\.b, z0\.b\[0\], #0
+ *[0-9a-f]+:	44a04400 	cdot	z0\.s, z0\.b, z0\.b\[0\], #90
+ *[0-9a-f]+:	44a04800 	cdot	z0\.s, z0\.b, z0\.b\[0\], #180
+ *[0-9a-f]+:	44a04c00 	cdot	z0\.s, z0\.b, z0\.b\[0\], #270
+ *[0-9a-f]+:	44fb42b1 	cdot	z17\.d, z21\.h, z11\.h\[1\], #0
+ *[0-9a-f]+:	44e04000 	cdot	z0\.d, z0\.h, z0\.h\[0\], #0
+ *[0-9a-f]+:	44e04400 	cdot	z0\.d, z0\.h, z0\.h\[0\], #90
+ *[0-9a-f]+:	44e04800 	cdot	z0\.d, z0\.h, z0\.h\[0\], #180
+ *[0-9a-f]+:	44e04c00 	cdot	z0\.d, z0\.h, z0\.h\[0\], #270
+ *[0-9a-f]+:	449b12b1 	cdot	z17\.s, z21\.b, z27\.b, #0
+ *[0-9a-f]+:	44801000 	cdot	z0\.s, z0\.b, z0\.b, #0
+ *[0-9a-f]+:	44c01000 	cdot	z0\.d, z0\.h, z0\.h, #0
+ *[0-9a-f]+:	44801400 	cdot	z0\.s, z0\.b, z0\.b, #90
+ *[0-9a-f]+:	44801800 	cdot	z0\.s, z0\.b, z0\.b, #180
+ *[0-9a-f]+:	44801c00 	cdot	z0\.s, z0\.b, z0\.b, #270
+ *[0-9a-f]+:	44bb62b1 	cmla	z17\.h, z21\.h, z3\.h\[3\], #0
+ *[0-9a-f]+:	44a06000 	cmla	z0\.h, z0\.h, z0\.h\[0\], #0
+ *[0-9a-f]+:	44a06400 	cmla	z0\.h, z0\.h, z0\.h\[0\], #90
+ *[0-9a-f]+:	44a06800 	cmla	z0\.h, z0\.h, z0\.h\[0\], #180
+ *[0-9a-f]+:	44a06c00 	cmla	z0\.h, z0\.h, z0\.h\[0\], #270
+ *[0-9a-f]+:	44fb62b1 	cmla	z17\.s, z21\.s, z11\.s\[1\], #0
+ *[0-9a-f]+:	44e06000 	cmla	z0\.s, z0\.s, z0\.s\[0\], #0
+ *[0-9a-f]+:	44e06400 	cmla	z0\.s, z0\.s, z0\.s\[0\], #90
+ *[0-9a-f]+:	44e06800 	cmla	z0\.s, z0\.s, z0\.s\[0\], #180
+ *[0-9a-f]+:	44e06c00 	cmla	z0\.s, z0\.s, z0\.s\[0\], #270
+ *[0-9a-f]+:	441b22b1 	cmla	z17\.b, z21\.b, z27\.b, #0
+ *[0-9a-f]+:	44002000 	cmla	z0\.b, z0\.b, z0\.b, #0
+ *[0-9a-f]+:	44402000 	cmla	z0\.h, z0\.h, z0\.h, #0
+ *[0-9a-f]+:	44802000 	cmla	z0\.s, z0\.s, z0\.s, #0
+ *[0-9a-f]+:	44c02000 	cmla	z0\.d, z0\.d, z0\.d, #0
+ *[0-9a-f]+:	44002400 	cmla	z0\.b, z0\.b, z0\.b, #90
+ *[0-9a-f]+:	44002800 	cmla	z0\.b, z0\.b, z0\.b, #180
+ *[0-9a-f]+:	44002c00 	cmla	z0\.b, z0\.b, z0\.b, #270
+ *[0-9a-f]+:	04353b71 	eor3	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04203800 	eor3	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451b92b1 	eorbt	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	45009000 	eorbt	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	45409000 	eorbt	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	45809000 	eorbt	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c09000 	eorbt	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451b96b1 	eortb	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	45009400 	eortb	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	45409400 	eortb	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	45809400 	eortb	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c09400 	eortb	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	057b16b1 	ext	z17\.b, {z21\.b, z22\.b}, #221
+ *[0-9a-f]+:	05600000 	ext	z0\.b, {z0\.b, z1\.b}, #0
+ *[0-9a-f]+:	056003e0 	ext	z0\.b, {z31\.b, z0\.b}, #0
+ *[0-9a-f]+:	645096b1 	faddp	z17\.h, p5/m, z17\.h, z21\.h
+ *[0-9a-f]+:	64508000 	faddp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	64908000 	faddp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	64d08000 	faddp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	6489b6b1 	fcvtlt	z17\.s, p5/m, z21\.h
+ *[0-9a-f]+:	6489a000 	fcvtlt	z0\.s, p0/m, z0\.h
+ *[0-9a-f]+:	64cbb6b1 	fcvtlt	z17\.d, p5/m, z21\.s
+ *[0-9a-f]+:	64cba000 	fcvtlt	z0\.d, p0/m, z0\.s
+ *[0-9a-f]+:	6488b6b1 	fcvtnt	z17\.h, p5/m, z21\.s
+ *[0-9a-f]+:	6488a000 	fcvtnt	z0\.h, p0/m, z0\.s
+ *[0-9a-f]+:	64cab6b1 	fcvtnt	z17\.s, p5/m, z21\.d
+ *[0-9a-f]+:	64caa000 	fcvtnt	z0\.s, p0/m, z0\.d
+ *[0-9a-f]+:	650ab6b1 	fcvtx	z17\.s, p5/m, z21\.d
+ *[0-9a-f]+:	650aa000 	fcvtx	z0\.s, p0/m, z0\.d
+ *[0-9a-f]+:	04d02020 	movprfx	z0\.d, p0/z, z1\.d
+ *[0-9a-f]+:	650aa040 	fcvtx	z0\.s, p0/m, z2\.d
+ *[0-9a-f]+:	640ab6b1 	fcvtxnt	z17\.s, p5/m, z21\.d
+ *[0-9a-f]+:	640aa000 	fcvtxnt	z0\.s, p0/m, z0\.d
+ *[0-9a-f]+:	651ab6b1 	flogb	z17\.h, p5/m, z21\.h
+ *[0-9a-f]+:	651aa000 	flogb	z0\.h, p0/m, z0\.h
+ *[0-9a-f]+:	651ca000 	flogb	z0\.s, p0/m, z0\.s
+ *[0-9a-f]+:	651ea000 	flogb	z0\.d, p0/m, z0\.d
+ *[0-9a-f]+:	645496b1 	fmaxnmp	z17\.h, p5/m, z17\.h, z21\.h
+ *[0-9a-f]+:	64548000 	fmaxnmp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	64948000 	fmaxnmp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	64d48000 	fmaxnmp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	645696b1 	fmaxp	z17\.h, p5/m, z17\.h, z21\.h
+ *[0-9a-f]+:	64568000 	fmaxp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	64968000 	fmaxp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	64d68000 	fmaxp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	645596b1 	fminnmp	z17\.h, p5/m, z17\.h, z21\.h
+ *[0-9a-f]+:	64558000 	fminnmp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	64958000 	fminnmp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	64d58000 	fminnmp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	645796b1 	fminp	z17\.h, p5/m, z17\.h, z21\.h
+ *[0-9a-f]+:	64578000 	fminp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	64978000 	fminp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	64d78000 	fminp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	64a542b1 	fmlalb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	64b04800 	fmlalb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	64a04000 	fmlalb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	64bb82b1 	fmlalb	z17\.s, z21\.h, z27\.h
+ *[0-9a-f]+:	64a08000 	fmlalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	64a546b1 	fmlalt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	64b04c00 	fmlalt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	64a04400 	fmlalt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	64bb86b1 	fmlalt	z17\.s, z21\.h, z27\.h
+ *[0-9a-f]+:	64a08400 	fmlalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	64a562b1 	fmlslb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	64b06800 	fmlslb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	64a06000 	fmlslb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	64bba2b1 	fmlslb	z17\.s, z21\.h, z27\.h
+ *[0-9a-f]+:	64a0a000 	fmlslb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	64a566b1 	fmlslt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	64b06c00 	fmlslt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	64a06400 	fmlslt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	64bba6b1 	fmlslt	z17\.s, z21\.h, z27\.h
+ *[0-9a-f]+:	64a0a400 	fmlslt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45bbd6b1 	histcnt	z17\.s, p5/z, z21\.s, z27\.s
+ *[0-9a-f]+:	45a0c000 	histcnt	z0\.s, p0/z, z0\.s, z0\.s
+ *[0-9a-f]+:	45e0c000 	histcnt	z0\.d, p0/z, z0\.d, z0\.d
+ *[0-9a-f]+:	453ba2b1 	histseg	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4520a000 	histseg	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	c41bd6b1 	ldnt1b	{z17\.d}, p5/z, \[z21\.d, x27\]
+ *[0-9a-f]+:	c400c000 	ldnt1b	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c41fc000 	ldnt1b	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c41fc000 	ldnt1b	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	841bb6b1 	ldnt1b	{z17\.s}, p5/z, \[z21\.s, x27\]
+ *[0-9a-f]+:	8400a000 	ldnt1b	{z0\.s}, p0/z, \[z0\.s, x0\]
+ *[0-9a-f]+:	841fa000 	ldnt1b	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	841fa000 	ldnt1b	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	c59bd6b1 	ldnt1d	{z17\.d}, p5/z, \[z21\.d, x27\]
+ *[0-9a-f]+:	c580c000 	ldnt1d	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c59fc000 	ldnt1d	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c59fc000 	ldnt1d	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c49bd6b1 	ldnt1h	{z17\.d}, p5/z, \[z21\.d, x27\]
+ *[0-9a-f]+:	c480c000 	ldnt1h	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c49fc000 	ldnt1h	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c49fc000 	ldnt1h	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	849bb6b1 	ldnt1h	{z17\.s}, p5/z, \[z21\.s, x27\]
+ *[0-9a-f]+:	8480a000 	ldnt1h	{z0\.s}, p0/z, \[z0\.s, x0\]
+ *[0-9a-f]+:	849fa000 	ldnt1h	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	849fa000 	ldnt1h	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	841b96b1 	ldnt1sb	{z17\.s}, p5/z, \[z21\.s, x27\]
+ *[0-9a-f]+:	84008000 	ldnt1sb	{z0\.s}, p0/z, \[z0\.s, x0\]
+ *[0-9a-f]+:	841f8000 	ldnt1sb	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	841f8000 	ldnt1sb	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	c4008000 	ldnt1sb	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c41f8000 	ldnt1sb	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c41f8000 	ldnt1sb	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	849b96b1 	ldnt1sh	{z17\.s}, p5/z, \[z21\.s, x27\]
+ *[0-9a-f]+:	84808000 	ldnt1sh	{z0\.s}, p0/z, \[z0\.s, x0\]
+ *[0-9a-f]+:	849f8000 	ldnt1sh	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	849f8000 	ldnt1sh	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	c4808000 	ldnt1sh	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c49f8000 	ldnt1sh	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c49f8000 	ldnt1sh	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c51b96b1 	ldnt1sw	{z17\.d}, p5/z, \[z21\.d, x27\]
+ *[0-9a-f]+:	c5008000 	ldnt1sw	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c51f8000 	ldnt1sw	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c51f8000 	ldnt1sw	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	851bb6b1 	ldnt1w	{z17\.s}, p5/z, \[z21\.s, x27\]
+ *[0-9a-f]+:	8500a000 	ldnt1w	{z0\.s}, p0/z, \[z0\.s, x0\]
+ *[0-9a-f]+:	851fa000 	ldnt1w	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	851fa000 	ldnt1w	{z0\.s}, p0/z, \[z0\.s, xzr\]
+ *[0-9a-f]+:	c51bd6b1 	ldnt1w	{z17\.d}, p5/z, \[z21\.d, x27\]
+ *[0-9a-f]+:	c500c000 	ldnt1w	{z0\.d}, p0/z, \[z0\.d, x0\]
+ *[0-9a-f]+:	c51fc000 	ldnt1w	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	c51fc000 	ldnt1w	{z0\.d}, p0/z, \[z0\.d, xzr\]
+ *[0-9a-f]+:	45359629 	match	p9\.b, p5/z, z17\.b, z21\.b
+ *[0-9a-f]+:	45358220 	match	p0\.b, p0/z, z17\.b, z21\.b
+ *[0-9a-f]+:	45208000 	match	p0\.b, p0/z, z0\.b, z0\.b
+ *[0-9a-f]+:	45608000 	match	p0\.h, p0/z, z0\.h, z0\.h
+ *[0-9a-f]+:	443b0ab1 	mla	z17\.h, z21\.h, z3\.h\[3\]
+ *[0-9a-f]+:	44600800 	mla	z0\.h, z0\.h, z0\.h\[4\]
+ *[0-9a-f]+:	44200800 	mla	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44bb0ab1 	mla	z17\.s, z21\.s, z3\.s\[3\]
+ *[0-9a-f]+:	44a00800 	mla	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44fb0ab1 	mla	z17\.d, z21\.d, z11\.d\[1\]
+ *[0-9a-f]+:	44e00800 	mla	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	443b0eb1 	mls	z17\.h, z21\.h, z3\.h\[3\]
+ *[0-9a-f]+:	44600c00 	mls	z0\.h, z0\.h, z0\.h\[4\]
+ *[0-9a-f]+:	44200c00 	mls	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44bb0eb1 	mls	z17\.s, z21\.s, z3\.s\[3\]
+ *[0-9a-f]+:	44a00c00 	mls	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44fb0eb1 	mls	z17\.d, z21\.d, z11\.d\[1\]
+ *[0-9a-f]+:	44e00c00 	mls	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	443bfab1 	mul	z17\.h, z21\.h, z3\.h\[3\]
+ *[0-9a-f]+:	4460f800 	mul	z0\.h, z0\.h, z0\.h\[4\]
+ *[0-9a-f]+:	4420f800 	mul	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44bbfab1 	mul	z17\.s, z21\.s, z3\.s\[3\]
+ *[0-9a-f]+:	44a0f800 	mul	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44fbfab1 	mul	z17\.d, z21\.d, z11\.d\[1\]
+ *[0-9a-f]+:	44e0f800 	mul	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	043b62b1 	mul	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04206000 	mul	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	04606000 	mul	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	04a06000 	mul	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	04e06000 	mul	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	453b96b9 	nmatch	p9\.b, p5/z, z21\.b, z27\.b
+ *[0-9a-f]+:	45208010 	nmatch	p0\.b, p0/z, z0\.b, z0\.b
+ *[0-9a-f]+:	45608010 	nmatch	p0\.h, p0/z, z0\.h, z0\.h
+ *[0-9a-f]+:	04f53f71 	nbsl	z17\.d, z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	04e03c00 	nbsl	z0\.d, z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	043b66b1 	pmul	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04206400 	pmul	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	451b6ab1 	pmullb	z17\.q, z21\.d, z27\.d
+ *[0-9a-f]+:	45006800 	pmullb	z0\.q, z0\.d, z0\.d
+ *[0-9a-f]+:	45406800 	pmullb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45c06800 	pmullb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	451b6eb1 	pmullt	z17\.q, z21\.d, z27\.d
+ *[0-9a-f]+:	45006c00 	pmullt	z0\.q, z0\.d, z0\.d
+ *[0-9a-f]+:	45406c00 	pmullt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45c06c00 	pmullt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	457b6ab1 	raddhnb	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45606800 	raddhnb	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a06800 	raddhnb	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e06800 	raddhnb	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	457b6eb1 	raddhnt	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45606c00 	raddhnt	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a06c00 	raddhnt	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e06c00 	raddhnt	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	453bf6b1 	rax1	z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+:	4520f400 	rax1	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	45291ab1 	rshrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f1800 	rshrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45281800 	rshrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f1800 	rshrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45311800 	rshrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45301800 	rshrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f1800 	rshrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45611800 	rshrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45601800 	rshrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	45291eb1 	rshrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f1c00 	rshrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45281c00 	rshrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f1c00 	rshrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45311c00 	rshrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45301c00 	rshrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f1c00 	rshrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45611c00 	rshrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45601c00 	rshrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	457b7ab1 	rsubhnb	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45607800 	rsubhnb	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a07800 	rsubhnb	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e07800 	rsubhnb	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	457b7eb1 	rsubhnt	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45607c00 	rsubhnt	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a07c00 	rsubhnt	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e07c00 	rsubhnt	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	451bfab1 	saba	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4500f800 	saba	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4540f800 	saba	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	4580f800 	saba	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0f800 	saba	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	455bc2b1 	sabalb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	4540c000 	sabalb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	4580c000 	sabalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c0c000 	sabalb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455bc6b1 	sabalt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	4540c400 	sabalt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	4580c400 	sabalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c0c400 	sabalt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b32b1 	sabdlb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45403000 	sabdlb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45803000 	sabdlb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c03000 	sabdlb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b36b1 	sabdlt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45403400 	sabdlt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45803400 	sabdlt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c03400 	sabdlt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	4444b6b1 	sadalp	z17\.h, p5/m, z21\.b
+ *[0-9a-f]+:	4444a000 	sadalp	z0\.h, p0/m, z0\.b
+ *[0-9a-f]+:	4484a000 	sadalp	z0\.s, p0/m, z0\.h
+ *[0-9a-f]+:	44c4a000 	sadalp	z0\.d, p0/m, z0\.s
+ *[0-9a-f]+:	455b02b1 	saddlb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45400000 	saddlb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45800000 	saddlb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c00000 	saddlb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b82b1 	saddlbt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45408000 	saddlbt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45808000 	saddlbt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c08000 	saddlbt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b06b1 	saddlt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45400400 	saddlt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45800400 	saddlt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c00400 	saddlt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b42b1 	saddwb	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45404000 	saddwb	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45804000 	saddwb	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c04000 	saddwb	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	455b46b1 	saddwt	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45404400 	saddwt	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45804400 	saddwt	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c04400 	saddwt	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	459bd2b1 	sbclb	z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+:	4580d000 	sbclb	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0d000 	sbclb	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	459bd6b1 	sbclt	z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+:	4580d400 	sbclt	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0d400 	sbclt	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	441096b1 	shadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44108000 	shadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44508000 	shadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44908000 	shadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d08000 	shadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	452912b1 	shrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f1000 	shrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45281000 	shrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f1000 	shrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45311000 	shrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45301000 	shrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f1000 	shrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45611000 	shrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45601000 	shrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	452916b1 	shrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f1400 	shrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45281400 	shrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f1400 	shrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45311400 	shrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45301400 	shrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f1400 	shrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45611400 	shrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45601400 	shrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	441296b1 	shsub	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44128000 	shsub	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44528000 	shsub	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44928000 	shsub	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d28000 	shsub	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	441696b1 	shsubr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44168000 	shsubr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44568000 	shsubr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44968000 	shsubr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d68000 	shsubr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4509f6b1 	sli	z17\.b, z21\.b, #1
+ *[0-9a-f]+:	4508f400 	sli	z0\.b, z0\.b, #0
+ *[0-9a-f]+:	450ff400 	sli	z0\.b, z0\.b, #7
+ *[0-9a-f]+:	4510f400 	sli	z0\.h, z0\.h, #0
+ *[0-9a-f]+:	451ff400 	sli	z0\.h, z0\.h, #15
+ *[0-9a-f]+:	4540f400 	sli	z0\.s, z0\.s, #0
+ *[0-9a-f]+:	455ff400 	sli	z0\.s, z0\.s, #31
+ *[0-9a-f]+:	4580f400 	sli	z0\.d, z0\.d, #0
+ *[0-9a-f]+:	45dff400 	sli	z0\.d, z0\.d, #63
+ *[0-9a-f]+:	4523e2b1 	sm4e	z17\.s, z17\.s, z21\.s
+ *[0-9a-f]+:	4523e000 	sm4e	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	453bf2b1 	sm4ekey	z17\.s, z21\.s, z27\.s
+ *[0-9a-f]+:	4520f000 	sm4ekey	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	4414b6b1 	smaxp	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	4414a000 	smaxp	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	4454a000 	smaxp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	4494a000 	smaxp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d4a000 	smaxp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4416b6b1 	sminp	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	4416a000 	sminp	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	4456a000 	sminp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	4496a000 	sminp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d6a000 	sminp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	44a582b1 	smlalb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b08800 	smlalb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a08000 	smlalb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e982b1 	smlalb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f08800 	smlalb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e08000 	smlalb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b42b1 	smlalb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44404000 	smlalb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44804000 	smlalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c04000 	smlalb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a586b1 	smlalt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b08c00 	smlalt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a08400 	smlalt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e986b1 	smlalt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f08c00 	smlalt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e08400 	smlalt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b46b1 	smlalt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44404400 	smlalt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44804400 	smlalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c04400 	smlalt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5a2b1 	smlslb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0a800 	smlslb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0a000 	smlslb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9a2b1 	smlslb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0a800 	smlslb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0a000 	smlslb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b52b1 	smlslb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44405000 	smlslb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44805000 	smlslb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c05000 	smlslb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5a6b1 	smlslt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0ac00 	smlslt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0a400 	smlslt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9a6b1 	smlslt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0ac00 	smlslt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0a400 	smlslt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b56b1 	smlslt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44405400 	smlslt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44805400 	smlslt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c05400 	smlslt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	043b6ab1 	smulh	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04206800 	smulh	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	04606800 	smulh	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	04a06800 	smulh	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	04e06800 	smulh	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	44a5c2b1 	smullb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0c800 	smullb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0c000 	smullb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9c2b1 	smullb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0c800 	smullb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0c000 	smullb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b72b1 	smullb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45407000 	smullb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45807000 	smullb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c07000 	smullb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5c6b1 	smullt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0cc00 	smullt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0c400 	smullt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9c6b1 	smullt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0cc00 	smullt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0c400 	smullt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b76b1 	smullt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45407400 	smullt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45807400 	smullt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c07400 	smullt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	052d96b1 	splice	z17\.b, p5, {z21\.b, z22\.b}
+ *[0-9a-f]+:	052d8000 	splice	z0\.b, p0, {z0\.b, z1\.b}
+ *[0-9a-f]+:	056d8000 	splice	z0\.h, p0, {z0\.h, z1\.h}
+ *[0-9a-f]+:	05ad8000 	splice	z0\.s, p0, {z0\.s, z1\.s}
+ *[0-9a-f]+:	05ed8000 	splice	z0\.d, p0, {z0\.d, z1\.d}
+ *[0-9a-f]+:	052d83e0 	splice	z0\.b, p0, {z31\.b, z0\.b}
+ *[0-9a-f]+:	4408b6b1 	sqabs	z17\.b, p5/m, z21\.b
+ *[0-9a-f]+:	4408a000 	sqabs	z0\.b, p0/m, z0\.b
+ *[0-9a-f]+:	4448a000 	sqabs	z0\.h, p0/m, z0\.h
+ *[0-9a-f]+:	4488a000 	sqabs	z0\.s, p0/m, z0\.s
+ *[0-9a-f]+:	44c8a000 	sqabs	z0\.d, p0/m, z0\.d
+ *[0-9a-f]+:	441896b1 	sqadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44188000 	sqadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44588000 	sqadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44988000 	sqadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d88000 	sqadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4501dab1 	sqcadd	z17\.b, z17\.b, z21\.b, #90
+ *[0-9a-f]+:	4501dc00 	sqcadd	z0\.b, z0\.b, z0\.b, #270
+ *[0-9a-f]+:	4501d800 	sqcadd	z0\.b, z0\.b, z0\.b, #90
+ *[0-9a-f]+:	4541d800 	sqcadd	z0\.h, z0\.h, z0\.h, #90
+ *[0-9a-f]+:	4581d800 	sqcadd	z0\.s, z0\.s, z0\.s, #90
+ *[0-9a-f]+:	45c1d800 	sqcadd	z0\.d, z0\.d, z0\.d, #90
+ *[0-9a-f]+:	44a522b1 	sqdmlalb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b02800 	sqdmlalb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a02000 	sqdmlalb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e922b1 	sqdmlalb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f02800 	sqdmlalb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e02000 	sqdmlalb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b62b1 	sqdmlalb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44406000 	sqdmlalb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44806000 	sqdmlalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c06000 	sqdmlalb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	445b0ab1 	sqdmlalbt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44400800 	sqdmlalbt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44800800 	sqdmlalbt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c00800 	sqdmlalbt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a526b1 	sqdmlalt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b02c00 	sqdmlalt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a02400 	sqdmlalt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e926b1 	sqdmlalt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f02c00 	sqdmlalt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e02400 	sqdmlalt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b66b1 	sqdmlalt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44406400 	sqdmlalt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44806400 	sqdmlalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c06400 	sqdmlalt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a532b1 	sqdmlslb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b03800 	sqdmlslb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a03000 	sqdmlslb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e932b1 	sqdmlslb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f03800 	sqdmlslb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e03000 	sqdmlslb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b6ab1 	sqdmlslb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44406800 	sqdmlslb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44806800 	sqdmlslb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c06800 	sqdmlslb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	445b0eb1 	sqdmlslbt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44400c00 	sqdmlslbt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44800c00 	sqdmlslbt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c00c00 	sqdmlslbt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a536b1 	sqdmlslt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b03c00 	sqdmlslt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a03400 	sqdmlslt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e936b1 	sqdmlslt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f03c00 	sqdmlslt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e03400 	sqdmlslt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b6eb1 	sqdmlslt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44406c00 	sqdmlslt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44806c00 	sqdmlslt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c06c00 	sqdmlslt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	4425f2b1 	sqdmulh	z17\.h, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	4468f000 	sqdmulh	z0\.h, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	4420f000 	sqdmulh	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44a5f2b1 	sqdmulh	z17\.s, z21\.s, z5\.s\[0\]
+ *[0-9a-f]+:	44b8f000 	sqdmulh	z0\.s, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44a0f000 	sqdmulh	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44e9f2b1 	sqdmulh	z17\.d, z21\.d, z9\.d\[0\]
+ *[0-9a-f]+:	44f0f000 	sqdmulh	z0\.d, z0\.d, z0\.d\[1\]
+ *[0-9a-f]+:	44e0f000 	sqdmulh	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	043b72b1 	sqdmulh	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04207000 	sqdmulh	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	04607000 	sqdmulh	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	04a07000 	sqdmulh	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	04e07000 	sqdmulh	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	44a5e2b1 	sqdmullb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0e800 	sqdmullb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0e000 	sqdmullb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9e2b1 	sqdmullb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0e800 	sqdmullb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0e000 	sqdmullb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b62b1 	sqdmullb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45406000 	sqdmullb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45806000 	sqdmullb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c06000 	sqdmullb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5e6b1 	sqdmullt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0ec00 	sqdmullt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0e400 	sqdmullt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9e6b1 	sqdmullt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0ec00 	sqdmullt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0e400 	sqdmullt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b66b1 	sqdmullt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45406400 	sqdmullt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45806400 	sqdmullt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c06400 	sqdmullt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	4409b6b1 	sqneg	z17\.b, p5/m, z21\.b
+ *[0-9a-f]+:	4409a000 	sqneg	z0\.b, p0/m, z0\.b
+ *[0-9a-f]+:	4449a000 	sqneg	z0\.h, p0/m, z0\.h
+ *[0-9a-f]+:	4489a000 	sqneg	z0\.s, p0/m, z0\.s
+ *[0-9a-f]+:	44c9a000 	sqneg	z0\.d, p0/m, z0\.d
+ *[0-9a-f]+:	44a572b1 	sqrdcmlah	z17\.h, z21\.h, z5\.h\[0\], #0
+ *[0-9a-f]+:	44b87000 	sqrdcmlah	z0\.h, z0\.h, z0\.h\[3\], #0
+ *[0-9a-f]+:	44a07400 	sqrdcmlah	z0\.h, z0\.h, z0\.h\[0\], #90
+ *[0-9a-f]+:	44a07800 	sqrdcmlah	z0\.h, z0\.h, z0\.h\[0\], #180
+ *[0-9a-f]+:	44a07c00 	sqrdcmlah	z0\.h, z0\.h, z0\.h\[0\], #270
+ *[0-9a-f]+:	44e972b1 	sqrdcmlah	z17\.s, z21\.s, z9\.s\[0\], #0
+ *[0-9a-f]+:	44f07000 	sqrdcmlah	z0\.s, z0\.s, z0\.s\[1\], #0
+ *[0-9a-f]+:	44e07400 	sqrdcmlah	z0\.s, z0\.s, z0\.s\[0\], #90
+ *[0-9a-f]+:	44e07800 	sqrdcmlah	z0\.s, z0\.s, z0\.s\[0\], #180
+ *[0-9a-f]+:	44e07c00 	sqrdcmlah	z0\.s, z0\.s, z0\.s\[0\], #270
+ *[0-9a-f]+:	441b32b1 	sqrdcmlah	z17\.b, z21\.b, z27\.b, #0
+ *[0-9a-f]+:	44003000 	sqrdcmlah	z0\.b, z0\.b, z0\.b, #0
+ *[0-9a-f]+:	44003400 	sqrdcmlah	z0\.b, z0\.b, z0\.b, #90
+ *[0-9a-f]+:	44003800 	sqrdcmlah	z0\.b, z0\.b, z0\.b, #180
+ *[0-9a-f]+:	44003c00 	sqrdcmlah	z0\.b, z0\.b, z0\.b, #270
+ *[0-9a-f]+:	44403000 	sqrdcmlah	z0\.h, z0\.h, z0\.h, #0
+ *[0-9a-f]+:	44803000 	sqrdcmlah	z0\.s, z0\.s, z0\.s, #0
+ *[0-9a-f]+:	44c03000 	sqrdcmlah	z0\.d, z0\.d, z0\.d, #0
+ *[0-9a-f]+:	442512b1 	sqrdmlah	z17\.h, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44681000 	sqrdmlah	z0\.h, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44201000 	sqrdmlah	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44a512b1 	sqrdmlah	z17\.s, z21\.s, z5\.s\[0\]
+ *[0-9a-f]+:	44b81000 	sqrdmlah	z0\.s, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44a01000 	sqrdmlah	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44e912b1 	sqrdmlah	z17\.d, z21\.d, z9\.d\[0\]
+ *[0-9a-f]+:	44f01000 	sqrdmlah	z0\.d, z0\.d, z0\.d\[1\]
+ *[0-9a-f]+:	44e01000 	sqrdmlah	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	441b72b1 	sqrdmlah	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	44007000 	sqrdmlah	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	44407000 	sqrdmlah	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	44807000 	sqrdmlah	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	44c07000 	sqrdmlah	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	442516b1 	sqrdmlsh	z17\.h, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44681400 	sqrdmlsh	z0\.h, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44201400 	sqrdmlsh	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44a516b1 	sqrdmlsh	z17\.s, z21\.s, z5\.s\[0\]
+ *[0-9a-f]+:	44b81400 	sqrdmlsh	z0\.s, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44a01400 	sqrdmlsh	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44e916b1 	sqrdmlsh	z17\.d, z21\.d, z9\.d\[0\]
+ *[0-9a-f]+:	44f01400 	sqrdmlsh	z0\.d, z0\.d, z0\.d\[1\]
+ *[0-9a-f]+:	44e01400 	sqrdmlsh	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	441b76b1 	sqrdmlsh	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	44007400 	sqrdmlsh	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	44407400 	sqrdmlsh	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	44807400 	sqrdmlsh	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	44c07400 	sqrdmlsh	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	4425f6b1 	sqrdmulh	z17\.h, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	4468f400 	sqrdmulh	z0\.h, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	4420f400 	sqrdmulh	z0\.h, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44a5f6b1 	sqrdmulh	z17\.s, z21\.s, z5\.s\[0\]
+ *[0-9a-f]+:	44b8f400 	sqrdmulh	z0\.s, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44a0f400 	sqrdmulh	z0\.s, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	44e9f6b1 	sqrdmulh	z17\.d, z21\.d, z9\.d\[0\]
+ *[0-9a-f]+:	44f0f400 	sqrdmulh	z0\.d, z0\.d, z0\.d\[1\]
+ *[0-9a-f]+:	44e0f400 	sqrdmulh	z0\.d, z0\.d, z0\.d\[0\]
+ *[0-9a-f]+:	043b76b1 	sqrdmulh	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04207400 	sqrdmulh	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	04607400 	sqrdmulh	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	04a07400 	sqrdmulh	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	04e07400 	sqrdmulh	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	440a96b1 	sqrshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440a8000 	sqrshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444a8000 	sqrshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448a8000 	sqrshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44ca8000 	sqrshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440e96b1 	sqrshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440e8000 	sqrshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444e8000 	sqrshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448e8000 	sqrshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44ce8000 	sqrshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	45292ab1 	sqrshrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f2800 	sqrshrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45282800 	sqrshrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f2800 	sqrshrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45312800 	sqrshrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45302800 	sqrshrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f2800 	sqrshrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45612800 	sqrshrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45602800 	sqrshrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	45292eb1 	sqrshrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f2c00 	sqrshrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45282c00 	sqrshrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f2c00 	sqrshrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45312c00 	sqrshrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45302c00 	sqrshrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f2c00 	sqrshrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45612c00 	sqrshrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45602c00 	sqrshrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	45290ab1 	sqrshrunb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f0800 	sqrshrunb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45280800 	sqrshrunb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f0800 	sqrshrunb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45310800 	sqrshrunb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45300800 	sqrshrunb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f0800 	sqrshrunb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45610800 	sqrshrunb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45600800 	sqrshrunb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	45290eb1 	sqrshrunt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f0c00 	sqrshrunt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45280c00 	sqrshrunt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f0c00 	sqrshrunt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45310c00 	sqrshrunt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45300c00 	sqrshrunt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f0c00 	sqrshrunt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45610c00 	sqrshrunt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45600c00 	sqrshrunt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	04069531 	sqshl	z17\.b, p5/m, z17\.b, #1
+ *[0-9a-f]+:	04068100 	sqshl	z0\.b, p0/m, z0\.b, #0
+ *[0-9a-f]+:	040681e0 	sqshl	z0\.b, p0/m, z0\.b, #7
+ *[0-9a-f]+:	04068200 	sqshl	z0\.h, p0/m, z0\.h, #0
+ *[0-9a-f]+:	040683e0 	sqshl	z0\.h, p0/m, z0\.h, #15
+ *[0-9a-f]+:	04468000 	sqshl	z0\.s, p0/m, z0\.s, #0
+ *[0-9a-f]+:	044683e0 	sqshl	z0\.s, p0/m, z0\.s, #31
+ *[0-9a-f]+:	04868000 	sqshl	z0\.d, p0/m, z0\.d, #0
+ *[0-9a-f]+:	04c683e0 	sqshl	z0\.d, p0/m, z0\.d, #63
+ *[0-9a-f]+:	440896b1 	sqshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44088000 	sqshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44488000 	sqshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44888000 	sqshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c88000 	sqshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440c96b1 	sqshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440c8000 	sqshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444c8000 	sqshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448c8000 	sqshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44cc8000 	sqshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	040f9531 	sqshlu	z17\.b, p5/m, z17\.b, #1
+ *[0-9a-f]+:	040f8100 	sqshlu	z0\.b, p0/m, z0\.b, #0
+ *[0-9a-f]+:	040f81e0 	sqshlu	z0\.b, p0/m, z0\.b, #7
+ *[0-9a-f]+:	040f8200 	sqshlu	z0\.h, p0/m, z0\.h, #0
+ *[0-9a-f]+:	040f83e0 	sqshlu	z0\.h, p0/m, z0\.h, #15
+ *[0-9a-f]+:	044f8000 	sqshlu	z0\.s, p0/m, z0\.s, #0
+ *[0-9a-f]+:	044f83e0 	sqshlu	z0\.s, p0/m, z0\.s, #31
+ *[0-9a-f]+:	048f8000 	sqshlu	z0\.d, p0/m, z0\.d, #0
+ *[0-9a-f]+:	04cf83e0 	sqshlu	z0\.d, p0/m, z0\.d, #63
+ *[0-9a-f]+:	452922b1 	sqshrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f2000 	sqshrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45282000 	sqshrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f2000 	sqshrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45312000 	sqshrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45302000 	sqshrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f2000 	sqshrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45612000 	sqshrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45602000 	sqshrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	452926b1 	sqshrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f2400 	sqshrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45282400 	sqshrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f2400 	sqshrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45312400 	sqshrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45302400 	sqshrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f2400 	sqshrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45612400 	sqshrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45602400 	sqshrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	452902b1 	sqshrunb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f0000 	sqshrunb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45280000 	sqshrunb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f0000 	sqshrunb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45310000 	sqshrunb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45300000 	sqshrunb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f0000 	sqshrunb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45610000 	sqshrunb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45600000 	sqshrunb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	452906b1 	sqshrunt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f0400 	sqshrunt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45280400 	sqshrunt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f0400 	sqshrunt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45310400 	sqshrunt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45300400 	sqshrunt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f0400 	sqshrunt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45610400 	sqshrunt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45600400 	sqshrunt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	441a96b1 	sqsub	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441a8000 	sqsub	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445a8000 	sqsub	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449a8000 	sqsub	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44da8000 	sqsub	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	441e96b1 	sqsubr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441e8000 	sqsubr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445e8000 	sqsubr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449e8000 	sqsubr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44de8000 	sqsubr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	452842b1 	sqxtnb	z17\.b, z21\.h
+ *[0-9a-f]+:	45284000 	sqxtnb	z0\.b, z0\.h
+ *[0-9a-f]+:	45304000 	sqxtnb	z0\.h, z0\.s
+ *[0-9a-f]+:	45604000 	sqxtnb	z0\.s, z0\.d
+ *[0-9a-f]+:	452846b1 	sqxtnt	z17\.b, z21\.h
+ *[0-9a-f]+:	45284400 	sqxtnt	z0\.b, z0\.h
+ *[0-9a-f]+:	45304400 	sqxtnt	z0\.h, z0\.s
+ *[0-9a-f]+:	45604400 	sqxtnt	z0\.s, z0\.d
+ *[0-9a-f]+:	452852b1 	sqxtunb	z17\.b, z21\.h
+ *[0-9a-f]+:	45285000 	sqxtunb	z0\.b, z0\.h
+ *[0-9a-f]+:	45305000 	sqxtunb	z0\.h, z0\.s
+ *[0-9a-f]+:	45605000 	sqxtunb	z0\.s, z0\.d
+ *[0-9a-f]+:	452856b1 	sqxtunt	z17\.b, z21\.h
+ *[0-9a-f]+:	45285400 	sqxtunt	z0\.b, z0\.h
+ *[0-9a-f]+:	45305400 	sqxtunt	z0\.h, z0\.s
+ *[0-9a-f]+:	45605400 	sqxtunt	z0\.s, z0\.d
+ *[0-9a-f]+:	441496b1 	srhadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44148000 	srhadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44548000 	srhadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44948000 	srhadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d48000 	srhadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4509f2b1 	sri	z17\.b, z21\.b, #7
+ *[0-9a-f]+:	4508f000 	sri	z0\.b, z0\.b, #8
+ *[0-9a-f]+:	450ff000 	sri	z0\.b, z0\.b, #1
+ *[0-9a-f]+:	4510f000 	sri	z0\.h, z0\.h, #16
+ *[0-9a-f]+:	451ff000 	sri	z0\.h, z0\.h, #1
+ *[0-9a-f]+:	4540f000 	sri	z0\.s, z0\.s, #32
+ *[0-9a-f]+:	455ff000 	sri	z0\.s, z0\.s, #1
+ *[0-9a-f]+:	4580f000 	sri	z0\.d, z0\.d, #64
+ *[0-9a-f]+:	45dff000 	sri	z0\.d, z0\.d, #1
+ *[0-9a-f]+:	440296b1 	srshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44028000 	srshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44428000 	srshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44828000 	srshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c28000 	srshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440696b1 	srshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44068000 	srshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44468000 	srshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44868000 	srshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c68000 	srshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	040c9531 	srshr	z17\.b, p5/m, z17\.b, #7
+ *[0-9a-f]+:	040c8100 	srshr	z0\.b, p0/m, z0\.b, #8
+ *[0-9a-f]+:	040c81e0 	srshr	z0\.b, p0/m, z0\.b, #1
+ *[0-9a-f]+:	040c8200 	srshr	z0\.h, p0/m, z0\.h, #16
+ *[0-9a-f]+:	040c83e0 	srshr	z0\.h, p0/m, z0\.h, #1
+ *[0-9a-f]+:	044c8000 	srshr	z0\.s, p0/m, z0\.s, #32
+ *[0-9a-f]+:	044c83e0 	srshr	z0\.s, p0/m, z0\.s, #1
+ *[0-9a-f]+:	048c8000 	srshr	z0\.d, p0/m, z0\.d, #64
+ *[0-9a-f]+:	04cc83e0 	srshr	z0\.d, p0/m, z0\.d, #1
+ *[0-9a-f]+:	4509eab1 	srsra	z17\.b, z21\.b, #7
+ *[0-9a-f]+:	4508e800 	srsra	z0\.b, z0\.b, #8
+ *[0-9a-f]+:	450fe800 	srsra	z0\.b, z0\.b, #1
+ *[0-9a-f]+:	4510e800 	srsra	z0\.h, z0\.h, #16
+ *[0-9a-f]+:	451fe800 	srsra	z0\.h, z0\.h, #1
+ *[0-9a-f]+:	4540e800 	srsra	z0\.s, z0\.s, #32
+ *[0-9a-f]+:	455fe800 	srsra	z0\.s, z0\.s, #1
+ *[0-9a-f]+:	4580e800 	srsra	z0\.d, z0\.d, #64
+ *[0-9a-f]+:	45dfe800 	srsra	z0\.d, z0\.d, #1
+ *[0-9a-f]+:	4509a2b1 	sshllb	z17\.h, z21\.b, #1
+ *[0-9a-f]+:	4508a000 	sshllb	z0\.h, z0\.b, #0
+ *[0-9a-f]+:	450fa000 	sshllb	z0\.h, z0\.b, #7
+ *[0-9a-f]+:	4510a000 	sshllb	z0\.s, z0\.h, #0
+ *[0-9a-f]+:	451fa000 	sshllb	z0\.s, z0\.h, #15
+ *[0-9a-f]+:	4540a000 	sshllb	z0\.d, z0\.s, #0
+ *[0-9a-f]+:	455fa000 	sshllb	z0\.d, z0\.s, #31
+ *[0-9a-f]+:	4509a6b1 	sshllt	z17\.h, z21\.b, #1
+ *[0-9a-f]+:	4508a400 	sshllt	z0\.h, z0\.b, #0
+ *[0-9a-f]+:	450fa400 	sshllt	z0\.h, z0\.b, #7
+ *[0-9a-f]+:	4510a400 	sshllt	z0\.s, z0\.h, #0
+ *[0-9a-f]+:	451fa400 	sshllt	z0\.s, z0\.h, #15
+ *[0-9a-f]+:	4540a400 	sshllt	z0\.d, z0\.s, #0
+ *[0-9a-f]+:	455fa400 	sshllt	z0\.d, z0\.s, #31
+ *[0-9a-f]+:	4509e2b1 	ssra	z17\.b, z21\.b, #7
+ *[0-9a-f]+:	4508e000 	ssra	z0\.b, z0\.b, #8
+ *[0-9a-f]+:	450fe000 	ssra	z0\.b, z0\.b, #1
+ *[0-9a-f]+:	4510e000 	ssra	z0\.h, z0\.h, #16
+ *[0-9a-f]+:	451fe000 	ssra	z0\.h, z0\.h, #1
+ *[0-9a-f]+:	4540e000 	ssra	z0\.s, z0\.s, #32
+ *[0-9a-f]+:	455fe000 	ssra	z0\.s, z0\.s, #1
+ *[0-9a-f]+:	4580e000 	ssra	z0\.d, z0\.d, #64
+ *[0-9a-f]+:	45dfe000 	ssra	z0\.d, z0\.d, #1
+ *[0-9a-f]+:	455b12b1 	ssublb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45401000 	ssublb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45801000 	ssublb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c01000 	ssublb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b8ab1 	ssublbt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45408800 	ssublbt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45808800 	ssublbt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c08800 	ssublbt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b16b1 	ssublt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45401400 	ssublt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45801400 	ssublt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c01400 	ssublt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b8eb1 	ssubltb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45408c00 	ssubltb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45808c00 	ssubltb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c08c00 	ssubltb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b52b1 	ssubwb	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45405000 	ssubwb	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45805000 	ssubwb	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c05000 	ssubwb	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	455b56b1 	ssubwt	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45405400 	ssubwt	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45805400 	ssubwt	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c05400 	ssubwt	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	e45b36b1 	stnt1b	{z17\.s}, p5, \[z21\.s, x27\]
+ *[0-9a-f]+:	e4402000 	stnt1b	{z0\.s}, p0, \[z0\.s, x0\]
+ *[0-9a-f]+:	e45f2000 	stnt1b	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e45f2000 	stnt1b	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e41b36b1 	stnt1b	{z17\.d}, p5, \[z21\.d, x27\]
+ *[0-9a-f]+:	e4002000 	stnt1b	{z0\.d}, p0, \[z0\.d, x0\]
+ *[0-9a-f]+:	e41f2000 	stnt1b	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e41f2000 	stnt1b	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e59b36b1 	stnt1d	{z17\.d}, p5, \[z21\.d, x27\]
+ *[0-9a-f]+:	e5802000 	stnt1d	{z0\.d}, p0, \[z0\.d, x0\]
+ *[0-9a-f]+:	e59f2000 	stnt1d	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e59f2000 	stnt1d	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e4db36b1 	stnt1h	{z17\.s}, p5, \[z21\.s, x27\]
+ *[0-9a-f]+:	e4c02000 	stnt1h	{z0\.s}, p0, \[z0\.s, x0\]
+ *[0-9a-f]+:	e4df2000 	stnt1h	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e4df2000 	stnt1h	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e49b36b1 	stnt1h	{z17\.d}, p5, \[z21\.d, x27\]
+ *[0-9a-f]+:	e4802000 	stnt1h	{z0\.d}, p0, \[z0\.d, x0\]
+ *[0-9a-f]+:	e49f2000 	stnt1h	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e49f2000 	stnt1h	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e55b36b1 	stnt1w	{z17\.s}, p5, \[z21\.s, x27\]
+ *[0-9a-f]+:	e5402000 	stnt1w	{z0\.s}, p0, \[z0\.s, x0\]
+ *[0-9a-f]+:	e55f2000 	stnt1w	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e55f2000 	stnt1w	{z0\.s}, p0, \[z0\.s, xzr\]
+ *[0-9a-f]+:	e51b36b1 	stnt1w	{z17\.d}, p5, \[z21\.d, x27\]
+ *[0-9a-f]+:	e5002000 	stnt1w	{z0\.d}, p0, \[z0\.d, x0\]
+ *[0-9a-f]+:	e51f2000 	stnt1w	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	e51f2000 	stnt1w	{z0\.d}, p0, \[z0\.d, xzr\]
+ *[0-9a-f]+:	457b72b1 	subhnb	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45607000 	subhnb	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a07000 	subhnb	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e07000 	subhnb	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	457b76b1 	subhnt	z17\.b, z21\.h, z27\.h
+ *[0-9a-f]+:	45607400 	subhnt	z0\.b, z0\.h, z0\.h
+ *[0-9a-f]+:	45a07400 	subhnt	z0\.h, z0\.s, z0\.s
+ *[0-9a-f]+:	45e07400 	subhnt	z0\.s, z0\.d, z0\.d
+ *[0-9a-f]+:	441c96b1 	suqadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441c8000 	suqadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445c8000 	suqadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449c8000 	suqadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44dc8000 	suqadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	053b2ab1 	tbl	z17\.b, {z21\.b, z22\.b}, z27\.b
+ *[0-9a-f]+:	05202800 	tbl	z0\.b, {z0\.b, z1\.b}, z0\.b
+ *[0-9a-f]+:	05602800 	tbl	z0\.h, {z0\.h, z1\.h}, z0\.h
+ *[0-9a-f]+:	05a02800 	tbl	z0\.s, {z0\.s, z1\.s}, z0\.s
+ *[0-9a-f]+:	05e02800 	tbl	z0\.d, {z0\.d, z1\.d}, z0\.d
+ *[0-9a-f]+:	05202be0 	tbl	z0\.b, {z31\.b, z0\.b}, z0\.b
+ *[0-9a-f]+:	053b2eb1 	tbx	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	05202c00 	tbx	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	05602c00 	tbx	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	05a02c00 	tbx	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	05e02c00 	tbx	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	451bfeb1 	uaba	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	4500fc00 	uaba	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	4540fc00 	uaba	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	4580fc00 	uaba	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	45c0fc00 	uaba	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	455bcab1 	uabalb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	4540c800 	uabalb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	4580c800 	uabalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c0c800 	uabalb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455bceb1 	uabalt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	4540cc00 	uabalt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	4580cc00 	uabalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c0cc00 	uabalt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b3ab1 	uabdlb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45403800 	uabdlb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45803800 	uabdlb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c03800 	uabdlb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b3eb1 	uabdlt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45403c00 	uabdlt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45803c00 	uabdlt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c03c00 	uabdlt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	4445b6b1 	uadalp	z17\.h, p5/m, z21\.b
+ *[0-9a-f]+:	4445a000 	uadalp	z0\.h, p0/m, z0\.b
+ *[0-9a-f]+:	4485a000 	uadalp	z0\.s, p0/m, z0\.h
+ *[0-9a-f]+:	44c5a000 	uadalp	z0\.d, p0/m, z0\.s
+ *[0-9a-f]+:	455b0ab1 	uaddlb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45400800 	uaddlb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45800800 	uaddlb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c00800 	uaddlb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b0eb1 	uaddlt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45400c00 	uaddlt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45800c00 	uaddlt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c00c00 	uaddlt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b4ab1 	uaddwb	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45404800 	uaddwb	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45804800 	uaddwb	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c04800 	uaddwb	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	455b4eb1 	uaddwt	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45404c00 	uaddwt	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45804c00 	uaddwt	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c04c00 	uaddwt	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	441196b1 	uhadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44118000 	uhadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44518000 	uhadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44918000 	uhadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d18000 	uhadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	441396b1 	uhsub	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44138000 	uhsub	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44538000 	uhsub	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44938000 	uhsub	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d38000 	uhsub	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	441796b1 	uhsubr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44178000 	uhsubr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44578000 	uhsubr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44978000 	uhsubr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d78000 	uhsubr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4415b6b1 	umaxp	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	4415a000 	umaxp	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	4455a000 	umaxp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	4495a000 	umaxp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d5a000 	umaxp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4417b6b1 	uminp	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	4417a000 	uminp	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	4457a000 	uminp	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	4497a000 	uminp	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d7a000 	uminp	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	44a592b1 	umlalb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b09800 	umlalb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a09000 	umlalb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e992b1 	umlalb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f09800 	umlalb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e09000 	umlalb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b4ab1 	umlalb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44404800 	umlalb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44804800 	umlalb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c04800 	umlalb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a596b1 	umlalt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b09c00 	umlalt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a09400 	umlalt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e996b1 	umlalt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f09c00 	umlalt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e09400 	umlalt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b4eb1 	umlalt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44404c00 	umlalt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44804c00 	umlalt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c04c00 	umlalt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5b2b1 	umlslb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0b800 	umlslb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0b000 	umlslb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9b2b1 	umlslb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0b800 	umlslb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0b000 	umlslb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b5ab1 	umlslb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44405800 	umlslb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44805800 	umlslb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c05800 	umlslb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5b6b1 	umlslt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0bc00 	umlslt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0b400 	umlslt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9b6b1 	umlslt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0bc00 	umlslt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0b400 	umlslt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	445b5eb1 	umlslt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	44405c00 	umlslt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	44805c00 	umlslt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	44c05c00 	umlslt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	043b6eb1 	umulh	z17\.b, z21\.b, z27\.b
+ *[0-9a-f]+:	04206c00 	umulh	z0\.b, z0\.b, z0\.b
+ *[0-9a-f]+:	04606c00 	umulh	z0\.h, z0\.h, z0\.h
+ *[0-9a-f]+:	04a06c00 	umulh	z0\.s, z0\.s, z0\.s
+ *[0-9a-f]+:	04e06c00 	umulh	z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+:	44a5d2b1 	umullb	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0d800 	umullb	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0d000 	umullb	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9d2b1 	umullb	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0d800 	umullb	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0d000 	umullb	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b7ab1 	umullb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45407800 	umullb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45807800 	umullb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c07800 	umullb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	44a5d6b1 	umullt	z17\.s, z21\.h, z5\.h\[0\]
+ *[0-9a-f]+:	44b0dc00 	umullt	z0\.s, z0\.h, z0\.h\[5\]
+ *[0-9a-f]+:	44a0d400 	umullt	z0\.s, z0\.h, z0\.h\[0\]
+ *[0-9a-f]+:	44e9d6b1 	umullt	z17\.d, z21\.s, z9\.s\[0\]
+ *[0-9a-f]+:	44f0dc00 	umullt	z0\.d, z0\.s, z0\.s\[3\]
+ *[0-9a-f]+:	44e0d400 	umullt	z0\.d, z0\.s, z0\.s\[0\]
+ *[0-9a-f]+:	455b7eb1 	umullt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45407c00 	umullt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45807c00 	umullt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c07c00 	umullt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	441996b1 	uqadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44198000 	uqadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44598000 	uqadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44998000 	uqadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d98000 	uqadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440b96b1 	uqrshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440b8000 	uqrshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444b8000 	uqrshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448b8000 	uqrshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44cb8000 	uqrshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440f96b1 	uqrshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440f8000 	uqrshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444f8000 	uqrshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448f8000 	uqrshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44cf8000 	uqrshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	45293ab1 	uqrshrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f3800 	uqrshrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45283800 	uqrshrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f3800 	uqrshrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45313800 	uqrshrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45303800 	uqrshrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f3800 	uqrshrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45613800 	uqrshrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45603800 	uqrshrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	45293eb1 	uqrshrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f3c00 	uqrshrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45283c00 	uqrshrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f3c00 	uqrshrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45313c00 	uqrshrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45303c00 	uqrshrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f3c00 	uqrshrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45613c00 	uqrshrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45603c00 	uqrshrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	04079531 	uqshl	z17\.b, p5/m, z17\.b, #1
+ *[0-9a-f]+:	04078100 	uqshl	z0\.b, p0/m, z0\.b, #0
+ *[0-9a-f]+:	040781e0 	uqshl	z0\.b, p0/m, z0\.b, #7
+ *[0-9a-f]+:	04078200 	uqshl	z0\.h, p0/m, z0\.h, #0
+ *[0-9a-f]+:	040783e0 	uqshl	z0\.h, p0/m, z0\.h, #15
+ *[0-9a-f]+:	04478000 	uqshl	z0\.s, p0/m, z0\.s, #0
+ *[0-9a-f]+:	044783e0 	uqshl	z0\.s, p0/m, z0\.s, #31
+ *[0-9a-f]+:	04878000 	uqshl	z0\.d, p0/m, z0\.d, #0
+ *[0-9a-f]+:	04c783e0 	uqshl	z0\.d, p0/m, z0\.d, #63
+ *[0-9a-f]+:	440996b1 	uqshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44098000 	uqshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44498000 	uqshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44898000 	uqshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c98000 	uqshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440d96b1 	uqshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	440d8000 	uqshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	444d8000 	uqshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	448d8000 	uqshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44cd8000 	uqshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	452932b1 	uqshrnb	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f3000 	uqshrnb	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45283000 	uqshrnb	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f3000 	uqshrnb	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45313000 	uqshrnb	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45303000 	uqshrnb	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f3000 	uqshrnb	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45613000 	uqshrnb	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45603000 	uqshrnb	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	452936b1 	uqshrnt	z17\.b, z21\.h, #7
+ *[0-9a-f]+:	452f3400 	uqshrnt	z0\.b, z0\.h, #1
+ *[0-9a-f]+:	45283400 	uqshrnt	z0\.b, z0\.h, #8
+ *[0-9a-f]+:	453f3400 	uqshrnt	z0\.h, z0\.s, #1
+ *[0-9a-f]+:	45313400 	uqshrnt	z0\.h, z0\.s, #15
+ *[0-9a-f]+:	45303400 	uqshrnt	z0\.h, z0\.s, #16
+ *[0-9a-f]+:	457f3400 	uqshrnt	z0\.s, z0\.d, #1
+ *[0-9a-f]+:	45613400 	uqshrnt	z0\.s, z0\.d, #31
+ *[0-9a-f]+:	45603400 	uqshrnt	z0\.s, z0\.d, #32
+ *[0-9a-f]+:	441b96b1 	uqsub	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441b8000 	uqsub	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445b8000 	uqsub	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449b8000 	uqsub	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44db8000 	uqsub	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	441f96b1 	uqsubr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441f8000 	uqsubr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445f8000 	uqsubr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449f8000 	uqsubr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44df8000 	uqsubr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	45284ab1 	uqxtnb	z17\.b, z21\.h
+ *[0-9a-f]+:	45284800 	uqxtnb	z0\.b, z0\.h
+ *[0-9a-f]+:	45304800 	uqxtnb	z0\.h, z0\.s
+ *[0-9a-f]+:	45604800 	uqxtnb	z0\.s, z0\.d
+ *[0-9a-f]+:	45284eb1 	uqxtnt	z17\.b, z21\.h
+ *[0-9a-f]+:	45284c00 	uqxtnt	z0\.b, z0\.h
+ *[0-9a-f]+:	45304c00 	uqxtnt	z0\.h, z0\.s
+ *[0-9a-f]+:	45604c00 	uqxtnt	z0\.s, z0\.d
+ *[0-9a-f]+:	4480b6b1 	urecpe	z17\.s, p5/m, z21\.s
+ *[0-9a-f]+:	4480a000 	urecpe	z0\.s, p0/m, z0\.s
+ *[0-9a-f]+:	441596b1 	urhadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44158000 	urhadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44558000 	urhadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44958000 	urhadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44d58000 	urhadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440396b1 	urshl	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44038000 	urshl	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44438000 	urshl	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44838000 	urshl	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c38000 	urshl	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	440796b1 	urshlr	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	44078000 	urshlr	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	44478000 	urshlr	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	44878000 	urshlr	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44c78000 	urshlr	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	040d9531 	urshr	z17\.b, p5/m, z17\.b, #7
+ *[0-9a-f]+:	040d8100 	urshr	z0\.b, p0/m, z0\.b, #8
+ *[0-9a-f]+:	040d81e0 	urshr	z0\.b, p0/m, z0\.b, #1
+ *[0-9a-f]+:	040d8200 	urshr	z0\.h, p0/m, z0\.h, #16
+ *[0-9a-f]+:	040d83e0 	urshr	z0\.h, p0/m, z0\.h, #1
+ *[0-9a-f]+:	044d8000 	urshr	z0\.s, p0/m, z0\.s, #32
+ *[0-9a-f]+:	044d83e0 	urshr	z0\.s, p0/m, z0\.s, #1
+ *[0-9a-f]+:	048d8000 	urshr	z0\.d, p0/m, z0\.d, #64
+ *[0-9a-f]+:	04cd83e0 	urshr	z0\.d, p0/m, z0\.d, #1
+ *[0-9a-f]+:	4481b6b1 	ursqrte	z17\.s, p5/m, z21\.s
+ *[0-9a-f]+:	4481a000 	ursqrte	z0\.s, p0/m, z0\.s
+ *[0-9a-f]+:	4509eeb1 	ursra	z17\.b, z21\.b, #7
+ *[0-9a-f]+:	4508ec00 	ursra	z0\.b, z0\.b, #8
+ *[0-9a-f]+:	450fec00 	ursra	z0\.b, z0\.b, #1
+ *[0-9a-f]+:	4510ec00 	ursra	z0\.h, z0\.h, #16
+ *[0-9a-f]+:	451fec00 	ursra	z0\.h, z0\.h, #1
+ *[0-9a-f]+:	4540ec00 	ursra	z0\.s, z0\.s, #32
+ *[0-9a-f]+:	455fec00 	ursra	z0\.s, z0\.s, #1
+ *[0-9a-f]+:	4580ec00 	ursra	z0\.d, z0\.d, #64
+ *[0-9a-f]+:	45dfec00 	ursra	z0\.d, z0\.d, #1
+ *[0-9a-f]+:	4509aab1 	ushllb	z17\.h, z21\.b, #1
+ *[0-9a-f]+:	4508a800 	ushllb	z0\.h, z0\.b, #0
+ *[0-9a-f]+:	450fa800 	ushllb	z0\.h, z0\.b, #7
+ *[0-9a-f]+:	4510a800 	ushllb	z0\.s, z0\.h, #0
+ *[0-9a-f]+:	451fa800 	ushllb	z0\.s, z0\.h, #15
+ *[0-9a-f]+:	4540a800 	ushllb	z0\.d, z0\.s, #0
+ *[0-9a-f]+:	455fa800 	ushllb	z0\.d, z0\.s, #31
+ *[0-9a-f]+:	4509aeb1 	ushllt	z17\.h, z21\.b, #1
+ *[0-9a-f]+:	4508ac00 	ushllt	z0\.h, z0\.b, #0
+ *[0-9a-f]+:	450fac00 	ushllt	z0\.h, z0\.b, #7
+ *[0-9a-f]+:	4510ac00 	ushllt	z0\.s, z0\.h, #0
+ *[0-9a-f]+:	451fac00 	ushllt	z0\.s, z0\.h, #15
+ *[0-9a-f]+:	4540ac00 	ushllt	z0\.d, z0\.s, #0
+ *[0-9a-f]+:	455fac00 	ushllt	z0\.d, z0\.s, #31
+ *[0-9a-f]+:	441d96b1 	usqadd	z17\.b, p5/m, z17\.b, z21\.b
+ *[0-9a-f]+:	441d8000 	usqadd	z0\.b, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+:	445d8000 	usqadd	z0\.h, p0/m, z0\.h, z0\.h
+ *[0-9a-f]+:	449d8000 	usqadd	z0\.s, p0/m, z0\.s, z0\.s
+ *[0-9a-f]+:	44dd8000 	usqadd	z0\.d, p0/m, z0\.d, z0\.d
+ *[0-9a-f]+:	4509e6b1 	usra	z17\.b, z21\.b, #7
+ *[0-9a-f]+:	4508e400 	usra	z0\.b, z0\.b, #8
+ *[0-9a-f]+:	450fe400 	usra	z0\.b, z0\.b, #1
+ *[0-9a-f]+:	4510e400 	usra	z0\.h, z0\.h, #16
+ *[0-9a-f]+:	451fe400 	usra	z0\.h, z0\.h, #1
+ *[0-9a-f]+:	4540e400 	usra	z0\.s, z0\.s, #32
+ *[0-9a-f]+:	455fe400 	usra	z0\.s, z0\.s, #1
+ *[0-9a-f]+:	4580e400 	usra	z0\.d, z0\.d, #64
+ *[0-9a-f]+:	45dfe400 	usra	z0\.d, z0\.d, #1
+ *[0-9a-f]+:	455b1ab1 	usublb	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45401800 	usublb	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45801800 	usublb	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c01800 	usublb	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b1eb1 	usublt	z17\.h, z21\.b, z27\.b
+ *[0-9a-f]+:	45401c00 	usublt	z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+:	45801c00 	usublt	z0\.s, z0\.h, z0\.h
+ *[0-9a-f]+:	45c01c00 	usublt	z0\.d, z0\.s, z0\.s
+ *[0-9a-f]+:	455b5ab1 	usubwb	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45405800 	usubwb	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45805800 	usubwb	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c05800 	usubwb	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	455b5eb1 	usubwt	z17\.h, z21\.h, z27\.b
+ *[0-9a-f]+:	45405c00 	usubwt	z0\.h, z0\.h, z0\.b
+ *[0-9a-f]+:	45805c00 	usubwt	z0\.s, z0\.s, z0\.h
+ *[0-9a-f]+:	45c05c00 	usubwt	z0\.d, z0\.d, z0\.s
+ *[0-9a-f]+:	253b12a9 	whilege	p9\.b, x21, x27
+ *[0-9a-f]+:	25201000 	whilege	p0\.b, x0, x0
+ *[0-9a-f]+:	252013e0 	whilege	p0\.b, xzr, x0
+ *[0-9a-f]+:	253f1000 	whilege	p0\.b, x0, xzr
+ *[0-9a-f]+:	25601000 	whilege	p0\.h, x0, x0
+ *[0-9a-f]+:	25a01000 	whilege	p0\.s, x0, x0
+ *[0-9a-f]+:	25e01000 	whilege	p0\.d, x0, x0
+ *[0-9a-f]+:	253b02a9 	whilege	p9\.b, w21, w27
+ *[0-9a-f]+:	25200000 	whilege	p0\.b, w0, w0
+ *[0-9a-f]+:	252003e0 	whilege	p0\.b, wzr, w0
+ *[0-9a-f]+:	253f0000 	whilege	p0\.b, w0, wzr
+ *[0-9a-f]+:	25600000 	whilege	p0\.h, w0, w0
+ *[0-9a-f]+:	25a00000 	whilege	p0\.s, w0, w0
+ *[0-9a-f]+:	25e00000 	whilege	p0\.d, w0, w0
+ *[0-9a-f]+:	253b12b9 	whilegt	p9\.b, x21, x27
+ *[0-9a-f]+:	25201010 	whilegt	p0\.b, x0, x0
+ *[0-9a-f]+:	252013f0 	whilegt	p0\.b, xzr, x0
+ *[0-9a-f]+:	253f1010 	whilegt	p0\.b, x0, xzr
+ *[0-9a-f]+:	25601010 	whilegt	p0\.h, x0, x0
+ *[0-9a-f]+:	25a01010 	whilegt	p0\.s, x0, x0
+ *[0-9a-f]+:	25e01010 	whilegt	p0\.d, x0, x0
+ *[0-9a-f]+:	253b02b9 	whilegt	p9\.b, w21, w27
+ *[0-9a-f]+:	25200010 	whilegt	p0\.b, w0, w0
+ *[0-9a-f]+:	252003f0 	whilegt	p0\.b, wzr, w0
+ *[0-9a-f]+:	253f0010 	whilegt	p0\.b, w0, wzr
+ *[0-9a-f]+:	25600010 	whilegt	p0\.h, w0, w0
+ *[0-9a-f]+:	25a00010 	whilegt	p0\.s, w0, w0
+ *[0-9a-f]+:	25e00010 	whilegt	p0\.d, w0, w0
+ *[0-9a-f]+:	253b1ab9 	whilehi	p9\.b, x21, x27
+ *[0-9a-f]+:	25201810 	whilehi	p0\.b, x0, x0
+ *[0-9a-f]+:	25201bf0 	whilehi	p0\.b, xzr, x0
+ *[0-9a-f]+:	253f1810 	whilehi	p0\.b, x0, xzr
+ *[0-9a-f]+:	25601810 	whilehi	p0\.h, x0, x0
+ *[0-9a-f]+:	25a01810 	whilehi	p0\.s, x0, x0
+ *[0-9a-f]+:	25e01810 	whilehi	p0\.d, x0, x0
+ *[0-9a-f]+:	253b0ab9 	whilehi	p9\.b, w21, w27
+ *[0-9a-f]+:	25200810 	whilehi	p0\.b, w0, w0
+ *[0-9a-f]+:	25200bf0 	whilehi	p0\.b, wzr, w0
+ *[0-9a-f]+:	253f0810 	whilehi	p0\.b, w0, wzr
+ *[0-9a-f]+:	25600810 	whilehi	p0\.h, w0, w0
+ *[0-9a-f]+:	25a00810 	whilehi	p0\.s, w0, w0
+ *[0-9a-f]+:	25e00810 	whilehi	p0\.d, w0, w0
+ *[0-9a-f]+:	253b1aa9 	whilehs	p9\.b, x21, x27
+ *[0-9a-f]+:	25201800 	whilehs	p0\.b, x0, x0
+ *[0-9a-f]+:	25201be0 	whilehs	p0\.b, xzr, x0
+ *[0-9a-f]+:	253f1800 	whilehs	p0\.b, x0, xzr
+ *[0-9a-f]+:	25601800 	whilehs	p0\.h, x0, x0
+ *[0-9a-f]+:	25a01800 	whilehs	p0\.s, x0, x0
+ *[0-9a-f]+:	25e01800 	whilehs	p0\.d, x0, x0
+ *[0-9a-f]+:	253b0aa9 	whilehs	p9\.b, w21, w27
+ *[0-9a-f]+:	25200800 	whilehs	p0\.b, w0, w0
+ *[0-9a-f]+:	25200be0 	whilehs	p0\.b, wzr, w0
+ *[0-9a-f]+:	253f0800 	whilehs	p0\.b, w0, wzr
+ *[0-9a-f]+:	25600800 	whilehs	p0\.h, w0, w0
+ *[0-9a-f]+:	25a00800 	whilehs	p0\.s, w0, w0
+ *[0-9a-f]+:	25e00800 	whilehs	p0\.d, w0, w0
+ *[0-9a-f]+:	253b32b9 	whilerw	p9\.b, x21, x27
+ *[0-9a-f]+:	25203010 	whilerw	p0\.b, x0, x0
+ *[0-9a-f]+:	25603010 	whilerw	p0\.h, x0, x0
+ *[0-9a-f]+:	25a03010 	whilerw	p0\.s, x0, x0
+ *[0-9a-f]+:	25e03010 	whilerw	p0\.d, x0, x0
+ *[0-9a-f]+:	253b32a9 	whilewr	p9\.b, x21, x27
+ *[0-9a-f]+:	25203000 	whilewr	p0\.b, x0, x0
+ *[0-9a-f]+:	25603000 	whilewr	p0\.h, x0, x0
+ *[0-9a-f]+:	25a03000 	whilewr	p0\.s, x0, x0
+ *[0-9a-f]+:	25e03000 	whilewr	p0\.d, x0, x0
+ *[0-9a-f]+:	042936b1 	xar	z17\.b, z17\.b, z21\.b, #7
+ *[0-9a-f]+:	04283400 	xar	z0\.b, z0\.b, z0\.b, #8
+ *[0-9a-f]+:	042f3400 	xar	z0\.b, z0\.b, z0\.b, #1
+ *[0-9a-f]+:	04303400 	xar	z0\.h, z0\.h, z0\.h, #16
+ *[0-9a-f]+:	043f3400 	xar	z0\.h, z0\.h, z0\.h, #1
+ *[0-9a-f]+:	04603400 	xar	z0\.s, z0\.s, z0\.s, #32
+ *[0-9a-f]+:	047f3400 	xar	z0\.s, z0\.s, z0\.s, #1
+ *[0-9a-f]+:	04a03400 	xar	z0\.d, z0\.d, z0\.d, #64
+ *[0-9a-f]+:	04ff3400 	xar	z0\.d, z0\.d, z0\.d, #1
diff --git a/gas/testsuite/gas/aarch64/sve2.s b/gas/testsuite/gas/aarch64/sve2.s
new file mode 100644
index 0000000..13d2e2a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2.s
@@ -0,0 +1,1595 @@
+/* The instructions with non-zero register numbers are there to ensure we have
+   the correct argument positioning (i.e. check that the first argument is at
+   the end of the word etc).
+   The instructions with all-zero register numbers are to ensure the previous
+   encoding didn't just "happen" to fit -- so that if we change the registers
+   that changes the correct part of the word.
+   Each of the numbered patterns begin and end with a 1, so we can replace
+   them with all-zeros and see the entire range has changed.
+   17 -> 10001
+   21 -> 10101
+   27 -> 11011
+   */
+
+movprfx z0, z1
+adclb z0.d, z1.d, z2.d
+
+adclb z17.s, z21.s, z27.s
+adclb z0.s, z0.s, z0.s
+adclb z0.d, z0.d, z0.d
+
+adclt z17.s, z21.s, z27.s
+adclt z0.s, z0.s, z0.s
+adclt z0.d, z0.d, z0.d
+
+addhnb z17.b, z21.h, z27.h
+addhnb z0.b, z0.h, z0.h
+addhnb z0.h, z0.s, z0.s
+addhnb z0.s, z0.d, z0.d
+
+addhnt z17.b, z21.h, z27.h
+addhnt z0.b, z0.h, z0.h
+addhnt z0.h, z0.s, z0.s
+addhnt z0.s, z0.d, z0.d
+
+movprfx z0.d, p0/m, z1.d
+addp z0.d, p0/m, z0.d, z1.d
+
+addp z17.b, p5/m, z17.b, z21.b
+addp z0.b, p0/m, z0.b, z0.b
+addp z0.h, p0/m, z0.h, z0.h
+addp z0.s, p0/m, z0.s, z0.s
+addp z0.d, p0/m, z0.d, z0.d
+
+aesd z17.b, z17.b, z21.b
+aesd z0.b, z0.b, z0.b
+aese z17.b, z17.b, z21.b
+aese z0.b, z0.b, z0.b
+
+aesimc z17.b, z17.b
+aesimc z0.b, z0.b
+
+aesmc z17.b, z17.b
+aesmc z0.b, z0.b
+
+bcax z17.d, z17.d, z21.d, z27.d
+bcax z0.d, z0.d, z0.d, z0.d
+
+bsl z17.d, z17.d, z21.d, z27.d
+bsl z0.d, z0.d, z0.d, z0.d
+
+bsl1n z17.d, z17.d, z21.d, z27.d
+bsl1n z0.d, z0.d, z0.d, z0.d
+
+bsl2n z17.d, z17.d, z21.d, z27.d
+bsl2n z0.d, z0.d, z0.d, z0.d
+
+bdep z17.b, z21.b, z27.b
+bdep z0.b, z0.b, z0.b
+bdep z0.h, z0.h, z0.h
+bdep z0.s, z0.s, z0.s
+bdep z0.d, z0.d, z0.d
+
+bext z17.b, z21.b, z27.b
+bext z0.b, z0.b, z0.b
+bext z0.h, z0.h, z0.h
+bext z0.s, z0.s, z0.s
+bext z0.d, z0.d, z0.d
+
+bgrp z17.b, z21.b, z27.b
+bgrp z0.b, z0.b, z0.b
+bgrp z0.h, z0.h, z0.h
+bgrp z0.s, z0.s, z0.s
+bgrp z0.d, z0.d, z0.d
+
+cadd z17.b, z17.b, z21.b, #90
+cadd z0.b, z0.b, z0.b, #90
+cadd z0.h, z0.h, z0.h, #90
+cadd z0.s, z0.s, z0.s, #90
+cadd z0.d, z0.d, z0.d, #90
+cadd z0.b, z0.b, z0.b, #270
+
+cdot z17.s, z21.b, z3.b[3], #0
+cdot z0.s, z0.b, z0.b[0], #0
+cdot z0.s, z0.b, z0.b[0], #90
+cdot z0.s, z0.b, z0.b[0], #180
+cdot z0.s, z0.b, z0.b[0], #270
+
+cdot z17.d, z21.h, z11.h[1], #0
+cdot z0.d, z0.h, z0.h[0], #0
+cdot z0.d, z0.h, z0.h[0], #90
+cdot z0.d, z0.h, z0.h[0], #180
+cdot z0.d, z0.h, z0.h[0], #270
+
+cdot z17.s, z21.b, z27.b, #0
+cdot z0.s, z0.b, z0.b, #0
+cdot z0.d, z0.h, z0.h, #0
+cdot z0.s, z0.b, z0.b, #90
+cdot z0.s, z0.b, z0.b, #180
+cdot z0.s, z0.b, z0.b, #270
+
+cmla z17.h, z21.h, z3.h[3], #0
+cmla z0.h, z0.h, z0.h[0], #0
+cmla z0.h, z0.h, z0.h[0], #90
+cmla z0.h, z0.h, z0.h[0], #180
+cmla z0.h, z0.h, z0.h[0], #270
+
+cmla z17.s, z21.s, z11.s[1], #0
+cmla z0.s, z0.s, z0.s[0], #0
+cmla z0.s, z0.s, z0.s[0], #90
+cmla z0.s, z0.s, z0.s[0], #180
+cmla z0.s, z0.s, z0.s[0], #270
+
+cmla z17.b, z21.b, z27.b, #0
+cmla z0.b, z0.b, z0.b, #0
+cmla z0.h, z0.h, z0.h, #0
+cmla z0.s, z0.s, z0.s, #0
+cmla z0.d, z0.d, z0.d, #0
+cmla z0.b, z0.b, z0.b, #90
+cmla z0.b, z0.b, z0.b, #180
+cmla z0.b, z0.b, z0.b, #270
+
+eor3 z17.d, z17.d, z21.d, z27.d
+eor3 z0.d, z0.d, z0.d, z0.d
+
+eorbt z17.b, z21.b, z27.b
+eorbt z0.b, z0.b, z0.b
+eorbt z0.h, z0.h, z0.h
+eorbt z0.s, z0.s, z0.s
+eorbt z0.d, z0.d, z0.d
+
+eortb z17.b, z21.b, z27.b
+eortb z0.b, z0.b, z0.b
+eortb z0.h, z0.h, z0.h
+eortb z0.s, z0.s, z0.s
+eortb z0.d, z0.d, z0.d
+
+ext z17.b, { z21.b, z22.b }, #221
+ext z0.b, { z0.b, z1.b }, #0
+ext z0.b, { z31.b, z0.b }, #0
+
+faddp z17.h, p5/m, z17.h, z21.h
+faddp z0.h, p0/m, z0.h, z0.h
+faddp z0.s, p0/m, z0.s, z0.s
+faddp z0.d, p0/m, z0.d, z0.d
+
+fcvtlt z17.s, p5/m, z21.h
+fcvtlt z0.s, p0/m, z0.h
+fcvtlt z17.d, p5/m, z21.s
+fcvtlt z0.d, p0/m, z0.s
+
+fcvtnt z17.h, p5/m, z21.s
+fcvtnt z0.h, p0/m, z0.s
+fcvtnt z17.s, p5/m, z21.d
+fcvtnt z0.s, p0/m, z0.d
+
+fcvtx z17.s, p5/m, z21.d
+fcvtx z0.s, p0/m, z0.d
+
+movprfx z0.d, p0/z, z1.d
+fcvtx z0.s, p0/m, z2.d
+
+fcvtxnt z17.s, p5/m, z21.d
+fcvtxnt z0.s, p0/m, z0.d
+
+flogb z17.h, p5/m, z21.h
+flogb z0.h, p0/m, z0.h
+flogb z0.s, p0/m, z0.s
+flogb z0.d, p0/m, z0.d
+
+fmaxnmp z17.h, p5/m, z17.h, z21.h
+fmaxnmp z0.h, p0/m, z0.h, z0.h
+fmaxnmp z0.s, p0/m, z0.s, z0.s
+fmaxnmp z0.d, p0/m, z0.d, z0.d
+
+fmaxp z17.h, p5/m, z17.h, z21.h
+fmaxp z0.h, p0/m, z0.h, z0.h
+fmaxp z0.s, p0/m, z0.s, z0.s
+fmaxp z0.d, p0/m, z0.d, z0.d
+
+fminnmp z17.h, p5/m, z17.h, z21.h
+fminnmp z0.h, p0/m, z0.h, z0.h
+fminnmp z0.s, p0/m, z0.s, z0.s
+fminnmp z0.d, p0/m, z0.d, z0.d
+
+fminp z17.h, p5/m, z17.h, z21.h
+fminp z0.h, p0/m, z0.h, z0.h
+fminp z0.s, p0/m, z0.s, z0.s
+fminp z0.d, p0/m, z0.d, z0.d
+
+fmlalb z17.s, z21.h, z5.h[0]
+fmlalb z0.s, z0.h, z0.h[5]
+fmlalb z0.s, z0.h, z0.h[0]
+
+fmlalb z17.s, z21.h, z27.h
+fmlalb z0.s, z0.h, z0.h
+
+fmlalt z17.s, z21.h, z5.h[0]
+fmlalt z0.s, z0.h, z0.h[5]
+fmlalt z0.s, z0.h, z0.h[0]
+
+fmlalt z17.s, z21.h, z27.h
+fmlalt z0.s, z0.h, z0.h
+
+fmlslb z17.s, z21.h, z5.h[0]
+fmlslb z0.s, z0.h, z0.h[5]
+fmlslb z0.s, z0.h, z0.h[0]
+
+fmlslb z17.s, z21.h, z27.h
+fmlslb z0.s, z0.h, z0.h
+
+fmlslt z17.s, z21.h, z5.h[0]
+fmlslt z0.s, z0.h, z0.h[5]
+fmlslt z0.s, z0.h, z0.h[0]
+
+fmlslt z17.s, z21.h, z27.h
+fmlslt z0.s, z0.h, z0.h
+
+histcnt z17.s, p5/z, z21.s, z27.s
+histcnt z0.s, p0/z, z0.s, z0.s
+histcnt z0.d, p0/z, z0.d, z0.d
+
+histseg z17.b, z21.b, z27.b
+histseg z0.b, z0.b, z0.b
+
+ldnt1b { z17.d }, p5/z, [z21.d, x27]
+ldnt1b { z0.d }, p0/z, [z0.d, x0]
+ldnt1b { z0.d }, p0/z, [z0.d]
+ldnt1b { z0.d }, p0/z, [z0.d, xzr]
+ldnt1b { z17.s }, p5/z, [z21.s, x27]
+ldnt1b { z0.s }, p0/z, [z0.s, x0]
+ldnt1b { z0.s }, p0/z, [z0.s]
+ldnt1b { z0.s }, p0/z, [z0.s, xzr]
+
+ldnt1d { z17.d }, p5/z, [z21.d, x27]
+ldnt1d { z0.d }, p0/z, [z0.d, x0]
+ldnt1d { z0.d }, p0/z, [z0.d]
+ldnt1d { z0.d }, p0/z, [z0.d, xzr]
+
+ldnt1h { z17.d }, p5/z, [z21.d, x27]
+ldnt1h { z0.d }, p0/z, [z0.d, x0]
+ldnt1h { z0.d }, p0/z, [z0.d]
+ldnt1h { z0.d }, p0/z, [z0.d, xzr]
+ldnt1h { z17.s }, p5/z, [z21.s, x27]
+ldnt1h { z0.s }, p0/z, [z0.s, x0]
+ldnt1h { z0.s }, p0/z, [z0.s]
+ldnt1h { z0.s }, p0/z, [z0.s, xzr]
+
+ldnt1sb { z17.s }, p5/z, [z21.s, x27]
+ldnt1sb { z0.s }, p0/z, [z0.s, x0]
+ldnt1sb { z0.s }, p0/z, [z0.s]
+ldnt1sb { z0.s }, p0/z, [z0.s, xzr]
+ldnt1sb { z0.d }, p0/z, [z0.d, x0]
+ldnt1sb { z0.d }, p0/z, [z0.d]
+ldnt1sb { z0.d }, p0/z, [z0.d, xzr]
+
+ldnt1sh { z17.s }, p5/z, [z21.s, x27]
+ldnt1sh { z0.s }, p0/z, [z0.s, x0]
+ldnt1sh { z0.s }, p0/z, [z0.s]
+ldnt1sh { z0.s }, p0/z, [z0.s, xzr]
+ldnt1sh { z0.d }, p0/z, [z0.d, x0]
+ldnt1sh { z0.d }, p0/z, [z0.d]
+ldnt1sh { z0.d }, p0/z, [z0.d, xzr]
+
+ldnt1sw { z17.d }, p5/z, [z21.d, x27]
+ldnt1sw { z0.d }, p0/z, [z0.d, x0]
+ldnt1sw { z0.d }, p0/z, [z0.d]
+ldnt1sw { z0.d }, p0/z, [z0.d, xzr]
+
+ldnt1w { z17.s }, p5/z, [z21.s, x27]
+ldnt1w { z0.s }, p0/z, [z0.s, x0]
+ldnt1w { z0.s }, p0/z, [z0.s]
+ldnt1w { z0.s }, p0/z, [z0.s, xzr]
+ldnt1w { z17.d }, p5/z, [z21.d, x27]
+ldnt1w { z0.d }, p0/z, [z0.d, x0]
+ldnt1w { z0.d }, p0/z, [z0.d]
+ldnt1w { z0.d }, p0/z, [z0.d, xzr]
+
+match p9.b, p5/z, z17.b, z21.b
+match p0.b, p0/z, z17.b, z21.b
+match p0.b, p0/z, z0.b, z0.b
+match p0.h, p0/z, z0.h, z0.h
+
+mla z17.h, z21.h, z3.h[3]
+mla z0.h, z0.h, z0.h[4]
+mla z0.h, z0.h, z0.h[0]
+
+mla z17.s, z21.s, z3.s[3]
+mla z0.s, z0.s, z0.s[0]
+
+mla z17.d, z21.d, z11.d[1]
+mla z0.d, z0.d, z0.d[0]
+
+mls z17.h, z21.h, z3.h[3]
+mls z0.h, z0.h, z0.h[4]
+mls z0.h, z0.h, z0.h[0]
+
+mls z17.s, z21.s, z3.s[3]
+mls z0.s, z0.s, z0.s[0]
+
+mls z17.d, z21.d, z11.d[1]
+mls z0.d, z0.d, z0.d[0]
+
+mul z17.h, z21.h, z3.h[3]
+mul z0.h, z0.h, z0.h[4]
+mul z0.h, z0.h, z0.h[0]
+
+mul z17.s, z21.s, z3.s[3]
+mul z0.s, z0.s, z0.s[0]
+
+mul z17.d, z21.d, z11.d[1]
+mul z0.d, z0.d, z0.d[0]
+
+mul z17.b, z21.b, z27.b
+mul z0.b, z0.b, z0.b
+mul z0.h, z0.h, z0.h
+mul z0.s, z0.s, z0.s
+mul z0.d, z0.d, z0.d
+
+nmatch p9.b, p5/z, z21.b, z27.b
+nmatch p0.b, p0/z, z0.b, z0.b
+nmatch p0.h, p0/z, z0.h, z0.h
+
+nbsl z17.d, z17.d, z21.d, z27.d
+nbsl z0.d, z0.d, z0.d, z0.d
+
+pmul z17.b, z21.b, z27.b
+pmul z0.b, z0.b, z0.b
+
+pmullb z17.q, z21.d, z27.d
+pmullb z0.q, z0.d, z0.d
+pmullb z0.h, z0.b, z0.b
+pmullb z0.d, z0.s, z0.s
+
+pmullt z17.q, z21.d, z27.d
+pmullt z0.q, z0.d, z0.d
+pmullt z0.h, z0.b, z0.b
+pmullt z0.d, z0.s, z0.s
+
+raddhnb z17.b, z21.h, z27.h
+raddhnb z0.b, z0.h, z0.h
+raddhnb z0.h, z0.s, z0.s
+raddhnb z0.s, z0.d, z0.d
+
+raddhnt z17.b, z21.h, z27.h
+raddhnt z0.b, z0.h, z0.h
+raddhnt z0.h, z0.s, z0.s
+raddhnt z0.s, z0.d, z0.d
+
+rax1 z17.d, z21.d, z27.d
+rax1 z0.d, z0.d, z0.d
+
+# Shift is encoded as 2*esize - (tsz:imm3)
+# For .b .h first two bits are 0, want 1001 to match pattern of ones on the
+# outside, hence use 7.
+# For all zeros except the minimum size bit, use maximum size.
+rshrnb z17.b, z21.h, #7
+rshrnb z0.b, z0.h, #1
+rshrnb z0.b, z0.h, #8
+# .h .s 0100001 = 15
+rshrnb z0.h, z0.s, #1
+rshrnb z0.h, z0.s, #15
+rshrnb z0.h, z0.s, #16
+# .s .d 1000001 = 31
+rshrnb z0.s, z0.d, #1
+rshrnb z0.s, z0.d, #31
+rshrnb z0.s, z0.d, #32
+
+rshrnt z17.b, z21.h, #7
+rshrnt z0.b, z0.h, #1
+rshrnt z0.b, z0.h, #8
+rshrnt z0.h, z0.s, #1
+rshrnt z0.h, z0.s, #15
+rshrnt z0.h, z0.s, #16
+rshrnt z0.s, z0.d, #1
+rshrnt z0.s, z0.d, #31
+rshrnt z0.s, z0.d, #32
+
+rsubhnb z17.b, z21.h, z27.h
+rsubhnb z0.b, z0.h, z0.h
+rsubhnb z0.h, z0.s, z0.s
+rsubhnb z0.s, z0.d, z0.d
+
+rsubhnt z17.b, z21.h, z27.h
+rsubhnt z0.b, z0.h, z0.h
+rsubhnt z0.h, z0.s, z0.s
+rsubhnt z0.s, z0.d, z0.d
+
+saba z17.b, z21.b, z27.b
+saba z0.b, z0.b, z0.b
+saba z0.h, z0.h, z0.h
+saba z0.s, z0.s, z0.s
+saba z0.d, z0.d, z0.d
+
+sabalb z17.h, z21.b, z27.b
+sabalb z0.h, z0.b, z0.b
+sabalb z0.s, z0.h, z0.h
+sabalb z0.d, z0.s, z0.s
+
+sabalt z17.h, z21.b, z27.b
+sabalt z0.h, z0.b, z0.b
+sabalt z0.s, z0.h, z0.h
+sabalt z0.d, z0.s, z0.s
+
+sabdlb z17.h, z21.b, z27.b
+sabdlb z0.h, z0.b, z0.b
+sabdlb z0.s, z0.h, z0.h
+sabdlb z0.d, z0.s, z0.s
+
+sabdlt z17.h, z21.b, z27.b
+sabdlt z0.h, z0.b, z0.b
+sabdlt z0.s, z0.h, z0.h
+sabdlt z0.d, z0.s, z0.s
+
+sadalp z17.h, p5/m, z21.b
+sadalp z0.h, p0/m, z0.b
+sadalp z0.s, p0/m, z0.h
+sadalp z0.d, p0/m, z0.s
+
+saddlb z17.h, z21.b, z27.b
+saddlb z0.h, z0.b, z0.b
+saddlb z0.s, z0.h, z0.h
+saddlb z0.d, z0.s, z0.s
+
+saddlbt z17.h, z21.b, z27.b
+saddlbt z0.h, z0.b, z0.b
+saddlbt z0.s, z0.h, z0.h
+saddlbt z0.d, z0.s, z0.s
+
+saddlt z17.h, z21.b, z27.b
+saddlt z0.h, z0.b, z0.b
+saddlt z0.s, z0.h, z0.h
+saddlt z0.d, z0.s, z0.s
+
+saddwb z17.h, z21.h, z27.b
+saddwb z0.h, z0.h, z0.b
+saddwb z0.s, z0.s, z0.h
+saddwb z0.d, z0.d, z0.s
+
+saddwt z17.h, z21.h, z27.b
+saddwt z0.h, z0.h, z0.b
+saddwt z0.s, z0.s, z0.h
+saddwt z0.d, z0.d, z0.s
+
+sbclb z17.s, z21.s, z27.s
+sbclb z0.s, z0.s, z0.s
+sbclb z0.d, z0.d, z0.d
+
+sbclt z17.s, z21.s, z27.s
+sbclt z0.s, z0.s, z0.s
+sbclt z0.d, z0.d, z0.d
+
+shadd z17.b, p5/m, z17.b, z21.b
+shadd z0.b, p0/m, z0.b, z0.b
+shadd z0.h, p0/m, z0.h, z0.h
+shadd z0.s, p0/m, z0.s, z0.s
+shadd z0.d, p0/m, z0.d, z0.d
+
+shrnb z17.b, z21.h, #7
+shrnb z0.b, z0.h, #1
+shrnb z0.b, z0.h, #8
+shrnb z0.h, z0.s, #1
+shrnb z0.h, z0.s, #15
+shrnb z0.h, z0.s, #16
+shrnb z0.s, z0.d, #1
+shrnb z0.s, z0.d, #31
+shrnb z0.s, z0.d, #32
+
+shrnt z17.b, z21.h, #7
+shrnt z0.b, z0.h, #1
+shrnt z0.b, z0.h, #8
+shrnt z0.h, z0.s, #1
+shrnt z0.h, z0.s, #15
+shrnt z0.h, z0.s, #16
+shrnt z0.s, z0.d, #1
+shrnt z0.s, z0.d, #31
+shrnt z0.s, z0.d, #32
+
+shsub z17.b, p5/m, z17.b, z21.b
+shsub z0.b, p0/m, z0.b, z0.b
+shsub z0.h, p0/m, z0.h, z0.h
+shsub z0.s, p0/m, z0.s, z0.s
+shsub z0.d, p0/m, z0.d, z0.d
+
+shsubr z17.b, p5/m, z17.b, z21.b
+shsubr z0.b, p0/m, z0.b, z0.b
+shsubr z0.h, p0/m, z0.h, z0.h
+shsubr z0.s, p0/m, z0.s, z0.s
+shsubr z0.d, p0/m, z0.d, z0.d
+
+# shift - esize == 0b1001
+# All other tests alternate between 1000... and 1111...
+sli z17.b, z21.b, #1
+sli z0.b, z0.b, #0
+sli z0.b, z0.b, #7
+sli z0.h, z0.h, #0
+sli z0.h, z0.h, #15
+sli z0.s, z0.s, #0
+sli z0.s, z0.s, #31
+sli z0.d, z0.d, #0
+sli z0.d, z0.d, #63
+
+sm4e z17.s, z17.s, z21.s
+sm4e z0.s, z0.s, z0.s
+
+sm4ekey z17.s, z21.s, z27.s
+sm4ekey z0.s, z0.s, z0.s
+
+smaxp z17.b, p5/m, z17.b, z21.b
+smaxp z0.b, p0/m, z0.b, z0.b
+smaxp z0.h, p0/m, z0.h, z0.h
+smaxp z0.s, p0/m, z0.s, z0.s
+smaxp z0.d, p0/m, z0.d, z0.d
+
+sminp z17.b, p5/m, z17.b, z21.b
+sminp z0.b, p0/m, z0.b, z0.b
+sminp z0.h, p0/m, z0.h, z0.h
+sminp z0.s, p0/m, z0.s, z0.s
+sminp z0.d, p0/m, z0.d, z0.d
+
+smlalb z17.s, z21.h, z5.h[0]
+smlalb z0.s, z0.h, z0.h[5]
+smlalb z0.s, z0.h, z0.h[0]
+
+smlalb z17.d, z21.s, z9.s[0]
+smlalb z0.d, z0.s, z0.s[3]
+smlalb z0.d, z0.s, z0.s[0]
+
+smlalb z17.h, z21.b, z27.b
+smlalb z0.h, z0.b, z0.b
+smlalb z0.s, z0.h, z0.h
+smlalb z0.d, z0.s, z0.s
+
+smlalt z17.s, z21.h, z5.h[0]
+smlalt z0.s, z0.h, z0.h[5]
+smlalt z0.s, z0.h, z0.h[0]
+
+smlalt z17.d, z21.s, z9.s[0]
+smlalt z0.d, z0.s, z0.s[3]
+smlalt z0.d, z0.s, z0.s[0]
+
+smlalt z17.h, z21.b, z27.b
+smlalt z0.h, z0.b, z0.b
+smlalt z0.s, z0.h, z0.h
+smlalt z0.d, z0.s, z0.s
+
+smlslb z17.s, z21.h, z5.h[0]
+smlslb z0.s, z0.h, z0.h[5]
+smlslb z0.s, z0.h, z0.h[0]
+
+smlslb z17.d, z21.s, z9.s[0]
+smlslb z0.d, z0.s, z0.s[3]
+smlslb z0.d, z0.s, z0.s[0]
+
+smlslb z17.h, z21.b, z27.b
+smlslb z0.h, z0.b, z0.b
+smlslb z0.s, z0.h, z0.h
+smlslb z0.d, z0.s, z0.s
+
+smlslt z17.s, z21.h, z5.h[0]
+smlslt z0.s, z0.h, z0.h[5]
+smlslt z0.s, z0.h, z0.h[0]
+
+smlslt z17.d, z21.s, z9.s[0]
+smlslt z0.d, z0.s, z0.s[3]
+smlslt z0.d, z0.s, z0.s[0]
+
+smlslt z17.h, z21.b, z27.b
+smlslt z0.h, z0.b, z0.b
+smlslt z0.s, z0.h, z0.h
+smlslt z0.d, z0.s, z0.s
+
+smulh z17.b, z21.b, z27.b
+smulh z0.b, z0.b, z0.b
+smulh z0.h, z0.h, z0.h
+smulh z0.s, z0.s, z0.s
+smulh z0.d, z0.d, z0.d
+
+smullb z17.s, z21.h, z5.h[0]
+smullb z0.s, z0.h, z0.h[5]
+smullb z0.s, z0.h, z0.h[0]
+
+smullb z17.d, z21.s, z9.s[0]
+smullb z0.d, z0.s, z0.s[3]
+smullb z0.d, z0.s, z0.s[0]
+
+smullb z17.h, z21.b, z27.b
+smullb z0.h, z0.b, z0.b
+smullb z0.s, z0.h, z0.h
+smullb z0.d, z0.s, z0.s
+
+smullt z17.s, z21.h, z5.h[0]
+smullt z0.s, z0.h, z0.h[5]
+smullt z0.s, z0.h, z0.h[0]
+
+smullt z17.d, z21.s, z9.s[0]
+smullt z0.d, z0.s, z0.s[3]
+smullt z0.d, z0.s, z0.s[0]
+
+smullt z17.h, z21.b, z27.b
+smullt z0.h, z0.b, z0.b
+smullt z0.s, z0.h, z0.h
+smullt z0.d, z0.s, z0.s
+
+splice z17.b, p5, { z21.b, z22.b }
+splice z0.b, p0, { z0.b, z1.b }
+splice z0.h, p0, { z0.h, z1.h }
+splice z0.s, p0, { z0.s, z1.s }
+splice z0.d, p0, { z0.d, z1.d }
+splice z0.b, p0, { z31.b, z0.b }
+
+sqabs z17.b, p5/m, z21.b
+sqabs z0.b, p0/m, z0.b
+sqabs z0.h, p0/m, z0.h
+sqabs z0.s, p0/m, z0.s
+sqabs z0.d, p0/m, z0.d
+
+sqadd z17.b, p5/m, z17.b, z21.b
+sqadd z0.b, p0/m, z0.b, z0.b
+sqadd z0.h, p0/m, z0.h, z0.h
+sqadd z0.s, p0/m, z0.s, z0.s
+sqadd z0.d, p0/m, z0.d, z0.d
+
+sqcadd z17.b, z17.b, z21.b, #90
+sqcadd z0.b, z0.b, z0.b, #270
+sqcadd z0.b, z0.b, z0.b, #90
+sqcadd z0.h, z0.h, z0.h, #90
+sqcadd z0.s, z0.s, z0.s, #90
+sqcadd z0.d, z0.d, z0.d, #90
+
+sqdmlalb z17.s, z21.h, z5.h[0]
+sqdmlalb z0.s, z0.h, z0.h[5]
+sqdmlalb z0.s, z0.h, z0.h[0]
+
+sqdmlalb z17.d, z21.s, z9.s[0]
+sqdmlalb z0.d, z0.s, z0.s[3]
+sqdmlalb z0.d, z0.s, z0.s[0]
+
+sqdmlalb z17.h, z21.b, z27.b
+sqdmlalb z0.h, z0.b, z0.b
+sqdmlalb z0.s, z0.h, z0.h
+sqdmlalb z0.d, z0.s, z0.s
+
+sqdmlalbt z17.h, z21.b, z27.b
+sqdmlalbt z0.h, z0.b, z0.b
+sqdmlalbt z0.s, z0.h, z0.h
+sqdmlalbt z0.d, z0.s, z0.s
+
+sqdmlalt z17.s, z21.h, z5.h[0]
+sqdmlalt z0.s, z0.h, z0.h[5]
+sqdmlalt z0.s, z0.h, z0.h[0]
+
+sqdmlalt z17.d, z21.s, z9.s[0]
+sqdmlalt z0.d, z0.s, z0.s[3]
+sqdmlalt z0.d, z0.s, z0.s[0]
+
+sqdmlalt z17.h, z21.b, z27.b
+sqdmlalt z0.h, z0.b, z0.b
+sqdmlalt z0.s, z0.h, z0.h
+sqdmlalt z0.d, z0.s, z0.s
+
+sqdmlslb z17.s, z21.h, z5.h[0]
+sqdmlslb z0.s, z0.h, z0.h[5]
+sqdmlslb z0.s, z0.h, z0.h[0]
+
+sqdmlslb z17.d, z21.s, z9.s[0]
+sqdmlslb z0.d, z0.s, z0.s[3]
+sqdmlslb z0.d, z0.s, z0.s[0]
+
+sqdmlslb z17.h, z21.b, z27.b
+sqdmlslb z0.h, z0.b, z0.b
+sqdmlslb z0.s, z0.h, z0.h
+sqdmlslb z0.d, z0.s, z0.s
+
+sqdmlslbt z17.h, z21.b, z27.b
+sqdmlslbt z0.h, z0.b, z0.b
+sqdmlslbt z0.s, z0.h, z0.h
+sqdmlslbt z0.d, z0.s, z0.s
+
+sqdmlslt z17.s, z21.h, z5.h[0]
+sqdmlslt z0.s, z0.h, z0.h[5]
+sqdmlslt z0.s, z0.h, z0.h[0]
+
+sqdmlslt z17.d, z21.s, z9.s[0]
+sqdmlslt z0.d, z0.s, z0.s[3]
+sqdmlslt z0.d, z0.s, z0.s[0]
+
+sqdmlslt z17.h, z21.b, z27.b
+sqdmlslt z0.h, z0.b, z0.b
+sqdmlslt z0.s, z0.h, z0.h
+sqdmlslt z0.d, z0.s, z0.s
+
+sqdmulh z17.h, z21.h, z5.h[0]
+sqdmulh z0.h, z0.h, z0.h[5]
+sqdmulh z0.h, z0.h, z0.h[0]
+
+sqdmulh z17.s, z21.s, z5.s[0]
+sqdmulh z0.s, z0.s, z0.s[3]
+sqdmulh z0.s, z0.s, z0.s[0]
+
+sqdmulh z17.d, z21.d, z9.d[0]
+sqdmulh z0.d, z0.d, z0.d[1]
+sqdmulh z0.d, z0.d, z0.d[0]
+
+sqdmulh z17.b, z21.b, z27.b
+sqdmulh z0.b, z0.b, z0.b
+sqdmulh z0.h, z0.h, z0.h
+sqdmulh z0.s, z0.s, z0.s
+sqdmulh z0.d, z0.d, z0.d
+
+sqdmullb z17.s, z21.h, z5.h[0]
+sqdmullb z0.s, z0.h, z0.h[5]
+sqdmullb z0.s, z0.h, z0.h[0]
+
+sqdmullb z17.d, z21.s, z9.s[0]
+sqdmullb z0.d, z0.s, z0.s[3]
+sqdmullb z0.d, z0.s, z0.s[0]
+
+sqdmullb z17.h, z21.b, z27.b
+sqdmullb z0.h, z0.b, z0.b
+sqdmullb z0.s, z0.h, z0.h
+sqdmullb z0.d, z0.s, z0.s
+
+sqdmullt z17.s, z21.h, z5.h[0]
+sqdmullt z0.s, z0.h, z0.h[5]
+sqdmullt z0.s, z0.h, z0.h[0]
+
+sqdmullt z17.d, z21.s, z9.s[0]
+sqdmullt z0.d, z0.s, z0.s[3]
+sqdmullt z0.d, z0.s, z0.s[0]
+
+sqdmullt z17.h, z21.b, z27.b
+sqdmullt z0.h, z0.b, z0.b
+sqdmullt z0.s, z0.h, z0.h
+sqdmullt z0.d, z0.s, z0.s
+
+sqneg z17.b, p5/m, z21.b
+sqneg z0.b, p0/m, z0.b
+sqneg z0.h, p0/m, z0.h
+sqneg z0.s, p0/m, z0.s
+sqneg z0.d, p0/m, z0.d
+
+sqrdcmlah z17.h, z21.h, z5.h[0], #0
+sqrdcmlah z0.h, z0.h, z0.h[3], #0
+sqrdcmlah z0.h, z0.h, z0.h[0], #90
+sqrdcmlah z0.h, z0.h, z0.h[0], #180
+sqrdcmlah z0.h, z0.h, z0.h[0], #270
+
+sqrdcmlah z17.s, z21.s, z9.s[0], #0
+sqrdcmlah z0.s, z0.s, z0.s[1], #0
+sqrdcmlah z0.s, z0.s, z0.s[0], #90
+sqrdcmlah z0.s, z0.s, z0.s[0], #180
+sqrdcmlah z0.s, z0.s, z0.s[0], #270
+
+sqrdcmlah z17.b, z21.b, z27.b, #0
+sqrdcmlah z0.b, z0.b, z0.b, #0
+sqrdcmlah z0.b, z0.b, z0.b, #90
+sqrdcmlah z0.b, z0.b, z0.b, #180
+sqrdcmlah z0.b, z0.b, z0.b, #270
+sqrdcmlah z0.h, z0.h, z0.h, #0
+sqrdcmlah z0.s, z0.s, z0.s, #0
+sqrdcmlah z0.d, z0.d, z0.d, #0
+
+sqrdmlah z17.h, z21.h, z5.h[0]
+sqrdmlah z0.h, z0.h, z0.h[5]
+sqrdmlah z0.h, z0.h, z0.h[0]
+
+sqrdmlah z17.s, z21.s, z5.s[0]
+sqrdmlah z0.s, z0.s, z0.s[3]
+sqrdmlah z0.s, z0.s, z0.s[0]
+
+sqrdmlah z17.d, z21.d, z9.d[0]
+sqrdmlah z0.d, z0.d, z0.d[1]
+sqrdmlah z0.d, z0.d, z0.d[0]
+
+sqrdmlah z17.b, z21.b, z27.b
+sqrdmlah z0.b, z0.b, z0.b
+sqrdmlah z0.h, z0.h, z0.h
+sqrdmlah z0.s, z0.s, z0.s
+sqrdmlah z0.d, z0.d, z0.d
+
+sqrdmlsh z17.h, z21.h, z5.h[0]
+sqrdmlsh z0.h, z0.h, z0.h[5]
+sqrdmlsh z0.h, z0.h, z0.h[0]
+
+sqrdmlsh z17.s, z21.s, z5.s[0]
+sqrdmlsh z0.s, z0.s, z0.s[3]
+sqrdmlsh z0.s, z0.s, z0.s[0]
+
+sqrdmlsh z17.d, z21.d, z9.d[0]
+sqrdmlsh z0.d, z0.d, z0.d[1]
+sqrdmlsh z0.d, z0.d, z0.d[0]
+
+sqrdmlsh z17.b, z21.b, z27.b
+sqrdmlsh z0.b, z0.b, z0.b
+sqrdmlsh z0.h, z0.h, z0.h
+sqrdmlsh z0.s, z0.s, z0.s
+sqrdmlsh z0.d, z0.d, z0.d
+
+sqrdmulh z17.h, z21.h, z5.h[0]
+sqrdmulh z0.h, z0.h, z0.h[5]
+sqrdmulh z0.h, z0.h, z0.h[0]
+
+sqrdmulh z17.s, z21.s, z5.s[0]
+sqrdmulh z0.s, z0.s, z0.s[3]
+sqrdmulh z0.s, z0.s, z0.s[0]
+
+sqrdmulh z17.d, z21.d, z9.d[0]
+sqrdmulh z0.d, z0.d, z0.d[1]
+sqrdmulh z0.d, z0.d, z0.d[0]
+
+sqrdmulh z17.b, z21.b, z27.b
+sqrdmulh z0.b, z0.b, z0.b
+sqrdmulh z0.h, z0.h, z0.h
+sqrdmulh z0.s, z0.s, z0.s
+sqrdmulh z0.d, z0.d, z0.d
+
+sqrshl z17.b, p5/m, z17.b, z21.b
+sqrshl z0.b, p0/m, z0.b, z0.b
+sqrshl z0.h, p0/m, z0.h, z0.h
+sqrshl z0.s, p0/m, z0.s, z0.s
+sqrshl z0.d, p0/m, z0.d, z0.d
+
+sqrshlr z17.b, p5/m, z17.b, z21.b
+sqrshlr z0.b, p0/m, z0.b, z0.b
+sqrshlr z0.h, p0/m, z0.h, z0.h
+sqrshlr z0.s, p0/m, z0.s, z0.s
+sqrshlr z0.d, p0/m, z0.d, z0.d
+
+sqrshrnb z17.b, z21.h, #7
+sqrshrnb z0.b, z0.h, #1
+sqrshrnb z0.b, z0.h, #8
+sqrshrnb z0.h, z0.s, #1
+sqrshrnb z0.h, z0.s, #15
+sqrshrnb z0.h, z0.s, #16
+sqrshrnb z0.s, z0.d, #1
+sqrshrnb z0.s, z0.d, #31
+sqrshrnb z0.s, z0.d, #32
+
+sqrshrnt z17.b, z21.h, #7
+sqrshrnt z0.b, z0.h, #1
+sqrshrnt z0.b, z0.h, #8
+sqrshrnt z0.h, z0.s, #1
+sqrshrnt z0.h, z0.s, #15
+sqrshrnt z0.h, z0.s, #16
+sqrshrnt z0.s, z0.d, #1
+sqrshrnt z0.s, z0.d, #31
+sqrshrnt z0.s, z0.d, #32
+
+sqrshrunb z17.b, z21.h, #7
+sqrshrunb z0.b, z0.h, #1
+sqrshrunb z0.b, z0.h, #8
+sqrshrunb z0.h, z0.s, #1
+sqrshrunb z0.h, z0.s, #15
+sqrshrunb z0.h, z0.s, #16
+sqrshrunb z0.s, z0.d, #1
+sqrshrunb z0.s, z0.d, #31
+sqrshrunb z0.s, z0.d, #32
+
+sqrshrunt z17.b, z21.h, #7
+sqrshrunt z0.b, z0.h, #1
+sqrshrunt z0.b, z0.h, #8
+sqrshrunt z0.h, z0.s, #1
+sqrshrunt z0.h, z0.s, #15
+sqrshrunt z0.h, z0.s, #16
+sqrshrunt z0.s, z0.d, #1
+sqrshrunt z0.s, z0.d, #31
+sqrshrunt z0.s, z0.d, #32
+
+sqshl z17.b, p5/m, z17.b, #1
+sqshl z0.b, p0/m, z0.b, #0
+sqshl z0.b, p0/m, z0.b, #7
+sqshl z0.h, p0/m, z0.h, #0
+sqshl z0.h, p0/m, z0.h, #15
+sqshl z0.s, p0/m, z0.s, #0
+sqshl z0.s, p0/m, z0.s, #31
+sqshl z0.d, p0/m, z0.d, #0
+sqshl z0.d, p0/m, z0.d, #63
+
+sqshl z17.b, p5/m, z17.b, z21.b
+sqshl z0.b, p0/m, z0.b, z0.b
+sqshl z0.h, p0/m, z0.h, z0.h
+sqshl z0.s, p0/m, z0.s, z0.s
+sqshl z0.d, p0/m, z0.d, z0.d
+
+sqshlr z17.b, p5/m, z17.b, z21.b
+sqshlr z0.b, p0/m, z0.b, z0.b
+sqshlr z0.h, p0/m, z0.h, z0.h
+sqshlr z0.s, p0/m, z0.s, z0.s
+sqshlr z0.d, p0/m, z0.d, z0.d
+
+sqshlu z17.b, p5/m, z17.b, #1
+sqshlu z0.b, p0/m, z0.b, #0
+sqshlu z0.b, p0/m, z0.b, #7
+sqshlu z0.h, p0/m, z0.h, #0
+sqshlu z0.h, p0/m, z0.h, #15
+sqshlu z0.s, p0/m, z0.s, #0
+sqshlu z0.s, p0/m, z0.s, #31
+sqshlu z0.d, p0/m, z0.d, #0
+sqshlu z0.d, p0/m, z0.d, #63
+
+sqshrnb z17.b, z21.h, #7
+sqshrnb z0.b, z0.h, #1
+sqshrnb z0.b, z0.h, #8
+sqshrnb z0.h, z0.s, #1
+sqshrnb z0.h, z0.s, #15
+sqshrnb z0.h, z0.s, #16
+sqshrnb z0.s, z0.d, #1
+sqshrnb z0.s, z0.d, #31
+sqshrnb z0.s, z0.d, #32
+
+sqshrnt z17.b, z21.h, #7
+sqshrnt z0.b, z0.h, #1
+sqshrnt z0.b, z0.h, #8
+sqshrnt z0.h, z0.s, #1
+sqshrnt z0.h, z0.s, #15
+sqshrnt z0.h, z0.s, #16
+sqshrnt z0.s, z0.d, #1
+sqshrnt z0.s, z0.d, #31
+sqshrnt z0.s, z0.d, #32
+
+sqshrunb z17.b, z21.h, #7
+sqshrunb z0.b, z0.h, #1
+sqshrunb z0.b, z0.h, #8
+sqshrunb z0.h, z0.s, #1
+sqshrunb z0.h, z0.s, #15
+sqshrunb z0.h, z0.s, #16
+sqshrunb z0.s, z0.d, #1
+sqshrunb z0.s, z0.d, #31
+sqshrunb z0.s, z0.d, #32
+
+sqshrunt z17.b, z21.h, #7
+sqshrunt z0.b, z0.h, #1
+sqshrunt z0.b, z0.h, #8
+sqshrunt z0.h, z0.s, #1
+sqshrunt z0.h, z0.s, #15
+sqshrunt z0.h, z0.s, #16
+sqshrunt z0.s, z0.d, #1
+sqshrunt z0.s, z0.d, #31
+sqshrunt z0.s, z0.d, #32
+
+sqsub z17.b, p5/m, z17.b, z21.b
+sqsub z0.b, p0/m, z0.b, z0.b
+sqsub z0.h, p0/m, z0.h, z0.h
+sqsub z0.s, p0/m, z0.s, z0.s
+sqsub z0.d, p0/m, z0.d, z0.d
+
+sqsubr z17.b, p5/m, z17.b, z21.b
+sqsubr z0.b, p0/m, z0.b, z0.b
+sqsubr z0.h, p0/m, z0.h, z0.h
+sqsubr z0.s, p0/m, z0.s, z0.s
+sqsubr z0.d, p0/m, z0.d, z0.d
+
+sqxtnb z17.b, z21.h
+sqxtnb z0.b, z0.h
+sqxtnb z0.h, z0.s
+sqxtnb z0.s, z0.d
+
+sqxtnt z17.b, z21.h
+sqxtnt z0.b, z0.h
+sqxtnt z0.h, z0.s
+sqxtnt z0.s, z0.d
+
+sqxtunb z17.b, z21.h
+sqxtunb z0.b, z0.h
+sqxtunb z0.h, z0.s
+sqxtunb z0.s, z0.d
+
+sqxtunt z17.b, z21.h
+sqxtunt z0.b, z0.h
+sqxtunt z0.h, z0.s
+sqxtunt z0.s, z0.d
+
+srhadd z17.b, p5/m, z17.b, z21.b
+srhadd z0.b, p0/m, z0.b, z0.b
+srhadd z0.h, p0/m, z0.h, z0.h
+srhadd z0.s, p0/m, z0.s, z0.s
+srhadd z0.d, p0/m, z0.d, z0.d
+
+sri z17.b, z21.b, #7
+sri z0.b, z0.b, #8
+sri z0.b, z0.b, #1
+sri z0.h, z0.h, #16
+sri z0.h, z0.h, #1
+sri z0.s, z0.s, #32
+sri z0.s, z0.s, #1
+sri z0.d, z0.d, #64
+sri z0.d, z0.d, #1
+
+srshl z17.b, p5/m, z17.b, z21.b
+srshl z0.b, p0/m, z0.b, z0.b
+srshl z0.h, p0/m, z0.h, z0.h
+srshl z0.s, p0/m, z0.s, z0.s
+srshl z0.d, p0/m, z0.d, z0.d
+
+srshlr z17.b, p5/m, z17.b, z21.b
+srshlr z0.b, p0/m, z0.b, z0.b
+srshlr z0.h, p0/m, z0.h, z0.h
+srshlr z0.s, p0/m, z0.s, z0.s
+srshlr z0.d, p0/m, z0.d, z0.d
+
+srshr z17.b, p5/m, z17.b, #7
+srshr z0.b, p0/m, z0.b, #8
+srshr z0.b, p0/m, z0.b, #1
+srshr z0.h, p0/m, z0.h, #16
+srshr z0.h, p0/m, z0.h, #1
+srshr z0.s, p0/m, z0.s, #32
+srshr z0.s, p0/m, z0.s, #1
+srshr z0.d, p0/m, z0.d, #64
+srshr z0.d, p0/m, z0.d, #1
+
+srsra z17.b, z21.b, #7
+srsra z0.b, z0.b, #8
+srsra z0.b, z0.b, #1
+srsra z0.h, z0.h, #16
+srsra z0.h, z0.h, #1
+srsra z0.s, z0.s, #32
+srsra z0.s, z0.s, #1
+srsra z0.d, z0.d, #64
+srsra z0.d, z0.d, #1
+
+sshllb z17.h, z21.b, #1
+sshllb z0.h, z0.b, #0
+sshllb z0.h, z0.b, #7
+sshllb z0.s, z0.h, #0
+sshllb z0.s, z0.h, #15
+sshllb z0.d, z0.s, #0
+sshllb z0.d, z0.s, #31
+
+sshllt z17.h, z21.b, #1
+sshllt z0.h, z0.b, #0
+sshllt z0.h, z0.b, #7
+sshllt z0.s, z0.h, #0
+sshllt z0.s, z0.h, #15
+sshllt z0.d, z0.s, #0
+sshllt z0.d, z0.s, #31
+
+ssra z17.b, z21.b, #7
+ssra z0.b, z0.b, #8
+ssra z0.b, z0.b, #1
+ssra z0.h, z0.h, #16
+ssra z0.h, z0.h, #1
+ssra z0.s, z0.s, #32
+ssra z0.s, z0.s, #1
+ssra z0.d, z0.d, #64
+ssra z0.d, z0.d, #1
+
+ssublb z17.h, z21.b, z27.b
+ssublb z0.h, z0.b, z0.b
+ssublb z0.s, z0.h, z0.h
+ssublb z0.d, z0.s, z0.s
+
+ssublbt z17.h, z21.b, z27.b
+ssublbt z0.h, z0.b, z0.b
+ssublbt z0.s, z0.h, z0.h
+ssublbt z0.d, z0.s, z0.s
+
+ssublt z17.h, z21.b, z27.b
+ssublt z0.h, z0.b, z0.b
+ssublt z0.s, z0.h, z0.h
+ssublt z0.d, z0.s, z0.s
+
+ssubltb z17.h, z21.b, z27.b
+ssubltb z0.h, z0.b, z0.b
+ssubltb z0.s, z0.h, z0.h
+ssubltb z0.d, z0.s, z0.s
+
+ssubwb z17.h, z21.h, z27.b
+ssubwb z0.h, z0.h, z0.b
+ssubwb z0.s, z0.s, z0.h
+ssubwb z0.d, z0.d, z0.s
+
+ssubwt z17.h, z21.h, z27.b
+ssubwt z0.h, z0.h, z0.b
+ssubwt z0.s, z0.s, z0.h
+ssubwt z0.d, z0.d, z0.s
+
+stnt1b { z17.s }, p5, [z21.s, x27]
+stnt1b { z0.s }, p0, [z0.s, x0]
+stnt1b { z0.s }, p0, [z0.s]
+stnt1b { z0.s }, p0, [z0.s, xzr]
+stnt1b { z17.d }, p5, [z21.d, x27]
+stnt1b { z0.d }, p0, [z0.d, x0]
+stnt1b { z0.d }, p0, [z0.d]
+stnt1b { z0.d }, p0, [z0.d, xzr]
+
+stnt1d { z17.d }, p5, [z21.d, x27]
+stnt1d { z0.d }, p0, [z0.d, x0]
+stnt1d { z0.d }, p0, [z0.d]
+stnt1d { z0.d }, p0, [z0.d, xzr]
+
+stnt1h { z17.s }, p5, [z21.s, x27]
+stnt1h { z0.s }, p0, [z0.s, x0]
+stnt1h { z0.s }, p0, [z0.s]
+stnt1h { z0.s }, p0, [z0.s, xzr]
+stnt1h { z17.d }, p5, [z21.d, x27]
+stnt1h { z0.d }, p0, [z0.d, x0]
+stnt1h { z0.d }, p0, [z0.d]
+stnt1h { z0.d }, p0, [z0.d, xzr]
+
+stnt1w { z17.s }, p5, [z21.s, x27]
+stnt1w { z0.s }, p0, [z0.s, x0]
+stnt1w { z0.s }, p0, [z0.s]
+stnt1w { z0.s }, p0, [z0.s, xzr]
+stnt1w { z17.d }, p5, [z21.d, x27]
+stnt1w { z0.d }, p0, [z0.d, x0]
+stnt1w { z0.d }, p0, [z0.d]
+stnt1w { z0.d }, p0, [z0.d, xzr]
+
+subhnb z17.b, z21.h, z27.h
+subhnb z0.b, z0.h, z0.h
+subhnb z0.h, z0.s, z0.s
+subhnb z0.s, z0.d, z0.d
+
+subhnt z17.b, z21.h, z27.h
+subhnt z0.b, z0.h, z0.h
+subhnt z0.h, z0.s, z0.s
+subhnt z0.s, z0.d, z0.d
+
+suqadd z17.b, p5/m, z17.b, z21.b
+suqadd z0.b, p0/m, z0.b, z0.b
+suqadd z0.h, p0/m, z0.h, z0.h
+suqadd z0.s, p0/m, z0.s, z0.s
+suqadd z0.d, p0/m, z0.d, z0.d
+
+tbl z17.b, { z21.b, z22.b }, z27.b
+tbl z0.b, { z0.b, z1.b }, z0.b
+tbl z0.h, { z0.h, z1.h }, z0.h
+tbl z0.s, { z0.s, z1.s }, z0.s
+tbl z0.d, { z0.d, z1.d }, z0.d
+tbl z0.b, { z31.b, z0.b }, z0.b
+
+tbx z17.b, z21.b, z27.b
+tbx z0.b, z0.b, z0.b
+tbx z0.h, z0.h, z0.h
+tbx z0.s, z0.s, z0.s
+tbx z0.d, z0.d, z0.d
+
+uaba z17.b, z21.b, z27.b
+uaba z0.b, z0.b, z0.b
+uaba z0.h, z0.h, z0.h
+uaba z0.s, z0.s, z0.s
+uaba z0.d, z0.d, z0.d
+
+uabalb z17.h, z21.b, z27.b
+uabalb z0.h, z0.b, z0.b
+uabalb z0.s, z0.h, z0.h
+uabalb z0.d, z0.s, z0.s
+
+uabalt z17.h, z21.b, z27.b
+uabalt z0.h, z0.b, z0.b
+uabalt z0.s, z0.h, z0.h
+uabalt z0.d, z0.s, z0.s
+
+uabdlb z17.h, z21.b, z27.b
+uabdlb z0.h, z0.b, z0.b
+uabdlb z0.s, z0.h, z0.h
+uabdlb z0.d, z0.s, z0.s
+
+uabdlt z17.h, z21.b, z27.b
+uabdlt z0.h, z0.b, z0.b
+uabdlt z0.s, z0.h, z0.h
+uabdlt z0.d, z0.s, z0.s
+
+uadalp z17.h, p5/m, z21.b
+uadalp z0.h, p0/m, z0.b
+uadalp z0.s, p0/m, z0.h
+uadalp z0.d, p0/m, z0.s
+
+uaddlb z17.h, z21.b, z27.b
+uaddlb z0.h, z0.b, z0.b
+uaddlb z0.s, z0.h, z0.h
+uaddlb z0.d, z0.s, z0.s
+
+uaddlt z17.h, z21.b, z27.b
+uaddlt z0.h, z0.b, z0.b
+uaddlt z0.s, z0.h, z0.h
+uaddlt z0.d, z0.s, z0.s
+
+uaddwb z17.h, z21.h, z27.b
+uaddwb z0.h, z0.h, z0.b
+uaddwb z0.s, z0.s, z0.h
+uaddwb z0.d, z0.d, z0.s
+
+uaddwt z17.h, z21.h, z27.b
+uaddwt z0.h, z0.h, z0.b
+uaddwt z0.s, z0.s, z0.h
+uaddwt z0.d, z0.d, z0.s
+
+uhadd z17.b, p5/m, z17.b, z21.b
+uhadd z0.b, p0/m, z0.b, z0.b
+uhadd z0.h, p0/m, z0.h, z0.h
+uhadd z0.s, p0/m, z0.s, z0.s
+uhadd z0.d, p0/m, z0.d, z0.d
+
+uhsub z17.b, p5/m, z17.b, z21.b
+uhsub z0.b, p0/m, z0.b, z0.b
+uhsub z0.h, p0/m, z0.h, z0.h
+uhsub z0.s, p0/m, z0.s, z0.s
+uhsub z0.d, p0/m, z0.d, z0.d
+
+uhsubr z17.b, p5/m, z17.b, z21.b
+uhsubr z0.b, p0/m, z0.b, z0.b
+uhsubr z0.h, p0/m, z0.h, z0.h
+uhsubr z0.s, p0/m, z0.s, z0.s
+uhsubr z0.d, p0/m, z0.d, z0.d
+
+umaxp z17.b, p5/m, z17.b, z21.b
+umaxp z0.b, p0/m, z0.b, z0.b
+umaxp z0.h, p0/m, z0.h, z0.h
+umaxp z0.s, p0/m, z0.s, z0.s
+umaxp z0.d, p0/m, z0.d, z0.d
+
+uminp z17.b, p5/m, z17.b, z21.b
+uminp z0.b, p0/m, z0.b, z0.b
+uminp z0.h, p0/m, z0.h, z0.h
+uminp z0.s, p0/m, z0.s, z0.s
+uminp z0.d, p0/m, z0.d, z0.d
+
+umlalb z17.s, z21.h, z5.h[0]
+umlalb z0.s, z0.h, z0.h[5]
+umlalb z0.s, z0.h, z0.h[0]
+
+umlalb z17.d, z21.s, z9.s[0]
+umlalb z0.d, z0.s, z0.s[3]
+umlalb z0.d, z0.s, z0.s[0]
+
+umlalb z17.h, z21.b, z27.b
+umlalb z0.h, z0.b, z0.b
+umlalb z0.s, z0.h, z0.h
+umlalb z0.d, z0.s, z0.s
+
+umlalt z17.s, z21.h, z5.h[0]
+umlalt z0.s, z0.h, z0.h[5]
+umlalt z0.s, z0.h, z0.h[0]
+
+umlalt z17.d, z21.s, z9.s[0]
+umlalt z0.d, z0.s, z0.s[3]
+umlalt z0.d, z0.s, z0.s[0]
+
+umlalt z17.h, z21.b, z27.b
+umlalt z0.h, z0.b, z0.b
+umlalt z0.s, z0.h, z0.h
+umlalt z0.d, z0.s, z0.s
+
+umlslb z17.s, z21.h, z5.h[0]
+umlslb z0.s, z0.h, z0.h[5]
+umlslb z0.s, z0.h, z0.h[0]
+
+umlslb z17.d, z21.s, z9.s[0]
+umlslb z0.d, z0.s, z0.s[3]
+umlslb z0.d, z0.s, z0.s[0]
+
+umlslb z17.h, z21.b, z27.b
+umlslb z0.h, z0.b, z0.b
+umlslb z0.s, z0.h, z0.h
+umlslb z0.d, z0.s, z0.s
+
+umlslt z17.s, z21.h, z5.h[0]
+umlslt z0.s, z0.h, z0.h[5]
+umlslt z0.s, z0.h, z0.h[0]
+
+umlslt z17.d, z21.s, z9.s[0]
+umlslt z0.d, z0.s, z0.s[3]
+umlslt z0.d, z0.s, z0.s[0]
+
+umlslt z17.h, z21.b, z27.b
+umlslt z0.h, z0.b, z0.b
+umlslt z0.s, z0.h, z0.h
+umlslt z0.d, z0.s, z0.s
+
+umulh z17.b, z21.b, z27.b
+umulh z0.b, z0.b, z0.b
+umulh z0.h, z0.h, z0.h
+umulh z0.s, z0.s, z0.s
+umulh z0.d, z0.d, z0.d
+
+umullb z17.s, z21.h, z5.h[0]
+umullb z0.s, z0.h, z0.h[5]
+umullb z0.s, z0.h, z0.h[0]
+
+umullb z17.d, z21.s, z9.s[0]
+umullb z0.d, z0.s, z0.s[3]
+umullb z0.d, z0.s, z0.s[0]
+
+umullb z17.h, z21.b, z27.b
+umullb z0.h, z0.b, z0.b
+umullb z0.s, z0.h, z0.h
+umullb z0.d, z0.s, z0.s
+
+umullt z17.s, z21.h, z5.h[0]
+umullt z0.s, z0.h, z0.h[5]
+umullt z0.s, z0.h, z0.h[0]
+
+umullt z17.d, z21.s, z9.s[0]
+umullt z0.d, z0.s, z0.s[3]
+umullt z0.d, z0.s, z0.s[0]
+
+umullt z17.h, z21.b, z27.b
+umullt z0.h, z0.b, z0.b
+umullt z0.s, z0.h, z0.h
+umullt z0.d, z0.s, z0.s
+
+uqadd z17.b, p5/m, z17.b, z21.b
+uqadd z0.b, p0/m, z0.b, z0.b
+uqadd z0.h, p0/m, z0.h, z0.h
+uqadd z0.s, p0/m, z0.s, z0.s
+uqadd z0.d, p0/m, z0.d, z0.d
+
+uqrshl z17.b, p5/m, z17.b, z21.b
+uqrshl z0.b, p0/m, z0.b, z0.b
+uqrshl z0.h, p0/m, z0.h, z0.h
+uqrshl z0.s, p0/m, z0.s, z0.s
+uqrshl z0.d, p0/m, z0.d, z0.d
+
+uqrshlr z17.b, p5/m, z17.b, z21.b
+uqrshlr z0.b, p0/m, z0.b, z0.b
+uqrshlr z0.h, p0/m, z0.h, z0.h
+uqrshlr z0.s, p0/m, z0.s, z0.s
+uqrshlr z0.d, p0/m, z0.d, z0.d
+
+uqrshrnb z17.b, z21.h, #7
+uqrshrnb z0.b, z0.h, #1
+uqrshrnb z0.b, z0.h, #8
+uqrshrnb z0.h, z0.s, #1
+uqrshrnb z0.h, z0.s, #15
+uqrshrnb z0.h, z0.s, #16
+uqrshrnb z0.s, z0.d, #1
+uqrshrnb z0.s, z0.d, #31
+uqrshrnb z0.s, z0.d, #32
+
+uqrshrnt z17.b, z21.h, #7
+uqrshrnt z0.b, z0.h, #1
+uqrshrnt z0.b, z0.h, #8
+uqrshrnt z0.h, z0.s, #1
+uqrshrnt z0.h, z0.s, #15
+uqrshrnt z0.h, z0.s, #16
+uqrshrnt z0.s, z0.d, #1
+uqrshrnt z0.s, z0.d, #31
+uqrshrnt z0.s, z0.d, #32
+
+uqshl z17.b, p5/m, z17.b, #1
+uqshl z0.b, p0/m, z0.b, #0
+uqshl z0.b, p0/m, z0.b, #7
+uqshl z0.h, p0/m, z0.h, #0
+uqshl z0.h, p0/m, z0.h, #15
+uqshl z0.s, p0/m, z0.s, #0
+uqshl z0.s, p0/m, z0.s, #31
+uqshl z0.d, p0/m, z0.d, #0
+uqshl z0.d, p0/m, z0.d, #63
+
+uqshl z17.b, p5/m, z17.b, z21.b
+uqshl z0.b, p0/m, z0.b, z0.b
+uqshl z0.h, p0/m, z0.h, z0.h
+uqshl z0.s, p0/m, z0.s, z0.s
+uqshl z0.d, p0/m, z0.d, z0.d
+
+uqshlr z17.b, p5/m, z17.b, z21.b
+uqshlr z0.b, p0/m, z0.b, z0.b
+uqshlr z0.h, p0/m, z0.h, z0.h
+uqshlr z0.s, p0/m, z0.s, z0.s
+uqshlr z0.d, p0/m, z0.d, z0.d
+
+uqshrnb z17.b, z21.h, #7
+uqshrnb z0.b, z0.h, #1
+uqshrnb z0.b, z0.h, #8
+uqshrnb z0.h, z0.s, #1
+uqshrnb z0.h, z0.s, #15
+uqshrnb z0.h, z0.s, #16
+uqshrnb z0.s, z0.d, #1
+uqshrnb z0.s, z0.d, #31
+uqshrnb z0.s, z0.d, #32
+
+uqshrnt z17.b, z21.h, #7
+uqshrnt z0.b, z0.h, #1
+uqshrnt z0.b, z0.h, #8
+uqshrnt z0.h, z0.s, #1
+uqshrnt z0.h, z0.s, #15
+uqshrnt z0.h, z0.s, #16
+uqshrnt z0.s, z0.d, #1
+uqshrnt z0.s, z0.d, #31
+uqshrnt z0.s, z0.d, #32
+
+uqsub z17.b, p5/m, z17.b, z21.b
+uqsub z0.b, p0/m, z0.b, z0.b
+uqsub z0.h, p0/m, z0.h, z0.h
+uqsub z0.s, p0/m, z0.s, z0.s
+uqsub z0.d, p0/m, z0.d, z0.d
+
+uqsubr z17.b, p5/m, z17.b, z21.b
+uqsubr z0.b, p0/m, z0.b, z0.b
+uqsubr z0.h, p0/m, z0.h, z0.h
+uqsubr z0.s, p0/m, z0.s, z0.s
+uqsubr z0.d, p0/m, z0.d, z0.d
+
+uqxtnb z17.b, z21.h
+uqxtnb z0.b, z0.h
+uqxtnb z0.h, z0.s
+uqxtnb z0.s, z0.d
+
+uqxtnt z17.b, z21.h
+uqxtnt z0.b, z0.h
+uqxtnt z0.h, z0.s
+uqxtnt z0.s, z0.d
+
+urecpe z17.s, p5/m, z21.s
+urecpe z0.s, p0/m, z0.s
+
+urhadd z17.b, p5/m, z17.b, z21.b
+urhadd z0.b, p0/m, z0.b, z0.b
+urhadd z0.h, p0/m, z0.h, z0.h
+urhadd z0.s, p0/m, z0.s, z0.s
+urhadd z0.d, p0/m, z0.d, z0.d
+
+urshl z17.b, p5/m, z17.b, z21.b
+urshl z0.b, p0/m, z0.b, z0.b
+urshl z0.h, p0/m, z0.h, z0.h
+urshl z0.s, p0/m, z0.s, z0.s
+urshl z0.d, p0/m, z0.d, z0.d
+
+urshlr z17.b, p5/m, z17.b, z21.b
+urshlr z0.b, p0/m, z0.b, z0.b
+urshlr z0.h, p0/m, z0.h, z0.h
+urshlr z0.s, p0/m, z0.s, z0.s
+urshlr z0.d, p0/m, z0.d, z0.d
+
+urshr z17.b, p5/m, z17.b, #7
+urshr z0.b, p0/m, z0.b, #8
+urshr z0.b, p0/m, z0.b, #1
+urshr z0.h, p0/m, z0.h, #16
+urshr z0.h, p0/m, z0.h, #1
+urshr z0.s, p0/m, z0.s, #32
+urshr z0.s, p0/m, z0.s, #1
+urshr z0.d, p0/m, z0.d, #64
+urshr z0.d, p0/m, z0.d, #1
+
+ursqrte z17.s, p5/m, z21.s
+ursqrte z0.s, p0/m, z0.s
+
+ursra z17.b, z21.b, #7
+ursra z0.b, z0.b, #8
+ursra z0.b, z0.b, #1
+ursra z0.h, z0.h, #16
+ursra z0.h, z0.h, #1
+ursra z0.s, z0.s, #32
+ursra z0.s, z0.s, #1
+ursra z0.d, z0.d, #64
+ursra z0.d, z0.d, #1
+
+ushllb z17.h, z21.b, #1
+ushllb z0.h, z0.b, #0
+ushllb z0.h, z0.b, #7
+ushllb z0.s, z0.h, #0
+ushllb z0.s, z0.h, #15
+ushllb z0.d, z0.s, #0
+ushllb z0.d, z0.s, #31
+
+ushllt z17.h, z21.b, #1
+ushllt z0.h, z0.b, #0
+ushllt z0.h, z0.b, #7
+ushllt z0.s, z0.h, #0
+ushllt z0.s, z0.h, #15
+ushllt z0.d, z0.s, #0
+ushllt z0.d, z0.s, #31
+
+usqadd z17.b, p5/m, z17.b, z21.b
+usqadd z0.b, p0/m, z0.b, z0.b
+usqadd z0.h, p0/m, z0.h, z0.h
+usqadd z0.s, p0/m, z0.s, z0.s
+usqadd z0.d, p0/m, z0.d, z0.d
+
+usra z17.b, z21.b, #7
+usra z0.b, z0.b, #8
+usra z0.b, z0.b, #1
+usra z0.h, z0.h, #16
+usra z0.h, z0.h, #1
+usra z0.s, z0.s, #32
+usra z0.s, z0.s, #1
+usra z0.d, z0.d, #64
+usra z0.d, z0.d, #1
+
+usublb z17.h, z21.b, z27.b
+usublb z0.h, z0.b, z0.b
+usublb z0.s, z0.h, z0.h
+usublb z0.d, z0.s, z0.s
+
+usublt z17.h, z21.b, z27.b
+usublt z0.h, z0.b, z0.b
+usublt z0.s, z0.h, z0.h
+usublt z0.d, z0.s, z0.s
+
+usubwb z17.h, z21.h, z27.b
+usubwb z0.h, z0.h, z0.b
+usubwb z0.s, z0.s, z0.h
+usubwb z0.d, z0.d, z0.s
+
+usubwt z17.h, z21.h, z27.b
+usubwt z0.h, z0.h, z0.b
+usubwt z0.s, z0.s, z0.h
+usubwt z0.d, z0.d, z0.s
+
+whilege p9.b, x21, x27
+whilege p0.b, x0, x0
+whilege p0.b, xzr, x0
+whilege p0.b, x0, xzr
+whilege p0.h, x0, x0
+whilege p0.s, x0, x0
+whilege p0.d, x0, x0
+
+whilege p9.b, w21, w27
+whilege p0.b, w0, w0
+whilege p0.b, wzr, w0
+whilege p0.b, w0, wzr
+whilege p0.h, w0, w0
+whilege p0.s, w0, w0
+whilege p0.d, w0, w0
+
+whilegt p9.b, x21, x27
+whilegt p0.b, x0, x0
+whilegt p0.b, xzr, x0
+whilegt p0.b, x0, xzr
+whilegt p0.h, x0, x0
+whilegt p0.s, x0, x0
+whilegt p0.d, x0, x0
+
+whilegt p9.b, w21, w27
+whilegt p0.b, w0, w0
+whilegt p0.b, wzr, w0
+whilegt p0.b, w0, wzr
+whilegt p0.h, w0, w0
+whilegt p0.s, w0, w0
+whilegt p0.d, w0, w0
+
+whilehi p9.b, x21, x27
+whilehi p0.b, x0, x0
+whilehi p0.b, xzr, x0
+whilehi p0.b, x0, xzr
+whilehi p0.h, x0, x0
+whilehi p0.s, x0, x0
+whilehi p0.d, x0, x0
+
+whilehi p9.b, w21, w27
+whilehi p0.b, w0, w0
+whilehi p0.b, wzr, w0
+whilehi p0.b, w0, wzr
+whilehi p0.h, w0, w0
+whilehi p0.s, w0, w0
+whilehi p0.d, w0, w0
+
+whilehs p9.b, x21, x27
+whilehs p0.b, x0, x0
+whilehs p0.b, xzr, x0
+whilehs p0.b, x0, xzr
+whilehs p0.h, x0, x0
+whilehs p0.s, x0, x0
+whilehs p0.d, x0, x0
+
+whilehs p9.b, w21, w27
+whilehs p0.b, w0, w0
+whilehs p0.b, wzr, w0
+whilehs p0.b, w0, wzr
+whilehs p0.h, w0, w0
+whilehs p0.s, w0, w0
+whilehs p0.d, w0, w0
+
+whilerw p9.b, x21, x27
+whilerw p0.b, x0, x0
+whilerw p0.h, x0, x0
+whilerw p0.s, x0, x0
+whilerw p0.d, x0, x0
+
+whilewr p9.b, x21, x27
+whilewr p0.b, x0, x0
+whilewr p0.h, x0, x0
+whilewr p0.s, x0, x0
+whilewr p0.d, x0, x0
+
+xar z17.b, z17.b, z21.b, #7
+xar z0.b, z0.b, z0.b, #8
+xar z0.b, z0.b, z0.b, #1
+xar z0.h, z0.h, z0.h, #16
+xar z0.h, z0.h, z0.h, #1
+xar z0.s, z0.s, z0.s, #32
+xar z0.s, z0.s, z0.s, #1
+xar z0.d, z0.d, z0.d, #64
+xar z0.d, z0.d, z0.d, #1
author	Matthew Malcomson <matthew.malcomson@arm.com>	2019-05-09 10:29:29 +0100
committer	Matthew Malcomson <matthew.malcomson@arm.com>	2019-05-09 10:29:51 +0100
commit	e111c7d1eb8404f29c45f3aa5dbc531062ebbd73 (patch)
tree	6e85950c386a282064ae0374411d9c34e03c40f0 /gas
parent	42e6288f9f9d7dfe560d2bed1fb5e7f27ac3256f (diff)
download	gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.zip gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.tar.gz gdb-e111c7d1eb8404f29c45f3aa5dbc531062ebbd73.tar.bz2