[PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt

gas/ChangeLog:
2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (enum operand_parse_code): Add new operand.
	(parse_operands): Handle new operand.
	(do_neon_cvt_1): Handle MVE variants.
	(do_neon_cvttb_1): Likewise.
	(insns): Accept MVE variants.
	* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
	* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
	* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
	* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
	* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
	* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
	* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
	* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
	* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
	* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
	* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
	* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
	* testsuite/gas/arm/mve-vcvt-bad.d: New test.
	* testsuite/gas/arm/mve-vcvt-bad.l: New test.
	* testsuite/gas/arm/mve-vcvt-bad.s: New test.

17 files changed, 831 insertions, 19 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 6582744..eed8e52 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,28 @@
 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
+	* config/tc-arm.c (enum operand_parse_code): Add new operand.
+	(parse_operands): Handle new operand.
+	(do_neon_cvt_1): Handle MVE variants.
+	(do_neon_cvttb_1): Likewise.
+	(insns): Accept MVE variants.
+	* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
+	* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
+	* testsuite/gas/arm/mve-vcvt-bad.d: New test.
+	* testsuite/gas/arm/mve-vcvt-bad.l: New test.
+	* testsuite/gas/arm/mve-vcvt-bad.s: New test.
+
+2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
 	* config/tc-arm.c (struct arm_it): Make immisreg field larger to hold
 	type of register.
 	(enum shift_kind): Add SHIFT_UXTW shift kind.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 717f1b1..4e61eb5 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6776,6 +6776,7 @@ enum operand_parse_code
   OP_RNQ,	/* Neon quad precision register */
   OP_RNQMQ,	/* Neon quad or MVE vector register.  */
   OP_RVSD,	/* VFP single or double precision register */
+  OP_RVSDMQ,	/* VFP single, double precision or MVE vector register.  */
   OP_RNSD,      /* Neon single or double precision register */
   OP_RNDQ,      /* Neon double or quad precision register */
   OP_RNDQMQ,     /* Neon double, quad or MVE vector register.  */
@@ -7048,7 +7049,6 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
       if (op_parse_code >= OP_FIRST_OPTIONAL)
 	{
 	  /* Remember where we are in case we need to backtrack.  */
-	  gas_assert (!backtrack_pos);
 	  backtrack_pos = str;
 	  backtrack_error = inst.error;
 	  backtrack_index = i;
@@ -7116,6 +7116,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
 	try_rndq:
 	case OP_oRNDQ:
 	case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
+	case OP_RVSDMQ:
+	  po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
+	  break;
+	try_rvsd:
 	case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
 	case OP_oRNSDQ:
 	case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
@@ -17032,15 +17036,64 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
 
   switch (rs)
     {
-    case NS_DDI:
     case NS_QQI:
+      if (mode == neon_cvt_mode_z
+	  && (flavour == neon_cvt_flavour_f16_s16
+	      || flavour == neon_cvt_flavour_f16_u16
+	      || flavour == neon_cvt_flavour_s16_f16
+	      || flavour == neon_cvt_flavour_u16_f16
+	      || flavour == neon_cvt_flavour_f32_u32
+	      || flavour == neon_cvt_flavour_f32_s32
+	      || flavour == neon_cvt_flavour_s32_f32
+	      || flavour == neon_cvt_flavour_u32_f32))
+	{
+	  if (check_simd_pred_availability (1, NEON_CHECK_CC | NEON_CHECK_ARCH))
+	    return;
+	}
+      else if (mode == neon_cvt_mode_n)
+	{
+	  /* We are dealing with vcvt with the 'ne' condition.  */
+	  inst.cond = 0x1;
+	  inst.instruction = N_MNEM_vcvt;
+	  do_neon_cvt_1 (neon_cvt_mode_z);
+	  return;
+	}
+      /* fall through.  */
+    case NS_DDI:
       {
 	unsigned immbits;
 	unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
 			     0x0000100, 0x1000100, 0x0, 0x1000000};
 
-	if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
-	  return;
+	if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+	    && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+	    return;
+
+	if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+	  {
+	    constraint (inst.operands[2].present && inst.operands[2].imm == 0,
+			_("immediate value out of range"));
+	    switch (flavour)
+	      {
+		case neon_cvt_flavour_f16_s16:
+		case neon_cvt_flavour_f16_u16:
+		case neon_cvt_flavour_s16_f16:
+		case neon_cvt_flavour_u16_f16:
+		  constraint (inst.operands[2].imm > 16,
+			      _("immediate value out of range"));
+		  break;
+		case neon_cvt_flavour_f32_u32:
+		case neon_cvt_flavour_f32_s32:
+		case neon_cvt_flavour_s32_f32:
+		case neon_cvt_flavour_u32_f32:
+		  constraint (inst.operands[2].imm > 32,
+			      _("immediate value out of range"));
+		  break;
+		default:
+		  inst.error = BAD_FPU;
+		  return;
+	      }
+	  }
 
 	/* Fixed-point conversion with #0 immediate is encoded as an
 	   integer conversion.  */
@@ -17073,14 +17126,40 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
       }
       break;
 
-    case NS_DD:
     case NS_QQ:
+      if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
+	   || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
+	  && (flavour == neon_cvt_flavour_s16_f16
+	      || flavour == neon_cvt_flavour_u16_f16
+	      || flavour == neon_cvt_flavour_s32_f32
+	      || flavour == neon_cvt_flavour_u32_f32))
+	{
+	  if (check_simd_pred_availability (1,
+					    NEON_CHECK_CC | NEON_CHECK_ARCH8))
+	    return;
+	}
+      else if (mode == neon_cvt_mode_z
+	       && (flavour == neon_cvt_flavour_f16_s16
+		   || flavour == neon_cvt_flavour_f16_u16
+		   || flavour == neon_cvt_flavour_s16_f16
+		   || flavour == neon_cvt_flavour_u16_f16
+		   || flavour == neon_cvt_flavour_f32_u32
+		   || flavour == neon_cvt_flavour_f32_s32
+		   || flavour == neon_cvt_flavour_s32_f32
+		   || flavour == neon_cvt_flavour_u32_f32))
+	{
+	  if (check_simd_pred_availability (1,
+					    NEON_CHECK_CC | NEON_CHECK_ARCH))
+	    return;
+	}
+      /* fall through.  */
+    case NS_DD:
       if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
 	{
-	  NEON_ENCODE (FLOAT, inst);
-	  set_pred_insn_type (OUTSIDE_PRED_INSN);
 
-	  if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+	  NEON_ENCODE (FLOAT, inst);
+	  if (check_simd_pred_availability (1,
+					    NEON_CHECK_CC | NEON_CHECK_ARCH8))
 	    return;
 
 	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
@@ -17110,8 +17189,11 @@ do_neon_cvt_1 (enum neon_cvt_mode mode)
 
 	    NEON_ENCODE (INTEGER, inst);
 
-	    if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
-	      return;
+	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
+	    {
+	      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
+		return;
+	    }
 
 	    if (flavour != neon_cvt_flavour_invalid)
 	      inst.instruction |= enctab[flavour];
@@ -17230,10 +17312,51 @@ static void
 do_neon_cvttb_1 (bfd_boolean t)
 {
   enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
-					  NS_DF, NS_DH, NS_NULL);
+					  NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
 
   if (rs == NS_NULL)
     return;
+  else if (rs == NS_QQ || rs == NS_QQI)
+    {
+      int single_to_half = 0;
+      if (check_simd_pred_availability (1, NEON_CHECK_ARCH))
+	return;
+
+      enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
+
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
+	  && (flavour ==  neon_cvt_flavour_u16_f16
+	      || flavour ==  neon_cvt_flavour_s16_f16
+	      || flavour ==  neon_cvt_flavour_f16_s16
+	      || flavour ==  neon_cvt_flavour_f16_u16
+	      || flavour ==  neon_cvt_flavour_u32_f32
+	      || flavour ==  neon_cvt_flavour_s32_f32
+	      || flavour ==  neon_cvt_flavour_f32_s32
+	      || flavour ==  neon_cvt_flavour_f32_u32))
+	{
+	  inst.cond = 0xf;
+	  inst.instruction = N_MNEM_vcvt;
+	  set_pred_insn_type (INSIDE_VPT_INSN);
+	  do_neon_cvt_1 (neon_cvt_mode_z);
+	  return;
+	}
+      else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
+	single_to_half = 1;
+      else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
+	{
+	  first_error (BAD_FPU);
+	  return;
+	}
+
+      inst.instruction = 0xee3f0e01;
+      inst.instruction |= single_to_half << 28;
+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+      inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
+      inst.instruction |= t << 12;
+      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
+      inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
+      inst.is_neon = 1;
+    }
   else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
     {
       inst.error = NULL;
@@ -21848,10 +21971,6 @@ static const struct asm_opcode insns[] =
   nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD),		vsel),
   nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ),	vmaxnm),
   nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ),	vmaxnm),
-  nUF(vcvta,  _vcvta,  2, (RNSDQ, oRNSDQ),		neon_cvta),
-  nUF(vcvtn,  _vcvta,  2, (RNSDQ, oRNSDQ),		neon_cvtn),
-  nUF(vcvtp,  _vcvta,  2, (RNSDQ, oRNSDQ),		neon_cvtp),
-  nUF(vcvtm,  _vcvta,  2, (RNSDQ, oRNSDQ),		neon_cvtm),
   nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ),		vrintr),
   nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ),		vrintz),
   nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ),		vrintx),
@@ -22512,10 +22631,10 @@ static const struct asm_opcode insns[] =
  NCE(vstmia,    c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
  NCE(vstmdb,    d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
 
- nCEF(vcvt,     _vcvt,   3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
+ mnCEF(vcvt,     _vcvt,   3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
  nCEF(vcvtr,    _vcvt,   2, (RNSDQ, RNSDQ), neon_cvtr),
- NCEF(vcvtb,	eb20a40, 2, (RVSD, RVSD), neon_cvtb),
- NCEF(vcvtt,	eb20a40, 2, (RVSD, RVSD), neon_cvtt),
+ MNCEF(vcvtb,	eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
+ MNCEF(vcvtt,	eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
 
 
   /* NOTE: All VMOV encoding is special-cased!  */
@@ -23275,7 +23394,14 @@ static const struct asm_opcode insns[] =
  MNCEF(vabs,  1b10300,	2, (RNSDQMQ, RNSDQMQ),	neon_abs_neg),
  MNCEF(vneg,  1b10380,	2, (RNSDQMQ, RNSDQMQ),	neon_abs_neg),
 
-#undef ARM_VARIANT
+#undef  ARM_VARIANT
+#define ARM_VARIANT    & fpu_vfp_ext_armv8xd
+ mnUF(vcvta,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvta),
+ mnUF(vcvtp,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvtp),
+ mnUF(vcvtn,  _vcvta,  3, (RNSDQMQ, oRNSDQMQ, oI32z),	neon_cvtn),
+ mnUF(vcvtm,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvtm),
+
+#undef	ARM_VARIANT
 #define ARM_VARIANT & fpu_neon_ext_v1
  mnUF(vabd,      _vabd,    3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
  mnUF(vabdl,     _vabdl,	  3, (RNQMQ, RNDMQ, RNDMQ),   neon_dyadic_long),
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.d b/gas/testsuite/gas/arm/mve-vcvt-bad-1.d
new file mode 100644
index 0000000..15ba724
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.d
@@ -0,0 +1,6 @@
+#name: bad MVE VCVT (between floating-point and fixed-point) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-1.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.l b/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
new file mode 100644
index 0000000..4c727d3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.l
@@ -0,0 +1,75 @@
+[^:]*: Assembler messages:
+[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:13: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:15: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:16: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:17: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:18: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:19: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:21: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:23: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:24: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:25: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:26: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:27: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:28: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
+[^:]*:31: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
+[^:]*:32: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
+[^:]*:34: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:35: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:37: Error: syntax error -- `vcvteq.f32.u32 q0,q1,#1'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vcvt.f32.u32 q0,q1,#1'
+[^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f32.u32 q0,q1,#1'
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-1.s b/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
new file mode 100644
index 0000000..401014a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-1.s
@@ -0,0 +1,40 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+it \cond
+vcvt\size q0, q1, #1
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+vcvt.f16.s16 q0, q1, #0
+vcvt.s16.f16 q0, q1, #0
+vcvt.f16.u16 q0, q1, #0
+vcvt.u16.f16 q0, q1, #0
+vcvt.f16.s16 q0, q1, #17
+vcvt.s16.f16 q0, q1, #17
+vcvt.f16.u16 q0, q1, #17
+vcvt.u16.f16 q0, q1, #17
+vcvt.f32.s32 q0, q1, #0
+vcvt.s32.f32 q0, q1, #0
+vcvt.f32.u32 q0, q1, #0
+vcvt.u32.f32 q0, q1, #0
+vcvt.f32.s32 q0, q1, #33
+vcvt.s32.f32 q0, q1, #33
+vcvt.f32.u32 q0, q1, #33
+vcvt.u32.f32 q0, q1, #33
+cond
+vcvt.f64.u64 q0, q1, #1
+vcvt.u64.f64 q0, q1, #1
+vcvt.f64.s64 q0, q1, #1
+vcvt.s64.f64 q0, q1, #1
+it eq
+vcvteq.f32.u32 q0, q1, #1
+vcvteq.f32.u32 q0, q1, #1
+vpst
+vcvteq.f32.u32 q0, q1, #1
+vpst
+vcvt.f32.u32 q0, q1, #1
+vcvtt.f32.u32 q0, q1, #1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.d b/gas/testsuite/gas/arm/mve-vcvt-bad-2.d
new file mode 100644
index 0000000..eb98daa
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (between floating-point and integer) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-2.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.l b/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
new file mode 100644
index 0000000..a608fd4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.l
@@ -0,0 +1,58 @@
+[^:]*: Assembler messages:
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1'
+[^:]*:14: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1'
+[^:]*:18: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:19: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:21: Error: syntax error -- `vcvteq.f32.s32 q0,q1'
+[^:]*:23: Error: instruction missing MVE vector predication code -- `vcvt.f32.s32 q0,q1'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f32.s32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-2.s b/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
new file mode 100644
index 0000000..e3dc08b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-2.s
@@ -0,0 +1,24 @@
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.s16, .s16.f16, .f16.u16, .u16.f16, .f32.s32, .s32.f32, .f32.u32, .u32.f32
+it \cond
+vcvt\size q0, q1
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvt.u64.f64 q0, q1
+vcvt.f64.u64 q0, q1
+vcvt.s64.f64 q0, q1
+vcvt.f64.s64 q0, q1
+it eq
+vcvteq.f32.s32 q0, q1
+vcvteq.f32.s32 q0, q1
+vpst
+vcvteq.f32.s32 q0, q1
+vpst
+vcvt.f32.s32 q0, q1
+vcvtt.f32.s32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.d b/gas/testsuite/gas/arm/mve-vcvt-bad-3.d
new file mode 100644
index 0000000..b85a41e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (between single and half precision floating-point) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-3.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.l b/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
new file mode 100644
index 0000000..c51fd43
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.l
@@ -0,0 +1,39 @@
+[^:]*: Assembler messages:
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvt.f64.f16 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvt.f64.f32 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vcvt.f16.f64 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vcvt.f32.f64 q0,q1'
+[^:]*:20: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:21: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:23: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
+[^:]*:26: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
+[^:]*:28: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:29: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:31: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:32: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtbt.f16.f32 q0,q1'
+[^:]*:34: Error: instruction missing MVE vector predication code -- `vcvtb.f16.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-3.s b/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
new file mode 100644
index 0000000..6552cd2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-3.s
@@ -0,0 +1,34 @@
+.macro cond
+.irp top, t, b
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .f16.f32, .f32.f16
+it \cond
+vcvt\top\size q0, q1
+.endr
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvt.f64.f16 q0, q1
+vcvt.f64.f32 q0, q1
+vcvt.f16.f64 q0, q1
+vcvt.f32.f64 q0, q1
+it eq
+vcvtteq.f16.f32 q0, q1
+vcvtteq.f16.f32 q0, q1
+vpst
+vcvtteq.f16.f32 q0, q1
+vcvttt.f16.f32 q0, q1
+vpst
+vcvtt.f16.f32 q0, q1
+it eq
+vcvtbeq.f16.f32 q0, q1
+vcvtbeq.f16.f32 q0, q1
+vpst
+vcvtbeq.f16.f32 q0, q1
+vcvtbt.f16.f32 q0, q1
+vpst
+vcvtb.f16.f32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.d b/gas/testsuite/gas/arm/mve-vcvt-bad-4.d
new file mode 100644
index 0000000..2b46152
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.d
@@ -0,0 +1,5 @@
+#name: bad MVE VCVT (from floating-point to integer) instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad-4.l
+
+.*: +file format .*arm.*
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.l b/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
new file mode 100644
index 0000000..36d423a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.l
@@ -0,0 +1,133 @@
+[^:]*: Assembler messages:
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:15: Error: bad type in SIMD instruction -- `vcvta.s64.f64 q0,q1'
+[^:]*:16: Error: bad type in SIMD instruction -- `vcvta.u64.f64 q0,q1'
+[^:]*:17: Error: bad type in SIMD instruction -- `vcvta.f64.s64 q0,q1'
+[^:]*:18: Error: bad type in SIMD instruction -- `vcvta.f64.u64 q0,q1'
+[^:]*:19: Error: bad type in SIMD instruction -- `vcvtn.s64.f64 q0,q1'
+[^:]*:20: Error: bad type in SIMD instruction -- `vcvtn.u64.f64 q0,q1'
+[^:]*:21: Error: bad type in SIMD instruction -- `vcvtn.f64.s64 q0,q1'
+[^:]*:22: Error: bad type in SIMD instruction -- `vcvtn.f64.u64 q0,q1'
+[^:]*:23: Error: bad type in SIMD instruction -- `vcvtp.s64.f64 q0,q1'
+[^:]*:24: Error: bad type in SIMD instruction -- `vcvtp.u64.f64 q0,q1'
+[^:]*:25: Error: bad type in SIMD instruction -- `vcvtp.f64.s64 q0,q1'
+[^:]*:26: Error: bad type in SIMD instruction -- `vcvtp.f64.u64 q0,q1'
+[^:]*:27: Error: bad type in SIMD instruction -- `vcvtm.s64.f64 q0,q1'
+[^:]*:28: Error: bad type in SIMD instruction -- `vcvtm.u64.f64 q0,q1'
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvtm.f64.s64 q0,q1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvtm.f64.u64 q0,q1'
+[^:]*:32: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:33: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:35: Error: syntax error -- `vcvtaeq.s32.f32 q0,q1'
+[^:]*:36: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtat.s32.f32 q0,q1'
+[^:]*:38: Error: instruction missing MVE vector predication code -- `vcvta.s32.f32 q0,q1'
+[^:]*:40: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:41: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:43: Error: syntax error -- `vcvtneq.s32.f32 q0,q1'
+[^:]*:44: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtnt.s32.f32 q0,q1'
+[^:]*:46: Error: instruction missing MVE vector predication code -- `vcvtn.s32.f32 q0,q1'
+[^:]*:48: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:49: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:51: Error: syntax error -- `vcvtpeq.s32.f32 q0,q1'
+[^:]*:52: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtpt.s32.f32 q0,q1'
+[^:]*:54: Error: instruction missing MVE vector predication code -- `vcvtp.s32.f32 q0,q1'
+[^:]*:56: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:57: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:59: Error: syntax error -- `vcvtmeq.s32.f32 q0,q1'
+[^:]*:60: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtmt.s32.f32 q0,q1'
+[^:]*:62: Error: instruction missing MVE vector predication code -- `vcvtm.s32.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad-4.s b/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
new file mode 100644
index 0000000..cffb6e4
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad-4.s
@@ -0,0 +1,62 @@
+.macro cond
+.irp round, a, n, p, m
+.irp cond, eq, ne, gt, ge, lt, le
+.irp size, .s16.f16, .u16.f16, .s32.f32, .u32.f32
+it \cond
+vcvt\round\size q0, q1
+.endr
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vcvta.s64.f64 q0, q1
+vcvta.u64.f64 q0, q1
+vcvta.f64.s64 q0, q1
+vcvta.f64.u64 q0, q1
+vcvtn.s64.f64 q0, q1
+vcvtn.u64.f64 q0, q1
+vcvtn.f64.s64 q0, q1
+vcvtn.f64.u64 q0, q1
+vcvtp.s64.f64 q0, q1
+vcvtp.u64.f64 q0, q1
+vcvtp.f64.s64 q0, q1
+vcvtp.f64.u64 q0, q1
+vcvtm.s64.f64 q0, q1
+vcvtm.u64.f64 q0, q1
+vcvtm.f64.s64 q0, q1
+vcvtm.f64.u64 q0, q1
+it eq
+vcvtaeq.s32.f32 q0, q1
+vcvtaeq.s32.f32 q0, q1
+vpst
+vcvtaeq.s32.f32 q0, q1
+vcvtat.s32.f32 q0, q1
+vpst
+vcvta.s32.f32 q0, q1
+it eq
+vcvtneq.s32.f32 q0, q1
+vcvtneq.s32.f32 q0, q1
+vpst
+vcvtneq.s32.f32 q0, q1
+vcvtnt.s32.f32 q0, q1
+vpst
+vcvtn.s32.f32 q0, q1
+it eq
+vcvtpeq.s32.f32 q0, q1
+vcvtpeq.s32.f32 q0, q1
+vpst
+vcvtpeq.s32.f32 q0, q1
+vcvtpt.s32.f32 q0, q1
+vpst
+vcvtp.s32.f32 q0, q1
+it eq
+vcvtmeq.s32.f32 q0, q1
+vcvtmeq.s32.f32 q0, q1
+vpst
+vcvtmeq.s32.f32 q0, q1
+vcvtmt.s32.f32 q0, q1
+vpst
+vcvtm.s32.f32 q0, q1
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.d b/gas/testsuite/gas/arm/mve-vcvt-bad.d
new file mode 100644
index 0000000..dd0ec53
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.d
@@ -0,0 +1,6 @@
+#name: bad MVE VCVT instructions 
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vcvt-bad.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.l b/gas/testsuite/gas/arm/mve-vcvt-bad.l
new file mode 100644
index 0000000..7c4ea69
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.l
@@ -0,0 +1,77 @@
+[^:]*: Assembler messages:
+[^:]*:11: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#0'
+[^:]*:12: Error: immediate value out of range -- `vcvt.f16.s16 q0,q1,#17'
+[^:]*:13: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#0'
+[^:]*:14: Error: immediate value out of range -- `vcvt.f16.u16 q0,q1,#17'
+[^:]*:15: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#0'
+[^:]*:16: Error: immediate value out of range -- `vcvt.s16.f16 q0,q1,#17'
+[^:]*:17: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#0'
+[^:]*:18: Error: immediate value out of range -- `vcvt.u16.f16 q0,q1,#17'
+[^:]*:19: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#0'
+[^:]*:20: Error: immediate value out of range -- `vcvt.f32.s32 q0,q1,#33'
+[^:]*:21: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#0'
+[^:]*:22: Error: immediate value out of range -- `vcvt.f32.u32 q0,q1,#33'
+[^:]*:23: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#0'
+[^:]*:24: Error: immediate value out of range -- `vcvt.s32.f32 q0,q1,#33'
+[^:]*:25: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#0'
+[^:]*:26: Error: immediate value out of range -- `vcvt.u32.f32 q0,q1,#33'
+[^:]*:27: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1,#1'
+[^:]*:28: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1,#1'
+[^:]*:29: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1,#1'
+[^:]*:30: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1,#1'
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:31: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:33: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:34: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:36: Error: syntax error -- `vcvteq.f16.s16 q0,q1,#1'
+[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.f16.s16 q0,q1,#1'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vcvt.f16.s16 q0,q1,#1'
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:48: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:49: Error: bad type in SIMD instruction -- `vcvt.f64.s64 q0,q1'
+[^:]*:50: Error: bad type in SIMD instruction -- `vcvt.f64.u64 q0,q1'
+[^:]*:51: Error: bad type in SIMD instruction -- `vcvt.s64.f64 q0,q1'
+[^:]*:52: Error: bad type in SIMD instruction -- `vcvt.u64.f64 q0,q1'
+[^:]*:54: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:55: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:57: Error: syntax error -- `vcvteq.u32.f32 q0,q1'
+[^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtt.u32.f32 q0,q1'
+[^:]*:60: Error: instruction missing MVE vector predication code -- `vcvt.u32.f32 q0,q1'
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:69: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:70: Error: bad type in SIMD instruction -- `vcvtb.f16.f64 q0,q1'
+[^:]*:71: Error: bad type in SIMD instruction -- `vcvtb.f64.f16 q0,q1'
+[^:]*:72: Error: bad type in SIMD instruction -- `vcvtb.f32.f64 q0,q1'
+[^:]*:73: Error: bad type in SIMD instruction -- `vcvtb.f64.f32 q0,q1'
+[^:]*:75: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:76: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:78: Error: syntax error -- `vcvtbeq.f16.f32 q0,q1'
+[^:]*:79: Error: vector predicated instruction should be in VPT/VPST block -- `vcvtbt.f16.f32 q0,q1'
+[^:]*:81: Error: instruction missing MVE vector predication code -- `vcvtb.f16.f32 q0,q1'
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Error: bad type in SIMD instruction -- `vcvtt.f16.f64 q0,q1'
+[^:]*:84: Error: bad type in SIMD instruction -- `vcvtt.f64.f16 q0,q1'
+[^:]*:85: Error: bad type in SIMD instruction -- `vcvtt.f32.f64 q0,q1'
+[^:]*:86: Error: bad type in SIMD instruction -- `vcvtt.f64.f32 q0,q1'
+[^:]*:88: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:89: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:91: Error: syntax error -- `vcvtteq.f16.f32 q0,q1'
+[^:]*:92: Error: vector predicated instruction should be in VPT/VPST block -- `vcvttt.f16.f32 q0,q1'
+[^:]*:94: Error: instruction missing MVE vector predication code -- `vcvtt.f16.f32 q0,q1'
diff --git a/gas/testsuite/gas/arm/mve-vcvt-bad.s b/gas/testsuite/gas/arm/mve-vcvt-bad.s
new file mode 100644
index 0000000..302fe88
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vcvt-bad.s
@@ -0,0 +1,94 @@
+.macro cond1
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vcvt\().f16.s16 q0, q1, #1
+.endr
+.endm
+
+.syntax unified
+.thumb
+
+vcvt.f16.s16 q0, q1, #0
+vcvt.f16.s16 q0, q1, #17
+vcvt.f16.u16 q0, q1, #0
+vcvt.f16.u16 q0, q1, #17
+vcvt.s16.f16 q0, q1, #0
+vcvt.s16.f16 q0, q1, #17
+vcvt.u16.f16 q0, q1, #0
+vcvt.u16.f16 q0, q1, #17
+vcvt.f32.s32 q0, q1, #0
+vcvt.f32.s32 q0, q1, #33
+vcvt.f32.u32 q0, q1, #0
+vcvt.f32.u32 q0, q1, #33
+vcvt.s32.f32 q0, q1, #0
+vcvt.s32.f32 q0, q1, #33
+vcvt.u32.f32 q0, q1, #0
+vcvt.u32.f32 q0, q1, #33
+vcvt.f64.s64 q0, q1, #1
+vcvt.f64.u64 q0, q1, #1
+vcvt.s64.f64 q0, q1, #1
+vcvt.u64.f64 q0, q1, #1
+cond1
+it eq
+vcvteq.f16.s16 q0, q1, #1
+vcvteq.f16.s16 q0, q1, #1
+vpst
+vcvteq.f16.s16 q0, q1, #1
+vcvtt.f16.s16 q0, q1, #1
+vpst
+vcvt.f16.s16 q0, q1, #1
+
+.macro cond2
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vcvt\().f16.s16 q0, q1
+.endr
+.endm
+
+cond2
+vcvt.f64.s64 q0, q1
+vcvt.f64.u64 q0, q1
+vcvt.s64.f64 q0, q1
+vcvt.u64.f64 q0, q1
+it eq
+vcvteq.u32.f32 q0, q1
+vcvteq.u32.f32 q0, q1
+vpst
+vcvteq.u32.f32 q0, q1
+vcvtt.u32.f32 q0, q1
+vpst
+vcvt.u32.f32 q0, q1
+
+.macro cond3 mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().f16.f32 q0, q1
+.endr
+.endm
+
+cond3 vcvtb
+vcvtb.f16.f64 q0, q1
+vcvtb.f64.f16 q0, q1
+vcvtb.f32.f64 q0, q1
+vcvtb.f64.f32 q0, q1
+it eq
+vcvtbeq.f16.f32 q0, q1
+vcvtbeq.f16.f32 q0, q1
+vpst
+vcvtbeq.f16.f32 q0, q1
+vcvtbt.f16.f32 q0, q1
+vpst
+vcvtb.f16.f32 q0, q1
+cond3 vcvtt
+vcvtt.f16.f64 q0, q1
+vcvtt.f64.f16 q0, q1
+vcvtt.f32.f64 q0, q1
+vcvtt.f64.f32 q0, q1
+it eq
+vcvtteq.f16.f32 q0, q1
+vcvtteq.f16.f32 q0, q1
+vpst
+vcvtteq.f16.f32 q0, q1
+vcvttt.f16.f32 q0, q1
+vpst
+vcvtt.f16.f32 q0, q1