Age | Commit message (Collapse) | Author | Files | Lines |
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This was needed when gas was using the automake cygnus option, but
this was removed years ago by Simon in d0ac1c44885daf68f631befa37e
("Bump to autoconf 2.69 and automake 1.15.1"). So delete it here.
The info pages are already & still installed by default w/out it.
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sub-directories
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Regenerate Makefile.in files with the unmodified automake 1.15.1 to
remove
runstatedir = @runstatedir@
bfd/
* Makefile.in: Regenerate.
binutils/
* Makefile.in: Regenerate.
gas/
* Makefile.in: Regenerate.
gold/
* Makefile.in: Regenerate.
* testsuite/Makefile.in: Likewise.
gprof/
* Makefile.in: Regenerate.
ld/
* Makefile.in: Regenerate.
opcodes/
* Makefile.in: Regenerate.
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Regenerate configure files with the unmodified autoconf 2.69 to remove
--runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run]
bfd/
* configure: Regenerate.
binutils/
* configure: Regenerate.
gas/
* configure: Regenerate.
gold/
* configure: Regenerate.
gprof/
* configure: Regenerate.
ld/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
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PR 28793:
The alignment may be removed in linker. We need to create new frag after
alignment to prevent the assembler from computing static offsets.
gas/
* config/tc-riscv.c (riscv_frag_align_code): Create new frag.
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This was needed by ancient versions of automake, but that hasn't been
the case since at least automake-1.5, so punt this from the tree.
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regenerate files.
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PR 28762
* app.c (do_scrub_chars): Correct handling when the symbol is not 'af'.
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tc-ppc.c: In function 'ppc_comm':
tc-ppc.c:4560:40: error: 'visibility' may be used uninitialized in this function [-Werror=maybe-uninitialized]
With that fixed we hit lots of segfaults in the ld testsuite.
PR 22085
bfd/
* xcofflink.c (xcoff_link_input_bfd): Don't segfault on NULL
sym_hash.
gas/
* config/tc-ppc.c (ppc_comm): Init visibility.
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In order to ease port of GNU assembly code and especially ld testsuite,
this patch allows XCOFF to accept the usual GNU syntax for visibility.
PR 22085
gas/ChangeLog:
* config/tc-ppc.c (ppc_GNU_visibility): New function.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-visibility-2-32.d: New test.
* testsuite/gas/ppc/xcoff-visibility-2-64.d: New test.
* testsuite/gas/ppc/xcoff-visibility-2.s: New test.
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XCOFF assembly defines the visibility using an additional argument
on several pseudo-ops: .globl, .weak, .extern and .comm.
This implies that .globl and .weak syntax is different than the
usual GNU syntax. But we want to provide compatibility with AIX
assembler, especially because GCC is generating the visibility
using this XCOFF syntax.
PR 22085
bfd/ChangeLog:
* coffcode.h (coff_write_object_contents): Change XCOFF header
vstamp field to 2.
* coffgen.c (coff_print_symbol): Increase the size for n_type.
gas/ChangeLog:
* config/tc-ppc.c (ppc_xcoff_get_visibility): New function.
(ppc_globl): New function.
(ppc_weak): New function.
(ppc_comm): Add visibility field support.
(ppc_extern): Likewise.
* testsuite/gas/all/cofftag.d: Adjust to new n_type size
providing by objdump.
* testsuite/gas/ppc/test1xcoff32.d: Likewise.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-visibility-1-32.d: New test.
* testsuite/gas/ppc/xcoff-visibility-1-64.d: New test.
* testsuite/gas/ppc/xcoff-visibility-1.s: New test.
include/ChangeLog:
* coff/internal.h (SYM_V_INTERNAL, SYM_V_HIDDEN,
SYM_V_PROTECTED, SYM_V_EXPORTED, SYM_V_MASK): New defines.
* coff/xcoff.h (struct xcoff_link_hash_entry): Add visibility
field.
ld/ChangeLog:
* testsuite/ld-pe/pr19803.d: Adjust to new n_type size
providing by objdump.
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As pre-approved by Alan in
https://sourceware.org/pipermail/binutils/2021-September/118019.html
and I believe people have run into getting testsuite failures for
test-environments with "long" directory names, at least once more
since that time. Enough. I grepped the gas, binutils and ld
testsuites for "CU:" to catch target-specific occurrences, but I
noticed none. I chose to remove "CU:" on the objdump tests instead of
changing options to get the wide format, so as to keep the name of the
test consistent with actual options; but added it to the readelf
options for the gas test as I believe the "CU:" format is preferable.
Tested for cris-elf and native x86_64-pc-linux-gnu.
binutils:
* dwarf.c (display_debug_lines_decoded): Don't check the
string length of the directory, instead emit the "CU: dir/name"
format only if wide output is requested.
* testsuite/binutils-all/dw5.W, testsuite/binutils-all/objdump.WL:
Adjust accordingly.
gas:
* testsuite/gas/elf/dwarf-5-loc0.d: Add -W to readelf options.
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This patch adds support for TLS relocation targeting C_HIDEXT symbols.
In gas, TLS relocations, except R_TLSM and R_TLMSL, must keep the value
of their target symbol.
In ld, it simply ensures that internal TLS symbols are added to the
linker hash table for xcoff_reloc_type_tls.
It also improves the tests made by both.
bfd/ChangeLog:
* coff-rs6000.c (xcoff_howto_table): Fix name of R_TLSML.
(xcoff_reloc_type_tls): Replace the error when h is NULL by
an assert.
(xcoff_complain_overflow_unsigned_func): Adjust comments.
* coff64-rs6000.c (xcoff64_howto_table): Fix name of R_TLSML.
* xcofflink.c (xcoff_link_add_symbols_to_hash_table): New
function.
(xcoff_link_add_symbols): Add C_HIDEXT TLS symbols to the linker
hash table.
gas/ChangeLog:
* config/tc-ppc.c (md_apply_fix): Enable support for TLS
relocation over internal symbols.
* testsuite/gas/ppc/aix.exp: Replace xcoff-tlms by xcoff-tls.
* testsuite/gas/ppc/xcoff-tlsm-32.d: Removed.
* testsuite/gas/ppc/xcoff-tlsm-64.d: Removed.
* testsuite/gas/ppc/xcoff-tlsm.s: Removed.
* testsuite/gas/ppc/xcoff-tls-32.d: New test.
* testsuite/gas/ppc/xcoff-tls-64.d: New test.
* testsuite/gas/ppc/xcoff-tls.s: New test.
ld/ChangeLog:
* testsuite/ld-powerpc/aix52.exp: Improve aix-tls-reloc test.
* testsuite/ld-powerpc/aix-tls-reloc.s: Likewise.
* testsuite/ld-powerpc/aix-tls-reloc-32.d: Removed.
* testsuite/ld-powerpc/aix-tls-reloc-64.d: Removed.
* testsuite/ld-powerpc/aix-tls-reloc-32.dd: New test.
* testsuite/ld-powerpc/aix-tls-reloc-32.dt: New test.
* testsuite/ld-powerpc/aix-tls-reloc-64.dd: New test.
* testsuite/ld-powerpc/aix-tls-reloc-64.dt: New test.
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After commit d8af286fffa ("RISC-V: Drop the privileged spec v1.9
support.") has removed support for privileged spec v1.9, this removes
it from the documentation.
References: d8af286fffa ("RISC-V: Drop the privileged spec v1.9 support.")
gas/ChangeLog:
* configure: Regenerate.
* configure.ac: Remove reference to priv spec 1.9.
* po/fr.po: Same.
* po/ru.po: Same.
* po/uk.po: Same.
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While support for the privileged spec was added in a63375ac337
("RISC-V: Hypervisor ext: support Privileged Spec 1.12"), the
documentation has not been updated. Add 1.12 to the relevant
documentation.
References: a63375ac337 ("RISC-V: Hypervisor ext: support Privileged Spec 1.12")
gas/ChangeLog:
* config/tc-riscv.c: Add 1.12 to the usage message.
* configure: Regenerate.
* configure.ac: Add 1.12 to the help/usage message.
* po/fr.po: Same.
* po/ru.po: Same.
* po/uk.po: Same.
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Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1. Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions. Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.
bfd/
* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
recognize zicsr and zifencei.
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
the default version of i is 2.1.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
the default version of i is 2.1.
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
into Tag_RISCV_arch since it is added implied when i's version is
larger than 2.1.
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This patch adds support for three new SME instructions: ADDSPL,
ADDSVL and RDSVL. They behave like ADDPL, ADDVL and RDVL, but read
the streaming vector length instead of the current vector length.
opcodes/
* aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL.
* aarch64-dis-2.c: Regenerate.
gas/
* testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests
for ADDSPL, ADDSVL and RDSVL.
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To avoid issues like that addressed by 6e3e5c9e4181 ("x86: extend SSE
check to PCLMULQDQ, AES, and GFNI insns"), base the check on opcode
attributes and operand types.
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Neither non-64-bit code nor uses with a non-zero offset from a symbol
should be converted to PLT32, as an eventual PLT entry would not express
what was requested.
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Some targets restrict symbol addresses in .text to instruction
boundaries.
* testsuite/gas/all/quoted-sym-names.s: Define syms in .data.
* testsuite/gas/all/quoted-sym-names.d: Adjust to suit.
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fits_in_disp8() can be called before ambiguous operands get resolved
or rejected (in process_suffix()), which requires that i.memshift be
non-negative to avoid an internal error. This case wasn't covered by
6c0946d0d28d ("x86: correct VFPCLASSP{S,D} operand size handling").
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Strange effects can result from the present handling, e.g.:
.if 1
"backslash\\":
.endif
yields first (correctly) "missing closing `"'" but then also "invalid
character '\' in mnemonic" and further "end of file inside conditional".
Symbols names ending in \ are in principle not expressable with that
scheme.
Instead of recording whether a backslash was seen, inspect the
subsequent character right away. Only accept \\ (meaning a single
backslash in the resulting symbol name) and \" (meaning an embedded
double quote in the resulting symbol name) for now, warning about any
other combination.
While perhaps not necessary immediately, also permit concatenated
strings to form a symbol name. This may become useful if going forward
we would want to support \<octal> or \x<hex> sequences, where closing
and re-opening quotes can be useful to delimit such sequences.
The ELF "Multibyte symbol names" test gets switched away from using
.set, as that would now also mean excluding nios2 and pru. By using
.equiv instead, even the existing #notarget can be dropped. (For h8300
the .section directive additionally needs attributes specified, to avoid
a target specific warning.)
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The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
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Squash another totally useless fuzz report that I should have ignored.
* read.c (next_char_of_string): Avoid integer overflow.
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9223371018427387904 * 2 cannot be represented in type 'long', yes, but
we don't care.
* expr.c (expr): Avoid signed overflow.
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In some cases, eg. riscv_pre_output_hook, gas generates out-of-order
relocations. Various places in the linker assume relocs are sorted
by increasing r_offset, which is normally the case. Provide
GAS_SORT_RELOCS to handle unsorted relocs.
bfd/
PR 28709
* elf32-nds32.c (nds32_insertion_sort): Make static.
* elf32-nds32.h (nds32_insertion_sort): Delete declaration.
gas/
PR 28709
* write.c (write_relocs): Implement reloc sorting by r_offset
when GAS_SORT_RELOCS.
* config/tc-nds32.c (compar_relent, nds32_set_section_relocs): Delete.
* config/tc-nds32.h (nds32_set_section_relocs): Don't declare.
(SET_SECTION_RELOCS): Don't define.
(GAS_SORT_RELOCS): Define.
* config/tc-riscv.h (GAS_SORT_RELOCS): Define.
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Maskray (Fangrui Song) had suggested me before that we should combine
multiple testcases into one file as possible as we can. So that we can
more easily understand what these test cases are testing, and easier to
maintain. Therefore, this patch rewrites all csr testcases, to make them
more clean.
gas/
* testsuite/gas/riscv/csr-fail-nonexistent.d: Renamed from
priv-reg-fail-nonexistent testcase.
* testsuite/gas/riscv/csr-fail-nonexistent.: Likewise.
* testsuite/gas/riscv/csr-fail-nonexistent.s: Likewise.
* testsuite/gas/riscv/csr-insns-pseudo-noalias.d: Renamed from
priv-reg-pseudo testcase.
* testsuite/gas/riscv/csr-insns-pseudo.d: Likewise.
* testsuite/gas/riscv/csr-insns-pseudo.s: Likewise.
* testsuite/gas/riscv/csr-insns-read-only.d: Renamed from
priv-reg-fail-read-only-02 testcase.
* testsuite/gas/riscv/csr-insns-read-only.l: Likewise.
* testsuite/gas/riscv/csr-insns-read-only.s: Likewise.
* testsuite/gas/riscv/h-ext-32.d: Moved hypervisor csrs to csr.s.
* testsuite/gas/riscv/h-ext-32.s: Likewise.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/h-ext-64.s: Likewise.
* testsuite/gas/riscv/csr.s: Renamed from priv-reg.s, and then
added the hypervisor csrs.
* testsuite/gas/riscv/csr-version-1p9p1.d: The csr testcase when
the privileged spec is 1.9.1. Also tested all invalid csr warnings
when -mcsr-check is enabled.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Likewise, but the
privileged spec is 1.10..
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise, but the
privileged spec is 1.11.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise, but the
privileged spec is 1.12.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/priv-reg*: Removed or Renamed.
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This is the Hypervisor Extension 1.0
- Hypervisor Memory-Management Instructions
HFENCE.VVMA, HFENCE.GVMA,
- Hypervisor Virtual Machine Load and Store Instructions
HLV.B, HLV.BU, HSV.B,
HLV.H, HLV.HU, HLVX.HU, HSB.H,
HLV.W, HLV.WU, HLVX.WU, HSV.W,
HLV.D, HSV.D
- Hypervisor CSRs (some new, some address changed)
hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,
Note that following were added already as part of svinval extension
support:
HINVAL.GVMA, HINVAL.VVMA
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
bfd/
* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
* config/tc-riscv.c (abort_version): Updated comment.
(validate_riscv_insn): Annotate switch-break.
* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
* testsuite/gas/riscv/h-ext-32.s: Likewise.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
instrcutions.
opcodes/
* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
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This makes way for a clean 1.12 based Hypervisor Ext support.
There are no known implementors of 1.9.1 H-ext. (Per Jim, kendryte k210
is based on priv spec 1.9.1, but it seems unlikely that they implemented
H-ext).
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
gas/
* testsuite/gas/riscv/csr-dw-regnums.d: Drop the hypervisor csrs
defined in the privileged spec 1.9.1.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg.s: Likewise.
include/
* opcode/riscv-opc.h: Drop the hypervisor csrs defined in the
privileged spec 1.9.1.
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Add opcodes in testcases to make sure every instruction generate
right opcode after disassemble.
gas/ChangeLog:
* testsuite/gas/riscv/k-ext-64.d: Add opcode detect.
* testsuite/gas/riscv/k-ext.d: Ditto.
* testsuite/gas/riscv/zbkb-32.d: Ditto.
* testsuite/gas/riscv/zbkb-64.d: Ditto.
* testsuite/gas/riscv/zbkc-32.d: Ditto.
* testsuite/gas/riscv/zbkc-64.d: Ditto.
* testsuite/gas/riscv/zbkx-32.d: Ditto.
* testsuite/gas/riscv/zbkx-64.d: Ditto.
* testsuite/gas/riscv/zknd-32.d: Ditto.
* testsuite/gas/riscv/zknd-64.d: Ditto.
* testsuite/gas/riscv/zkne-32.d: Ditto.
* testsuite/gas/riscv/zkne-64.d: Ditto.
* testsuite/gas/riscv/zknh-32.d: Ditto.
* testsuite/gas/riscv/zknh-64.d: Ditto.
* testsuite/gas/riscv/zksed-32.d: Ditto.
* testsuite/gas/riscv/zksed-64.d: Ditto.
* testsuite/gas/riscv/zksh-32.d: Ditto.
* testsuite/gas/riscv/zksh-64.d: Ditto.
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Rather than trying to fix this (which would require making an assumption
on the upper half of %esp being zero), simply issue an error. While at
it, since the generated code is in conflict with -momit-lock-prefix=yes,
issue an error in that case as well.
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We would better be prepared for 'm' being the first character of the
incoming string.
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Tested on x86_64-pc-linux-gnu.
opcodes/ChangeLog:
2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* i386-dis.c (swap_operand): Terminate mnemonicendp.
gas/ChangeLog:
2021-12-17 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
* testsuite/gas/i386/opts-intel.d: Updated expected disassembly.
* testsuite/gas/i386/opts.d: Likewise.
* testsuite/gas/i386/sse2avx-opts-intel.d: Likewise.
* testsuite/gas/i386/sse2avx-opts.d: Likewise.
* testsuite/gas/i386/x86-64-opts-intel.d: Likewise.
* testsuite/gas/i386/x86-64-opts.d: Likewise.
* testsuite/gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
* testsuite/gas/i386/x86-64-sse2avx-opts.d: Likewise.
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relaxation.
PR 28686
gas * config/tc-avr.h (tc_fix_adjustable): Define.
* config/tc-avr.c (avr_fix_adjustable): New function.
* testsuite/gas/all/gas.exp: Skip tests that need adjustable fixups.
* testsuite/gas/elf/elf.exp: Likewise.
* testsuite/gas/avr/diffreloc_withrelax.d: Adjust expected output.
* testsuite/gas/avr/pc-relative-reloc.d: Adjust expected output.
ld * testsuite/ld-avr/avr-prop-7.d: Adjust expected output.
* testsuite/ld-avr/avr-prop-8.d: Likewise.
* testsuite/ld-avr/pr13402.d: Likewise.
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This patch adds AArch32 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.
The cpu_arch_ver entries for ARM_ARCH_V9_2A and ARM_ARCH_V9_3A
are technically redundant but it seemed less surprising to include
them anyway.
include/
* opcode/arm.h (ARM_ARCH_V9_1A, ARM_ARCH_V9_2A): New macros.
(ARM_ARCH_V9_3A): Likewise.
gas/
* doc/c-arm.texi: Add armv9.1-a, armv9.2-a and armv9.3-a.
* config/tc-arm.c (armv91a_ext_table, armv92a_ext_table): New macros.
(armv93a_ext_table): Likewise.
(arm_archs): Add armv9.1-a, armv9.2-a and armv9.3-a.
(cpu_arch_ver): Add ARM_ARCH_V9_1A, ARM_ARCH_V9_2A and ARM_ARCH_V9_3A.
* NEWS: Mention the above.
* testsuite/gas/arm/attr-march-armv9_1-a.d: New test.
* testsuite/gas/arm/attr-march-armv9_2-a.d: Likewise.
* testsuite/gas/arm/attr-march-armv9_3-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.1-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.2-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv9.3-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.1-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.2-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv9.3-a.d: Likewise.
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This patch adds AArch32 support for -march=armv8.[78]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags and tables.
The cpu_arch_ver entries are technically redundant but
it seemed less surprising to include them anyway.
include/
* opcode/arm.h (ARM_ARCH_V8_7A, ARM_ARCH_V8_8A): New macros.
gas/
* doc/c-arm.texi: Add armv8.7-a and armv8.8-a.
* config/tc-arm.c (armv87a_ext_table, armv88a_ext_table): New macros.
(arm_archs): Add armv8.7-a and armv8.8-a.
(cpu_arch_ver): Add ARM_ARCH_V8_7A and ARM_ARCH_V8_8A.
* NEWS: Mention the above.
* testsuite/gas/arm/attr-march-armv8_7-a.d: New test.
* testsuite/gas/arm/attr-march-armv8_8-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv8.7-a.d: Likewise.
* testsuite/gas/arm/bfloat16-armv8.8-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv8.7-a.d: Likewise.
* testsuite/gas/arm/i8mm-armv8.8-a.d: Likewise.
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This patch adds AArch64 support for -march=armv9.[123]-a.
The behaviour of the new options can be expressed using a
combination of existing feature flags, so we don't need to
eat into the vanishing number of spare AARCH64_FEATURE_* bits.
Hoewver, it was more convenient to separate out the |s of
feature flags so that Armv9.1-A could reuse the set for
Armv8.6-A, and so on.
include/
* opcode/aarch64.h (AARCH64_ARCH_V8_FEATURES): New macro,
split out from...
(AARCH64_ARCH_V8): ...here.
(AARCH64_ARCH_V8_1_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_1): ...here.
(AARCH64_ARCH_V8_2_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_2): ...here.
(AARCH64_ARCH_V8_3_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_3): ...here.
(AARCH64_ARCH_V8_4_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_4): ...here.
(AARCH64_ARCH_V8_5_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_5): ...here.
(AARCH64_ARCH_V8_6_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_6): ...here.
(AARCH64_ARCH_V8_7_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_7): ...here.
(AARCH64_ARCH_V8_8_FEATURES): New macro, split out from...
(AARCH64_ARCH_V8_8): ...here.
(AARCH64_ARCH_V9_FEATURES): New macro, split out from...
(AARCH64_ARCH_V9): ...here.
(AARCH64_ARCH_V9_1_FEATURES, AARCH64_ARCH_V9_1): New macros.
(AARCH64_ARCH_V9_2_FEATURES, AARCH64_ARCH_V9_2): New macros.
(AARCH64_ARCH_V9_3_FEATURES, AARCH64_ARCH_V9_3): New macros.
gas/
* doc/c-aarch64.texi: Add armv9.1-a, armv9-2-a and armv9.3-a.
* config/tc-aarch64.c (aarch64_archs): Likewise.
* NEWS: Mention the above.
* testsuite/gas/aarch64/armv9_invalid.d,
testsuite/gas/aarch64/armv9_invalid.s,
testsuite/gas/aarch64/armv9_invalid.l: New test.
* testsuite/gas/aarch64/armv9_1.d,
testsuite/gas/aarch64/armv9_1.s: Likewise.
* testsuite/gas/aarch64/armv9_1_invalid.d,
testsuite/gas/aarch64/armv9_1_invalid.s,
testsuite/gas/aarch64/armv9_1_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_2.d,
testsuite/gas/aarch64/armv9_2.s: Likewise.
* testsuite/gas/aarch64/armv9_2_invalid.d,
testsuite/gas/aarch64/armv9_2_invalid.s,
testsuite/gas/aarch64/armv9_2_invalid.l: Likewise.
* testsuite/gas/aarch64/armv9_3.d,
testsuite/gas/aarch64/armv9_3.s: Likewise.
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According to the privileged spec, there are five new instructions for
svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to
enable the hypervisor extension. But there is no implementation of
hypervisor extension in mainline for now, so let's consider the related
issues later.
31..25 24..20 19..15 14..12 11...7 6..2 1..0
sinval.vma 0001011 rs2 rs1 000 00000 11100 11
sfence.w.inval 0001100 00000 00000 000 00000 11100 11
sfence.inval.ir 0001100 00001 00000 000 00000 11100 11
hinval.vvma 0010011 rs2 rs1 000 00000 11100 11
hinval.gvma 0110011 rs2 rs1 000 00000 11100 11
This patch is cherry-picked from the riscv integration branch since the
svinval extension is frozen for now. Besides, we fix the funct7 encodings
of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011
and 0x0110011.
bfd/
* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
(riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL.
gas/
* testsuite/gas/riscv/svinval.d: New testcase.
* testsuite/gas/riscv/svinval.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for svinval.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
* riscv-opc.c (riscv_opcodes): Added svinval instructions.
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gas/config/tc-loongarch.c: In function ‘loongarch_args_parser_can_match_arg_helper’:
gas/config/tc-loongarch.c:661:13: error: cast from pointer to integer of different size [-Werror=pointer
-to-int-cast]
661 | imm = (offsetT) str_hash_find (r_htab, arg);
| ^
Cast it to the correct size int, relying on normal integer promotions
if offsetT is larger than a pointer.
* config/tc-loongarch.c (loongarch_args_parser_can_match_arg_helper):
Cast return from str_hash_find to intptr_t, not offsetT.
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* To be consistent with -march option, removed the "=" operator when
user want to reset the whole architecture string. So the formats are,
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, <ISA string>
* Don't allow to add or remove the base extensions in the .option arch
directive. Instead, users should reset the whole architecture string
while they want to change the base extension.
* The operator "+" won't update the version of extension, if the
extension is already in the subset list.
bfd/
* elfxx-riscv.c (riscv_add_subset): Don't update the version
if the extension is already in the subset list.
(riscv_update_subset): To be consistent with -march option,
removed the "=" operator when user want to reset the whole
architecture string. Besides, Don't allow to add or remove
the base extensions in the .option arch directive.
gas/
* testsuite/gas/riscv/option-arch-01.s: Updated since we cannot
add or remove the base extensions in the .option arch directive.
* testsuite/gas/riscv/option-arch-02.s: Likewise.
* testsuite/gas/riscv/option-arch-fail.l: Likewise.
* testsuite/gas/riscv/option-arch-fail.s: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Set -misa-spec=2.2.
* testsuite/gas/riscv/option-arch-01b.d: Likewise.
* testsuite/gas/riscv/option-arch-02.d: Updated since the .option
arch, + won't change the version of extension, if the extension is
already in the subset list.
* testsuite/gas/riscv/option-arch-03.s: Removed the "=" operator
when resetting the whole architecture string.
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gas/
* NEWS: Mention support for Armv8.8-A and for new system registers.
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This patch adds support for the Armv8.8-A BC instruction.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions/BC-cond--Branch-Consistent-conditionally-?lang=en]
include/
* opcode/aarch64.h (AARCH64_FEATURE_HBC): New macro.
(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_HBC.
opcodes/
* aarch64-tbl.h (aarch64_feature_hbc): New variable.
(HBC, HBC_INSN): New macros.
(aarch64_opcode_table): Add BC.C.
* aarch64-dis-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document +hbc.
* config/tc-aarch64.c (aarch64_features): Add "hbc".
* testsuite/gas/aarch64/hbc.s, testsuite/gas/aarch64/hbc.d: New test.
* testsuite/gas/aarch64/hbc-invalid.s,
testsuite/gas/aarch64/hbc-invalid.l,
testsuite/gas/aarch64/hbc-invalid.d: New test.
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The MOPS instructions should be used as a triple, such as:
cpyfp [x0]!, [x1]!, x2!
cpyfm [x0]!, [x1]!, x2!
cpyfe [x0]!, [x1]!, x2!
The registers should also be the same for each writeback operand.
This patch adds a warning for code that doesn't follow this rule,
along similar lines to the warning that we already emit for
invalid uses of MOVPRFX.
include/
* opcode/aarch64.h (C_SCAN_MOPS_P, C_SCAN_MOPS_M, C_SCAN_MOPS_E)
(C_SCAN_MOPS_PME): New macros.
(AARCH64_OPDE_A_SHOULD_FOLLOW_B): New aarch64_operand_error_kind.
(AARCH64_OPDE_EXPECTED_A_AFTER_B): Likewise.
(aarch64_operand_error): Make each data value a union between
an int and a string.
opcodes/
* aarch64-tbl.h (MOPS_CPY_OP1_OP2_INSN): Add scan flags.
(MOPS_SET_OP1_OP2_INSN): Likewise.
* aarch64-opc.c (set_out_of_range_error): Update after change to
aarch64_operand_error.
(set_unaligned_error, set_reg_list_error): Likewise.
(init_insn_sequence): Use a 3-instruction sequence for
MOPS P instructions.
(verify_mops_pme_sequence): New function.
(verify_constraints): Call it.
* aarch64-dis.c (print_verifier_notes): Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
gas/
* config/tc-aarch64.c (operand_mismatch_kind_names): Add entries
for AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
(operand_error_higher_severity_p): Check that
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B
come between AARCH64_OPDE_RECOVERABLE and AARCH64_OPDE_SYNTAX_ERROR;
their relative order is not significant.
(record_operand_error_with_data): Update after change to
aarch64_operand_error.
(output_operand_error_record): Likewise. Handle
AARCH64_OPDE_A_SHOULD_FOLLOW_B and AARCH64_OPDE_EXPECTED_A_AFTER_B.
* testsuite/gas/aarch64/mops_invalid_2.s,
testsuite/gas/aarch64/mops_invalid_2.d,
testsuite/gas/aarch64/mops_invalid_2.l: New test.
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This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.
I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]
include/
* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
(AARCH64_OPND_MOPS_WB_Rn): Likewise.
opcodes/
* aarch64-asm.h (ins_x0_to_x30): New inserter.
* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
* aarch64-dis.h (ext_x0_to_x30): New extractor.
* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
* aarch64-tbl.h (aarch64_feature_mops): New feature set.
(aarch64_feature_mops_memtag): Likewise.
(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
(MOPS_SET_INSN): New macros.
(aarch64_opcode_table): Add MOPS instructions.
(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
* aarch64-opc.c (aarch64_print_operand): Handle
AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
AARCH64_OPND_MOPS_WB_Rn.
(verify_three_different_regs): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
gas/
* doc/c-aarch64.texi: Document +mops.
* config/tc-aarch64.c (parse_x0_to_x30): New function.
(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
(aarch64_features): Add "mops".
* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
* testsuite/gas/aarch64/mops_invalid.s,
* testsuite/gas/aarch64/mops_invalid.d,
* testsuite/gas/aarch64/mops_invalid.l: Likewise.
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Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1.
Both of them were previously unmapped. allint supports a 0/1 immediate.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en]
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en]
opcodes/
* aarch64-opc.c (SR_V8_8): New macro.
(aarch64_sys_regs): Add allint and icc_nmiar1_el1.
(aarch64_pstatefields): Add allint.
gas/
* testsuite/gas/aarch64/armv8_8-a-sysregs.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test.
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.
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Armv8.8-A defines a read-only system register called id_aa64isar2_el1.
The register was previously RES0 and should therefore be accepted
at all architecture levels.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en]
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add id_aa64isar2_el1.
gas/
* testsuite/gas/aarch64/sysreg-diagnostic.s: Test writes to
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg-diagnostic.d: Update accordingly.
* testsuite/gas/aarch64/sysreg-diagnostic.l: Likewise.
* testsuite/gas/aarch64/sysreg.s: Test reads from
id_aa64isar2_el1.
* testsuite/gas/aarch64/sysreg.d: Update accordingly.
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