diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-12-02 15:00:57 +0000 |
| commit | a5e9beead8580777ea4886b06c493a6f79570f93 (patch) | |
| tree | 431281e2d3691b7a3a2d67238d2aac7d0dfadcf3 /gas | |
| parent | e14c9cb6c88e3dbcbaef4e0f62f8e07ece17b51b (diff) | |
| download | gdb-a5e9beead8580777ea4886b06c493a6f79570f93.zip gdb-a5e9beead8580777ea4886b06c493a6f79570f93.tar.gz gdb-a5e9beead8580777ea4886b06c493a6f79570f93.tar.bz2 | |
aarch64: Add Armv8.8-A system registers
Armv8.8-A defines two new system registers: allint and icc_nmiar1_el1.
Both of them were previously unmapped. allint supports a 0/1 immediate.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ALLINT--All-Interrupt-Mask-Bit?lang=en]
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/ICC-NMIAR1-EL1--Interrupt-Controller-Non-maskable-Interrupt-Acknowledge-Register-1?lang=en]
opcodes/
* aarch64-opc.c (SR_V8_8): New macro.
(aarch64_sys_regs): Add allint and icc_nmiar1_el1.
(aarch64_pstatefields): Add allint.
gas/
* testsuite/gas/aarch64/armv8_8-a-sysregs.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs.d: New test.
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l,
* testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d: New test.
Diffstat (limited to 'gas')
5 files changed, 46 insertions, 0 deletions
diff --git a/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d new file mode 100644 index 0000000..5bab9fc --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.d @@ -0,0 +1 @@ +#error_output: armv8_8-a-sysregs-invalid.l diff --git a/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l new file mode 100644 index 0000000..c3cf033 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.l @@ -0,0 +1,6 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#-1' +[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#2' +[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#15' +[^:]*:[0-9]+: Error: immediate value out of range 0 to 1 at operand 2 -- `msr allint,#0x100000000' +[^:]*:[0-9]+: Warning: specified register cannot be written to at operand 1 -- `msr icc_nmiar1_el1,x0' diff --git a/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s new file mode 100644 index 0000000..7534f14 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs-invalid.s @@ -0,0 +1,8 @@ + .arch armv8.8-a + + msr allint, #-1 + msr allint, #2 + msr allint, #15 + msr allint, #0x100000000 + + msr icc_nmiar1_el1, x0 diff --git a/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.d new file mode 100644 index 0000000..294fed2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.d @@ -0,0 +1,19 @@ +#as: -march=armv8.8-a +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +[^:]+:\s+d5184300 msr allint, x0 +[^:]+:\s+d518430f msr allint, x15 +[^:]+:\s+d518431e msr allint, x30 +[^:]+:\s+d518431f msr allint, xzr +[^:]+:\s+d5384300 mrs x0, allint +[^:]+:\s+d5384310 mrs x16, allint +[^:]+:\s+d538431e mrs x30, allint +[^:]+:\s+d501401f msr allint, #0x0 +[^:]+:\s+d501411f msr allint, #0x1 +[^:]+:\s+d501421f msr s0_1_c4_c2_0, xzr +[^:]+:\s+d538c9a0 mrs x0, icc_nmiar1_el1 diff --git a/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.s new file mode 100644 index 0000000..dd43ad8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/armv8_8-a-sysregs.s @@ -0,0 +1,12 @@ + msr allint, x0 + MSR ALLINT, X15 + msr allint, x30 + msr allint, xzr + mrs x0, allint + mrs X16, ALLINT + mrs x30, allint + msr allint, #0 + msr allint, #1 + .inst 0xd501421f + + mrs x0, icc_nmiar1_el1 |