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| author | Jan Beulich <jbeulich@suse.com> | 2022-01-06 14:19:56 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-01-06 14:19:56 +0100 |
| commit | ffb864501ea53021f0bcedd6a8ffa440f5825efd (patch) | |
| tree | e63612f3454e42ad958b05914cc9c65902f086a1 /gas | |
| parent | f0db6fb6d964cd415b284d859d670df63b787697 (diff) | |
| download | gdb-ffb864501ea53021f0bcedd6a8ffa440f5825efd.zip gdb-ffb864501ea53021f0bcedd6a8ffa440f5825efd.tar.gz gdb-ffb864501ea53021f0bcedd6a8ffa440f5825efd.tar.bz2 | |
x86: drop NoAVX insn attribute
To avoid issues like that addressed by 6e3e5c9e4181 ("x86: extend SSE
check to PCLMULQDQ, AES, and GFNI insns"), base the check on opcode
attributes and operand types.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/config/tc-i386.c | 38 |
1 files changed, 21 insertions, 17 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 387fa60..e063268 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4986,23 +4986,27 @@ md_assemble (char *line) return; if (sse_check != check_none - && !i.tm.opcode_modifier.noavx - && !i.tm.cpu_flags.bitfield.cpuavx - && !i.tm.cpu_flags.bitfield.cpuavx512f - && (i.tm.cpu_flags.bitfield.cpusse - || i.tm.cpu_flags.bitfield.cpusse2 - || i.tm.cpu_flags.bitfield.cpusse3 - || i.tm.cpu_flags.bitfield.cpussse3 - || i.tm.cpu_flags.bitfield.cpusse4_1 - || i.tm.cpu_flags.bitfield.cpusse4_2 - || i.tm.cpu_flags.bitfield.cpupclmul - || i.tm.cpu_flags.bitfield.cpuaes - || i.tm.cpu_flags.bitfield.cpusha - || i.tm.cpu_flags.bitfield.cpugfni)) - { - (sse_check == check_warning - ? as_warn - : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); + /* The opcode space check isn't strictly needed; it's there only to + bypass the logic below when easily possible. */ + && t->opcode_modifier.opcodespace >= SPACE_0F + && t->opcode_modifier.opcodespace <= SPACE_0F3A + && !i.tm.cpu_flags.bitfield.cpusse4a + && !is_any_vex_encoding (t)) + { + bool simd = false; + + for (j = 0; j < t->operands; ++j) + { + if (t->operand_types[j].bitfield.class == RegMMX) + break; + if (t->operand_types[j].bitfield.class == RegSIMD) + simd = true; + } + + if (j >= t->operands && simd) + (sse_check == check_warning + ? as_warn + : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); } if (i.tm.opcode_modifier.fwait) |