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2024-03-22x86: fix Solaris testsuite failuresJan Beulich2-7/+4
For one 0afc614c9938 ("x86: Warn .insn instruction with length > 15 bytes") introduced a .insn use involving a slash; such tests need to have --divide passed to gas. And then 5bc71c2a6b8e ("x86-64: Add R_X86_64_CODE_6_GOTTPOFF") broke BFD_RELOC_X86_64_GOTTPOFF conversion to R_X86_64_CODE_4_GOTTPOFF, by adding respective code in a section guarded by generate_relax_relocations (the case of that not being required there was limited to 32-bit object files). Re-arrange that block of code to check generate_relax_relocations later.
2024-03-21New Romanian translation for gas sub-directoryNick Clifton1-0/+23890
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha23-0/+1119
2024-03-19LoongArch: Add relaxation for R_LARCH_CALL36mengqinggang5-147/+175
This relaxation is effective for both macro instructions (call36, tail36) and explicit relocation instructions (pcaddu18i + jirl). call36 f -> bl f R_LARCH_CALL36 -> R_LARCH_B26 tail36 $t0, f -> b f R_LARCH_CALL36 -> R_LARCH_B26
2024-03-18aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructionsYury Khrustalev9-2/+311
The following instructions are added in this patch: - ADDPT (predicated): Add checked pointer vectors (predicated). - ADDPT (unpredicated): Add checked pointer vectors (unpredicated). - SUBPT (predicated): Subtract checked pointer vectors (predicated). - SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated). - MADPT: Multiply-add checked pointer vectors, writing multiplicand - MLAPT: Multiply-add checked pointer vectors, writing addend These instructions are part of Checked Pointer Arithmetic extension and are enabled when both CPA and SVE are enabled. To achieve this, both flag "+sve" and "+cpa" should be active. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev9-0/+232
The following instructions are added in this patch: - ADDPT and SUBPT - Add/Subtract checked pointer - MADDPT and MSUBPT - Multiply Add/Subtract checked pointer These instructions are part of Checked Pointer Arithmetic extension. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. A new flag "+cpa" added to documentation. This flag enables CPA extension. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18Arm64: check matching operands for predicated B16B16 insnsJan Beulich6-36/+62
Except for bfml{a,s} their 1st and 3rd operands need to match - pass the TIED macro argument accordingly. While doing that also slightly re-arrange table entries, such that all predicated insns are close together. At the same time change the existing test source to actually use non- matching operands for the respective bfml{a,s} forms.
2024-03-18Arm64: correct B16B16 indexed bf{mla,mls,mul}Jan Beulich1-18/+18
Their index is in bits 19, 20, and 22. Bit 11 in particular is already set in the base opcode. Note also how disassembler output didn't match assembler input in the respective testcase.
2024-03-18RISC-V: Tidy smstateen and ssstateen testcases.Nelson Chu4-57/+6
gas/ * testsuite/gas/riscv/march-imply-smstateen.d: Added. * testsuite/gas/riscv/smstateen-csr-s.d: Removed. * testsuite/gas/riscv/ssstateen-csr.d: Likewise. * testsuite/gas/riscv/ssstateen-csr.s: Likewise.
2024-03-15gas/NEWS: Remove mention of AArch64 B16B16 extensionAndrew Carlotti1-3/+0
This aligns the 2.42 NEWS with the update backported to the 2.42 release branch.
2024-03-15x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich9-139/+119
Irrespective of the encoding being EVEX, the usable SIMD register range continues to be limited to %xmm0-%xmm15. Enforce this in gas (but continue to generate code, as in principle we know how to encode things) and recognize/flag the case in the disassembler. Oddly enough wrong forms were actually used in the testsuite (register- only forms are then really meaningless to test here, and are hence dropped instead of adjusted). Convert the POP2 test that needs touching anyway (due to a bad ModR/M byte having been chosen) to .insn.
2024-03-13RISC-V: Add -march=help for gasHau Hsu3-0/+126
Use -march=help for gas to print all supported extensions and versions. Here is part of the output of `as -march=help`: All available -march extensions for RISC-V: e 1.9 i 2.1, 2.0 m 2.0 a 2.1, 2.0 f 2.2, 2.0 d 2.2, 2.0 q 2.2, 2.0 c 2.0 v 1.0 h 1.0 zicbom 1.0 zicbop 1.0 ... This patch assumes that the supported extensions with the same versions are listed together. For example: static struct riscv_supported_ext riscv_supported_std_ext[] = { ... {"i", ISA_SPEC_CLASS_20191213, 2, 1, 0 }, {"i", ISA_SPEC_CLASS_20190608, 2, 1, 0 }, {"i", ISA_SPEC_CLASS_2P2, 2, 0, 0 }, ... }; For the "i" extension, 2.1.0 with different spec class are listed together. This patch records the previous printed extension and version. If the current extension and version are the same as the previous one, skip printing. bfd/ * elfxx-riscv.c (riscv_print_extensions): New function. Print available extensions and versions. * elfxx-riscv.h (riscv_print_extensions): New declaration. gas/ * gas/config/tc-riscv.c (md_parse_option): Parse 'help' keyword in -march option to print available extensions and versions. * testsuite/gas/riscv/march-help.l: New testcase for -march=help. * testsuite/gas/riscv/riscv.exp: Updated.
2024-03-12LoongArch: Scan all illegal operand instructions without interruptionLulu Cai8-7/+269
Currently, gas will exit immediately and report an error when it sees illegal operands, and will not process the remaining instructions. Replace as_fatal with as_bad to check for all illegal operands. Add test cases for illegal operands of some instructions.
2024-03-12LoongArch: Fix gas and ld test casesLulu Cai2-0/+6
* After adding the old LE relax, all old LE relocations will have an R_LARCH_RELAX relocation. Fix the gas test case failure caused by the implementation of the old LE relax. * loongarch64-elf does not support pie and -z norelro options, removed in test files.
2024-03-11x86: KeyLocker insn interaction with -msse-check / .sse_checkJan Beulich6-3/+49
Some of these have no explicit %xmm operand(s), yet they still act SSE- like (in leaveing bits 128 and up untouched). Hence they want similarly diagnosing, if that was asked for.
2024-03-11x86/APX: permit wider than 4-bit immediates with V{EXTRACT,INSERT}{F,I}128Jan Beulich1-1/+3
These aren't useful, but can be encoded for their AVX forms and hence should also be permitted for the APX surrogates. Extend the respective conditional by a base opcode check, to restrict it to VROUND{P,S}{S,D}.
2024-03-11x86: don't open-code REG_{SP,FP}Jan Beulich1-2/+2
Since we have the #define-s, we should also use them.
2024-03-08gas: Fix x86 build with GCC 6.4H.J. Lu1-1/+1
Add "()" to silence GCC 6.4: .../gas/config/tc-i386.c: In function ‘x86_ginsn_lea’: .../gas/config/tc-i386.c:5738:19: error: logical not is only applied to the left hand side of comparison [-Werror=logical-not-parentheses] if (!i.base_reg != (!i.index_reg || i.index_reg->reg_num == RegIZ)) ^~ cc1: all warnings being treated as errors PR gas/31464 * config/tc-i386.c (x86_ginsn_lea): Add "()" to silence GCC 6.4.
2024-03-08RISC-V: Support Zabha extension.Jiawei3-0/+235
The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-03-06LoongArch: Fix some test cases for TLS transition and relaxLulu Cai10-46/+41
2024-03-06LoongArch: Delete extra instructions when TLS type transitionLulu Cai1-5/+26
This modification mainly changes the timing of type transition, adds relaxation to the old LE instruction sequence, and fixes bugs in extreme code models. We strictly distinguish between type transition and relaxation. Type transition is from one type to another, while relaxation is the removal of instructions under the same TLS type. Detailed instructions are as follows: 1. For type transition, only the normal code model of DESC/IE does type transition, and each relocation is accompanied by a RELAX relocation. Neither abs nor extreme will do type transition, and no RELAX relocation will be generated. The extra instructions when DESC transitions to other TLS types will be deleted during the type transition. 2. Implemented relaxation for the old LE instruction sequence. The first two instructions of LE's 32-bit and 64-bit models use the same relocations and cannot be distinguished based on relocations. Therefore, for LE's instruction sequence, any code model will try to relax. 3. Some function names have been adjusted to facilitate understanding, parameters have been adjusted, and unused macros have been deleted.
2024-03-05LoongArch: Add gas testsuit for LA32 relocationsLulu Cai2-0/+136
Test the relocation of the LA32 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA64 relocationsLulu Cai2-0/+253
Test the relocation of the LA64 instruction set.
2024-03-05LoongArch: Add gas testsuit for LA32 int/float instructionsLulu Cai4-0/+609
Test the int/float instructions of LA32.
2024-03-05LoongArch: Add gas testsuit for LA64 int/float instructionsLulu Cai4-0/+1192
Test the int/float instructions of LA64.
2024-03-05LoongArch: Add gas testsuit for lsx/lasx instructionsLulu Cai4-0/+2938
Test the LSX/LASX instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for lbt/lvz instructionsLulu Cai4-0/+382
Test the LBT/LVZ instructions. Only LA64 supports these instructions.
2024-03-05LoongArch: Add gas testsuit for alias instructionsLulu Cai4-0/+60
Test the alias instructions.
2024-03-01s390: Be more verbose about missing operand typeJens Remus3-18/+54
Provide expected operand type in s390-specific assembler operand parsing error message: "error: operand <operand-number>: missing <operand-type> operand" With <operand-type> being one of: - base register - displacement - [vector] index register - length - access register - control register - floating-point register - general-purpose register - vector register - [un]signed number gas/ * config/tc-s390.c: Provide missing operand type in error message. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case result validation patterns to operand number in operand syntax error messages. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Provide operand number in assembler warning and error messagesJens Remus6-165/+206
Prepend the operand number "operand %d:" to the s390-specific assembler operand parsing warning and error messages. While at it reword the custom operand out of range error message text to be closer to the one used by as_bad_value_out_of_range(). Additionally reword the invalid FPR pair warning message to make it nicer. gas/ * config/tc-s390.c: Print operand number in error messages. * testsuite/gas/s390/zarch-base-index-0-err.l: Update test case verification patterns to accept syntax error messages now containing the operand number. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. * testsuite/gas/s390/zarch-z900-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Allow to explicitly omit base register operand in assemblyJens Remus10-165/+120
The base register operand B may be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may be omitted in D(X,B) by coding D(B) or explicitly omitted by coding D(,B). In both cases the omitted base register operand value defaults to zero. Allow to explicitly omit the base register operand B in D(X,B) and D(L,B) by coding D(X,) and D(L,). Default the omitted base register operand value to zero. gas/ * config/tc-s390.c: Allow to explicitly omit the base register operand in assembly. * NEWS: Mention that the base register now may be omitted on s390. * gas/testsuite/gas/s390/zarch-base-index-0.s: Update test cases for change to allow to explicitly omit the base register operand in assembly. * gas/testsuite/gas/s390/zarch-base-index-0.d: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.s: Likewise. * gas/testsuite/gas/s390/zarch-base-index-0-err.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Print base register 0 as "0" in disassemblyJens Remus2-35/+35
Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus12-22/+204
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Revise s390-specific assembler option descriptionsJens Remus1-10/+18
Reorder, reword, and complete the s390-specific option descriptions. Align the formatting of s390-specific assembler options to that of the general assembler options in "as --help". While at it change a warning message to use the term "z/Architecture" instead of the deprecated "esame" (ESA Modal Extensions or ESAME) one. gas/ * config/tc-s390.c: Revise s390-specific assembler option descriptions. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test case for disassembler option warn-areg-zeroJens Remus3-0/+182
gas/ * testsuite/gas/s390/s390.exp: Add test cases for s390-specific assembler option "warn-areg-zero". * testsuite/gas/s390/zarch-warn-areg-zero.s: Likewise. * testsuite/gas/s390/zarch-warn-areg-zero.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test cases for base/index register 0Jens Remus5-0/+394
While at it add comments to logic to omit base and/or index register 0 in s390 disassembly. opcodes/ * s390-dis.c: Add comments related to omitting base and/or index register 0 in disassembly. gas/ * testsuite/gas/s390/s390.exp: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.s: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.d: Likewise. * testsuite/gas/s390/zarch-base-index-0-err.s: Add error test cases for base and/or index register 0. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add comments to assembler operand parsing logicJens Remus1-6/+25
gas/ * config/tc-s390.c: Add comments to assembler operand parsing logic. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Assemble processor specific test cases for their processorJens Remus1-2/+2
Assemble the esa-g5 test case with -march=g5. Assemble the zarch-z900 test case with -march=z900. gas/ * testsuite/gas/s390/s390.exp: Assemble processor specific test cases for their respective processor (-march=<processor>). Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Correct setting of highgprs flag in ELF outputJens Remus10-6/+143
The combination of an architecture size of 32 bits and z/Architecture mode requires the highgprs flag to be set in the ELF output. It causes the high-halves of the general purpose registers (GPRs) to be preserved at run-time, so that the code can use 64-bit GPRs. The architecture size of 32 bits can either be the default in case of a default architecture name of "s390" or due to specification of the option -m31 (to generate the 31-bit file format). The z/Architecture mode can either be the default or due to specification of the option -mzarch (to assemble for z/Architecture mode). It can also be selected using the pseudo commands ".machinemode zarch" and ".machinemode zarch_nohighgprs". The latter not causing the highgprs flag to be set. The highgprs flag was only set when the following s390-specific assembler options were given in the following specific order: "-m31 -mzarch". The highgprs flag was erroneously not set when: - the order of above options was inverse (i.e. "-mzarch -m31"), - the architecture mode defaulted to z/Architecture mode and option "-m31" was specified, - the architecture size defaulted to 32 bits due to a default architecture name of "s390" and option -mzarch was specified, - the architecture size defaulted to 32 bits and the architecture mode defaulted to z/Architecture due to the specified processor (e.g. "-march=z900" or follow-on processor). Determine whether to set the highgprs flag in init_default_arch() after having processed all assembler options in md_parse_option(). This ensures the flag is set in all of the above cases it was erroneously not set. Add test cases for highgprs flag, including ones that use .machinemode to switch the architecture mode. gas/ * config/tc-s390.c: Correct setting of highgprs flag in ELF output. * testsuite/gas/s390/s390.exp: Add test cases for highgprs flag. * testsuite/gas/s390/blank.s: Empty assembler source used in test cases for "highgprs" flag. * testsuite/gas/s390/esa-highgprs-0.d: Add test case for highgprs flag. * testsuite/gas/s390/zarch-highgprs-0.d: Likewise. * testsuite/gas/s390/zarch-highgprs-1.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-0.s: Add test case for highgprs flag when using .machinemode to switch architecture mode. * testsuite/gas/s390/esa-highgprs-machinemode-0.d: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.s: Likewise. * testsuite/gas/s390/esa-highgprs-machinemode-1.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Do not erroneously use base operand value for length operandJens Remus6-17/+110
The base register operand B may optionally be omitted in D(B) by coding D and in D(L,B) by coding D(L). The index register operand X may optionally be omitted in D(X,B) by coding D(,B) or D(B). Both base and index register operands may optionally be omitted in D(X,B) by coding D. In any case the omitted base and/or index register operand value defaults to zero. When parsing an erroneously omitted length L operand in D(L,B) by coding D(,B) the base register operand B was erroneously consumed as length operand. When using a register name for the base register operand this was detected and reported as error. But when not using a register name the base register operand value was erroneously used as length operand value. Correct the parsing of an omitted optional base or index register to not erroneously use the base register operand value as length, when erroneously omitting the length operand. While at it rename the variable used to remember whether the base or index register operand was omitted to enhance code readability. Additionally add test cases for the optional omission of base and/or index register operands. Example assembler source: mvc 16(1,%r1),32(%r2) mvc 16(1),32(%r2) mvc 16(,1),32(%r2) # undetected syntax error Disassembly of bad assembly without commit shows the base register operand value was erroneously used as length operand value: 0: d2 00 10 10 20 20 mvc 16(1,%r1),32(%r2) 6: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) c: d2 00 00 10 20 20 mvc 16(1,%r0),32(%r2) Assembler messages with commit: 3: Error: operand 1: missing operand gas/ * config/tc-s390.c: Correct parsing of omitted base register. * testsuite/gas/s390/s390.exp: Add test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index.s: Test cases for omitted optional base or index register. * testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. * testsuite/gas/s390/zarch-omitted-base-index-err.s: Test cases for omitted base and/or index register. * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Enhance handling of syntax errors in assemblerJens Remus1-2/+4
Do not consume any unexpected character including newline ('\n') when detecting a syntax error when parsing an operand block with parenthesis. This resolves the unfavorable assembler messages from the example below, including consuming the newline at the end of the current statement and reporting the next statement as junk. While at it change the only pre-increment of the current instruction string pointer into a post-increment to align with the other instances. Example assembler source: mvi 16(),32 # syntax error a %r1,16(%r2 # syntax error a %r1,16(%r2) mvc 16(1,),32(%r2) # syntax error mvc 16(1,%r1,32(%r2 # syntax error Assembler messages without commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 1: Error: syntax error; expected ',' 1: Error: junk at end of line: `32' 2: Error: syntax error; missing ')' after base register 2: Error: junk at end of line: `a %r1,16(%r2)' 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 4: Error: syntax error; expected ',' 4: Error: operand out of range (32 is not between 0 and 15) 4: Error: syntax error; missing ')' after base register 4: Error: junk at end of line: `%r2)' 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; expected ',' 5: Error: operand out of range (32 is not between 0 and 15) 5: Error: syntax error; missing ')' after base register 5: Error: junk at end of line: `%r2' Assembler messages with commit: 1: Error: bad expression 1: Error: syntax error; missing ')' after base register 2: Error: syntax error; missing ')' after base register 4: Error: bad expression 4: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register 5: Error: syntax error; missing ')' after base register gas/ * config/tc-s390.c: Do not erroneously consume newline when parsing an addressing operand with parentheses. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Lower severity of assembler syntax errors from fatal to errorJens Remus2-7/+7
Report s390 assembler syntax errors as error instead of fatal error. This allows the assembler to continue and potentially report further syntax errors in the source. This should not cause syntax errors to be erroneously accepted, as both error and fatal error cause the assembler to return with a non-zero return code. The following syntax errors are changed from fatal to error: - invalid length field specified - odd numbered general purpose register specified as register pair - invalid floating point register pair. Valid fp register pair operands are 0, 1, 4, 5, 8, 9, 12 or 13. gas/ * config/tc-s390.c: Lower severity of assembler syntax errors from fatal to error. * testsuite/gas/s390/zarch-z9-109-err.l: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01x86: adjust which Dwarf2 register numbers to useJan Beulich2-23/+9
Consumers can't know which execution mode is in effect for a certain piece of code; they can only go from object file properties. Hence which register numbers to encode ought to depend solely on object file type. In tc_x86_frame_initial_instructions() do away with parsing a register name: We have a symbolic constant already for the 64-bit case, and the 32-bit number isn't going to change either. Said constant's definition needs moving, though, to be available also for non-ELF. While moving also adjust the comment to clarify that it's applicable to 64-bit mode only.
2024-03-01gas/NEWS: drop mention of Arm64's SVE2.1 and SME2.1Jan Beulich1-5/+1
... plus the SME part of B16B16. As per https://sourceware.org/pipermail/binutils/2024-February/132408.html SVE2.1 support is both incomplete and buggy. SME2.1 "support" goes as far as a single instruction (a subset of movaz forms) only. The SME part of B16B16 is entirely missing.
2024-03-01x86/APX: honor -mevexwig= for byte-size insnsJan Beulich3-0/+171
These uniformly ignore EVEX.W, and hence what we emit ought to be controllable by the command line option.
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich3-0/+76
While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately.
2024-03-01x86/APX: correct .insn opcode space determination when REX2 is neededJan Beulich4-28/+97
In this case spaces 0f38 and 0f3a may not be put in place. To achieve the intended effect, operand parsing (but not operand processing) needs pulling ahead, so we know whether eGRP-s are in use.
2024-03-01x86/APX: respect {vex}/{vex3}Jan Beulich4-137/+234
Even when an EVEX encoding is available, use of such a prefix ought to be respected (resulting in an error) rather than ignored. As requested during review already, introduce a new encoding enumerator to record use of eGPR-s, and update state transitions accordingly. The optimize_encoding() change also addresses an internal assembler error that was previously raised when respective memory operands used eGPR-s for addressing. While this results in a change of diagnostic issued for VEX-encoded insns, the new one is at least no worse than the prior one.
2024-02-29aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.Srinath Parvathaneni3-49/+49
The assembler wrongly expects plain register name instead of memory-form 2nd operand for gcsstr and gcssttr instructions. This patch fixes the issue.
2024-02-29RISC-V: Add assembly support for TLSDESC.Tatsuyuki Ishi3-5/+73
gas/ * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype renamed to percent_op_relax_only as this matcher is extended to handle jalr as well which is not R-type. (riscv_ip): Apply the percent_op_relax_only rename and update comment. (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to TLS relocation check list. * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation generation. opcodes/ * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with %tlsdesc_call annotations.
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