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2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+241
2018-03-07x86: Rewrite NOP generation for fill and alignmentH.J. Lu1-3/+4
2018-02-27gas: Rename .nop directive to .nopsH.J. Lu1-4/+4
2018-02-27x86: Add -O[2|s] assembler command-line optionsH.J. Lu1-0/+25
2018-02-26GAS/doc: Clean up `.dc' and `.ds' directive descriptionsMaciej W. Rozycki1-5/+4
2018-02-26Fix typo in documentation of assembler's .dc directive.Nick Clifton1-1/+1
2018-02-23Document the assembler's .dc, .dcb and .ds directives.Nick Clifton1-5/+103
2018-02-22x86: Add {rex} pseudo prefixH.J. Lu1-0/+5
2018-02-20Clarify .arch_extension possible valuesThomas Preud'homme1-1/+1
2018-02-17Add .nop assembler directiveH.J. Lu1-0/+18
2018-01-23Enable Intel PCONFIG instruction.Igor Tsimbalist1-1/+2
2018-01-23Enable Intel WBNOINVD instruction.Igor Tsimbalist1-0/+2
2018-01-22GAS/doc: Correct `.set nomips16e2' directive description syntaxMaciej W. Rozycki1-2/+2
2018-01-17Replace CET bit with IBT and SHSTK bits.Igor Tsimbalist1-3/+3
2018-01-08Add a description of the X86_64 assembler's .largcomm pseudo-op.Nick Clifton1-1/+10
2018-01-03Update year range in copyright notice of binutils filesAlan Modra65-67/+67
2017-12-04Documentation fixAlan Modra1-1/+1
2017-12-03Fix for texinfo 4.8.Jim Wilson1-2/+1
2017-12-01Update and clean up RISC-V gas documentation.Jim Wilson2-19/+123
2017-11-29In x86 -n docs, mention that you need an explicit nop fill byte.Jim Wilson1-1/+2
2017-11-22Update docs on filling text with nops.Jim Wilson1-3/+3
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-0/+3
2017-11-16Update documentation for Arvm8.4-A changes to AArch64.Tamar Christina1-3/+11
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-0/+2
2017-11-08Adds command line support for Armv8.4-A, via the new command line option -mar...Jiong Wang1-0/+1
2017-11-03Add option for Qualcomm Saphira partSiddhesh Poyarekar1-0/+1
2017-10-23Enable Intel AVX512_BITALG instructions.Igor Tsimbalist1-0/+3
2017-10-23Enable Intel AVX512_VNNI instructions.Igor Tsimbalist1-1/+3
2017-10-23Enable Intel VPCLMULQDQ instruction.Igor Tsimbalist1-1/+2
2017-10-23Enable Intel VAES instructions.Igor Tsimbalist1-0/+2
2017-10-23Enable Intel GFNI instructions.Igor Tsimbalist1-1/+2
2017-10-23Enable Intel AVX512_VBMI2 instructions.Igor Tsimbalist1-2/+4
2017-10-20Improve handling of REPT pseudo op with a negative count.Nick Clifton1-0/+3
2017-08-29Improve MSP430 section placement.Jozef Lawrynowicz1-0/+13
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov2-1/+4
2017-08-15[Patch AArch64] Turn lr, fp, ip0 and ip1 into proper aliasesRamana Radhakrishnan1-0/+3
2017-07-21This patch introduces support for specifing views in .loc directives, so that...Alexandre Oliva1-0/+13
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel2-2/+2
2017-07-17Update assembler documentation on some AVR cores.Georg-Johann Lay1-3/+6
2017-07-05[ARM] Add support for Cortex-A55 and Cortex-A75.James Greenhalgh1-0/+2
2017-06-30Add support for a __gcc_isr pseudo isntruction to the AVR assembler.Georg-Johann Lay1-0/+62
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+2
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-0/+1
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+1
2017-06-24[ARM] Add support for ARM Cortex-R52 processorThomas Preud'homme1-0/+1
2017-06-24[ARM] Add support for ARMv8-R in assembler and readelfThomas Preud'homme1-0/+1
2017-06-21Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 archite...James Greenhalgh1-0/+2
2017-06-05Drop arm support for falkor/qdf24xx targets, not present in released hardware.Jim Wilson1-2/+0
2017-05-19binutils: support for the SPARC M8 processorJose E. Marchesi1-9/+19
2017-05-15MIPS16e2: Add MIPS16e2 ASE supportMaciej W. Rozycki2-0/+23
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