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2022-07-06x86: make D attribute usable for XOP and FMA4 insnsJan Beulich1-7/+35
This once again allows to reduce redundancy in (and size of) the opcode table. Don't go as far as also making D work on the two 5-operand XOP insns: This would significantly complicate the code, as there the first (immediate) operand would need special treatment in several places. Note that the .s suffix isn't being enabled to have any effect, for being deprecated. Whereas neither {load} nor {store} pseudo prefixes make sense here, as the respective operands are inputs (loads) only anyway, regardless of order. Hence there is (as before) no way for the programmer to request the alternative encoding to be used for register- only insns. Note further that it is always the first original template which is retained (and altered), to make sure the same encoding as before is used for register-only insns. This has the slightly odd (but pre- existing) effect of XOP register-only insns having XOP.W clear, but FMA4 ones having VEX.W set.
2022-07-06x86: fold two switch() statements in match_template()Jan Beulich1-16/+3
I don't see why two of them were introduced (very long ago) using similar fall-through logic.
2022-07-06x86: fix 3-operand insn reverse-matchingJan Beulich1-2/+4
The middle operand would have gone entirely unchecked, allowing e.g. vmovss %xmm0, %esp, %xmm2 to assemble successfully, or e.g. vmovss %xmm0, $4, %xmm2 causing an internal error. Alongside dealing with this also drop a related comment, which hasn't been applicable anymore since the introduction of 3-operand patterns with D set (and which perhaps never had been logical to be there, as reverse-matched insns don't make it there in the first place).
2022-07-06x86: introduce a state stack for .archJan Beulich1-1/+80
When using just slightly non-trivial combinations of .arch, it can be quite useful to be able to go back to prior state without needing to re-invoke perhaps many earlier directives and without needing to invoke perhaps many "negative" ones. Like some other architectures allow saving (pushing) and restoring (popping) present/prior state. For now require the same .code<N> to be in effect for ".arch pop" that was in effect for the corresponding ".arch push". Also change the global "no_cond_jump_promotion" to be bool, to match the new struct field.
2022-07-06x86: generalize disabling of sub-architecturesJan Beulich1-235/+179
I never really understood upon what basis ".arch .no*" options were made available. Let's not have any "criteria" at all, and simply allow disabling of all of them. Then we also have all data for a sub-arch in a single place, as we now only need a single table.
2022-07-06x86: permit "default" with .archJan Beulich1-7/+49
So far there was no way to reset the architecture to that assembly would start with in the absence of any overrides (command line or directives). Note that for Intel MCU "default" is merely an alias of "iamcu". While there also zap a stray @item from the doc section, as noticed when inspecting the generated output (which still has some quirks, but those aren't easy to address without re-flowing almost the entire section).
2022-07-06x86: don't leak sub-architecture accumulated stringsJan Beulich1-0/+3
While it may not be necessary in i386_target_format() (but then setting the variable to NULL also wouldn't be necessary), at least in the other cases strings may already have accumulated.
2022-07-05x86: introduce fake processor type to mark sub-arch entries in cpu_arch[]Jan Beulich2-4/+10
This is in preparation of dropping the leading . from the strings. While there also move PROCESSOR_GENERIC{32,64} from the middle of AMD entries to near the top.
2022-07-05x86: macro-ize cpu_arch[] entriesJan Beulich1-308/+164
Putting individual elements behind macros, besides (imo) improving readability, will make subsequent (and likely also future) changes less intrusive. Utilize this right away to pack the table a little more tightly, by converting "skip" to bool and putting it earlier in a group of bitfields together with "len".
2022-07-05x86: de-duplicate sub-architecture strings accumulationJan Beulich1-38/+14
Introduce a helper function to replace 4 instances of similar code. Use reconcat() to cover the previously explicit free().
2022-07-04x86: fold Disp32S and Disp32Jan Beulich2-75/+42
The only case where 64-bit code uses non-sign-extended (can also be considered zero-extended) displacements is when an address size override is in place for a memory operand (i.e. particularly excluding displacements of direct branches, which - if at all - are controlled by operand size, and then are still sign-extended, just from 16 bits). Hence the distinction in templates is unnecessary, allowing code to be simplified in a number of places. The only place where logic becomes more complicated is when signed-ness of relocations is determined in output_disp(). The other caveat is that Disp64 cannot be specified anymore in an insn template at the same time as Disp32. Unlike for non-64-bit mode, templates don't specify displacements for both possible addressing modes; the necessary adjustment to the expected ones has already been done in match_template() anyway (but of course the logic there needs tweaking now). Hence the single template so far doing so is split.
2022-07-04x86: restore masking of displacement kindsJan Beulich1-16/+15
Commit 7d5e4556a375 rendered the check near the end of what is now i386_finalize_displacement() entirely dead for AT&T mode, since for operands involving a displacement .unspecified will always be set. But the logic there is bogus anyway - Intel syntax operand size specifiers are of no interest there either. The only thing which matters in the "displacement only" determination is .baseindex. Of course when masking displacement kinds we should not at the same time also mask off other attributes. Furthermore the type mask returned by lex_got() also needs to be adjusted: The only case where we want Disp32 (rather than Disp32S) is when dealing with 32-bit addressing mode in 64-bit code.
2022-07-04x86-64: improve handling of branches to absolute addressesJan Beulich1-2/+6
There are two related problems here: The use of "addr32" on a direct branch would, besides causing a warning, result in operands to be permitted which mistakenly are refused without "addr32". Plus at some point not too long ago I'm afraid it may have been me who regressed the relocation addends emitted for such branches. Correct both problems, adding a testcase to guard against regressing this again.
2022-06-29opcodes/aarch64: split off creation of comment text in disassemblerAndrew Burgess1-1/+11
The function aarch64_print_operand (aarch64-opc.c) is responsible for converting an instruction operand into the textual representation of that operand. In some cases, a comment is included in the operand representation, though this (currently) only happens for the last operand of the instruction. In a future commit I would like to enable the new libopcodes styling for AArch64, this will allow objdump and GDB[1] to syntax highlight the disassembler output, however, having operands and comments combined in a single string like this makes such styling harder. In this commit, I propose to extend aarch64_print_operand to take a second buffer. Any comments for the instruction are written into this extra buffer. The two callers of aarch64_print_operand are then updated to pass an extra buffer, and print any resulting comment. In this commit no styling is added, that will come later. However, I have adjusted the output slightly. Before this commit some comments would be separated from the instruction operands with a tab character, while in other cases the comment was separated with two single spaces. After this commit I use a single tab character in all cases. This means a few test cases needed updated. If people would prefer me to move everyone to use the two spaces, then just let me know. Or maybe there was a good reason why we used a mix of styles, I could probably figure out a way to maintain the old output exactly if that is critical. Other than that, there should be no user visible changes after this commit. [1] GDB patches have not been merged yet, but have been posted to the GDB mailing list: https://sourceware.org/pipermail/gdb-patches/2022-June/190142.html
2022-06-28RISC-V: Add 'Sstc' extension and its CSRsTsukasa OI1-0/+14
This commit adds "stimecmp / vstimecmp" Extension (Sstc) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sstc' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sstc' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_STIMECMP, CSR_STIMECMPH, CSR_VSTIMECMP, CSR_VSTIMECMPH): New CSR macros.
2022-06-28RISC-V: Add 'Sscofpmf' extension with its CSRsTsukasa OI1-0/+8
This commit adds Count Overflow and Mode-Based Filtering Extension (Sscofpmf) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Sscofpmf' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Sscofpmf' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTOVF, CSR_MHPMEVENT3H, CSR_MHPMEVENT4H, CSR_MHPMEVENT5H, CSR_MHPMEVENT6H, CSR_MHPMEVENT7H, CSR_MHPMEVENT8H, CSR_MHPMEVENT9H, CSR_MHPMEVENT10H, CSR_MHPMEVENT11H, CSR_MHPMEVENT12H, CSR_MHPMEVENT13H, CSR_MHPMEVENT14H, CSR_MHPMEVENT15H, CSR_MHPMEVENT16H, CSR_MHPMEVENT17H, CSR_MHPMEVENT18H, CSR_MHPMEVENT19H, CSR_MHPMEVENT20H, CSR_MHPMEVENT21H, CSR_MHPMEVENT22H, CSR_MHPMEVENT23H, CSR_MHPMEVENT24H, CSR_MHPMEVENT25H, CSR_MHPMEVENT26H, CSR_MHPMEVENT27H, CSR_MHPMEVENT28H, CSR_MHPMEVENT29H, CSR_MHPMEVENT30H, CSR_MHPMEVENT31H): New CSR macros.
2022-06-28RISC-V: Add 'Smstateen' extension and its CSRsTsukasa OI1-0/+14
This commit adds State Enable Extension (Smstateen) and its CSRs. bfd/ChangeLog: * elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smstateen' extension to valid 'S' extension list. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): Add CSR classes for 'Smstateen' extension. (riscv_csr_address): Add handling for new CSR classes. * testsuite/gas/riscv/csr-dw-regnums.s: Add new CSRs. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr.s: Add new CSRs. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Likewise. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. include/ChangeLog: * opcode/riscv-opc.h (CSR_MSTATEEN0, CSR_MSTATEEN1, CSR_MSTATEEN2, CSR_MSTATEEN3, CSR_SSTATEEN0, CSR_SSTATEEN1, CSR_SSTATEEN2, CSR_SSTATEEN3, CSR_HSTATEEN0, CSR_HSTATEEN1, CSR_HSTATEEN2, CSR_HSTATEEN3, CSR_MSTATEEN0H, CSR_MSTATEEN1H, CSR_MSTATEEN2H, CSR_MSTATEEN3H, CSR_HSTATEEN0H, CSR_HSTATEEN1H, CSR_HSTATEEN2H, CSR_HSTATEEN3H): New CSR macros.
2022-06-28RISC-V: Add new CSR feature gate handling (RV32,H)Tsukasa OI1-4/+7
To support feature gate like Smstateen && H, this commit adds certain CSR feature gate handling. It also changes how RV32-only CSRs are handled for cleanliness. gas/ChangeLog: * config/tc-riscv.c (riscv_csr_address): Add CSR feature gate handling for H. Change handling on RV32.
2022-06-27drop XC16x bitsJan Beulich2-409/+0
Commit 04f096fb9e25 ("Move the xc16x target to the obsolete list") moved the architecture from the "obsolete but still available" to the "obsolete / support removed" list in config.bfd, making the architecture impossible to enable (except maybe via "enable everything" options"). Note that I didn't touch */po/*.po{,t} on the assumption that these would be updated by some (half)automatic means.
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu1-1/+9
According to the picture 28.1 in the current ISA spec, h is no larger the multi-letter extension, it is a single extension after v. Therefore, this patch fix the implementation, and use the single h to control hypervisor CSRs and instructions, which we promised to do before. bfd/ * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v. (riscv_supported_std_h_ext): Removed. (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed. (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H. (parse_config): Updated since riscv_prefix_ext_class is removed. (riscv_recognized_prefixed_ext): Likewise. (riscv_get_default_ext_version): Likewise. (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for hypervisor CSRs. (riscv_csr_address): Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are controlled by single h extension for now. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise. * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise. * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no longer multi-letter extension. * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise. include/ * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than the privileged spec verisons. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H. opcodes/ * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
2022-06-22RISC-V: Fix inconsistent error message (range)Tsukasa OI1-1/+1
This commit fixes inconsistent error message format involving compressed funct<n> fields. In specific, funct6 had an error message with range 0..2^<n> ("0..64") unlike other funct<n> fields with 0..2^<n>-1 (e.g. funct4 with "0..15"). gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Fix inconsistent error message.
2022-06-17PR29256, memory leak in obj_elf_section_nameAlan Modra1-14/+18
When handling section names in quotes obj_elf_section_name calls demand_copy_C_string, which puts the name on the gas notes obstack. Such strings aren't usually freed, since obstack_free frees all more recently allocated objects as well as its arg. When handling non-quoted names, obj_elf_section_name mallocs the name. Due to the mix of allocation strategies it isn't possible for callers to free names, if that was desirable. Partially fix this by always creating names on the obstack, which is more efficient anyway. (You still can't obstack_free on error paths due to the xtensa tc_canonicalize_section_name.) Also remove a couple of cases where the name is dup'd for no good reason as far as I know. PR 29256 * config/obj-elf.c (obj_elf_section_name): Create name on notes obstack. (obj_elf_attach_to_group): Don't strdup group name. (obj_elf_section): Likewise. (obj_elf_vendor_attribute): Use xmemdup0 rather than xstrndup.
2022-06-14BFD_RELOC_MIPS_16Alan Modra1-8/+8
MIPS should not be using BFD_RELOC_16 for its R_MIPS_16 relocation, since R_MIPS_16 specifies a 16-bit field in a 32-bit word. BFD_RELOC_16, emitted by generic code to handle fixups on 16-bit data directives, expects fixups to operate on the whole of a 16-bit word. This patch corrects the problem by using BFD_RELOC_MIPS_16, a new bfd reloc that is used to generate R_MIPS_16. BFD_RELOC_16 is handled in md_apply_fix for cases where the fixup can be applied at assembly time. Like BFD_RELOC_8, BFD_RELOC_16 now has no corresponding object file relocation, and thus .half, .hword, .short and .dc.w must be resolved at assembly time. BFD_RELOC_MIPS_REL16 is removed by this patch since it isn't used. PR 3243 PR 26542 * reloc.c (BFD_RELOC_MIPS_16): Rename from BFD_RELOC_MIPS_REL16. * elf32-mips.c (mips_reloc_map): Map BFD_RELOC_MIPS_16 to R_MIPS_16. * elf64-mips.c (mips_reloc_map): Likewise, delete BFD_RELOC_MIPS_REL16. * elfn32-mips.c (mips_reloc_map): Likewise. * libbfd.h: Regenerate. * bfd-in2.h: Regenerate. gas/ * config/tc-mips.c (append_insn): Handle BFD_RELOC_MIPS_16. (macro_build): Likewise. (mips_percent_op <%half>): Generate BFD_RELOC_MIPS_16. (md_apply_fix): Handle BFD_RELOC_16 and BFD_RELOC_MIPS_16 when fx_done. ld/ * testsuite/ld-mips-elf/reloc-local-overflow.d, * testsuite/ld-mips-elf/reloc-local-overflow.s: Rewrite.
2022-06-14gas dwarf2dbg.c tidyAlan Modra1-2/+2
Make it a little more obvious that remap_debug_filename returns an allocated string (that should be freed) by returning a char * rather than const char *. Free a few missed cases in dwarf2dbg.c, and free other memory allocated in dwarf2dbg.c. Also remove static initialisation of variables and initialise in dwarf2_init instead, in order to ensure gas state is saner for oss-fuzz. * remap.c (remap_debug_filename): Remove const from return. * as.h (remap_debug_filename): Update prototype. * config/obj-elf.c (obj_elf_ident): Simplify free of remap_debug_filename output. * stabs.c (stabs_generate_asm_file): Likewise. * dwarf2dbg.c (dirs, dirs_in_use, dirs_allocated, current): Don't initialise statically.. (dwarf2_init): ..do so here, along with most other static vars. (assign_file_to_slot): Don't set files_allocated until we succeed in allocating memory. (purge_generated_debug): Add bool param, free more stuff if true. (dwarf2_directive_filename): Adjust purge_generated_debug call. (process_entries): Don't free line_entry here.. (dwarf2_cleanup): ..do so here instead, new function. (dwarf2_finish): Call dwarf2_cleanup. When chaining together subseg line entries, unhook entries from old subseg list. (dwarf2_directive_loc): Free remap_debug_filename string. (out_dir_and_file_list): Likewise. (out_debug_str): Likewise.
2022-06-03Re: ubsan: undefined shift in frag_align_codeAlan Modra1-1/+2
This one needs the same fix too. * config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Avoid signed integer overflow.
2022-06-03x86: exclude certain ISA extensions from v3/v4 ISAJan Beulich1-4/+7
Like TBM and LWP, XOP and FMA4 also shouldn't be included in v3. Like AVX512-4VNNIW, AVX512-4FMAPS also shouldn't be included in v4.
2022-05-31ia64 gas: Remove unnecessary initAlan Modra1-2/+0
The whole struct is cleared by alloc_record. * config/tc-ia64.c (output_prologue, output_prologue_gr): Don't zero r.record.r.mask.
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra8-70/+55
Requiring C99 means that uses of bfd_uint64_t can be replaced with uint64_t, and similarly for bfd_int64_t, BFD_HOST_U_64_BIT, and BFD_HOST_64_BIT. This patch does that, removes #ifdef BFD_HOST_* and tidies a few places that print 64-bit values.
2022-05-27x86/Intel: allow MASM representation of embedded rounding / SAEJan Beulich2-22/+38
MASM doesn't support the separate operand form; the modifier belongs after the instruction instead. Accept this form alongside the original (now legacy) one. Short of having access to a MASM version to actually check in how far "after the instruction" is a precise statement in their documentation, allow both that and the SDM mandated form where the modifier is on the last register operand (with a possible immediate operand following). Sadly the split out function, at least for the time being, needs to cast away constness at some point, as the two callers disagree in this regard. Adjust some, but not all of the testcases.
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich2-72/+73
As a preparatory step to allowing proper non-operand forms of specifying embedded rounding / SAE, convert the internal representation to non- operand form. While retaining properties (and in a few cases perhaps providing more meaningful diagnostics), this means doing away with a few hundred standalone templates, thus - as a nice side effect - reducing memory consumption / cache occupancy.
2022-05-27x86/Intel: allow MASM representation of embedded broadcastJan Beulich2-12/+104
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Accept these forms alongside the original (now legacy) ones. Acceptance of the original {1to<n>} operand suffix is retained both for backwards compatibility and to disambiguate VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes. I have no insight (yet) into how MASM expects those to be disambiguated. Adjust some, but not all of the testcases.
2022-05-26 arm: avoid use of GNU builtin function in s_arm_unwind_save_mixedRichard Earnshaw1-40/+17
Whilst reviewing Luis' proposed change to s_arm_unwind_save_mixed yesterday I noticed that we were making use of __builting_clzl directly within the main function, which is not guaranteed to be portable. Whilst studying the code further, I also realized that it could be rewritten without using it and also reworked to remove a lot of unnecessary iterations steps. So this patch does that (and also removes the source of the warning that Luis was trying to fix). Finally, with the rewrite we can also simplify the caller of this routine as the new version can handle all the cases directly. * config/tc-arm.c (s_arm_unwind_save_mixed): Rewrite without using __builtin_clzl. (s_arm_unwind_save): Simplify logic for simple/mixed register saves.
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-6/+6
With the upcoming SVP64 extension[0] to PowerPC architecture, it became evident that PowerPC operand indices no longer fit 8 bits. This patch switches the underlying type to uint16_t, also introducing a special typedef so that any future extension goes even smoother. [0] https://libre-soc.org include/ * opcode/ppc.h (ppc_opindex_t): New typedef. (struct powerpc_opcode): Use it. (PPC_OPINDEX_MAX): Define. gas/ * write.h (struct fix): Increase size of fx_pcrel_adjust. Reorganise. * config/tc-ppc.c (insn_validate): Use ppc_opindex_t for operands. (md_assemble): Likewise. (md_apply_fix): Likewise. Mask fx_pcrel_adjust with PPC_OPINDEX_MAX. (ppc_setup_opcodes): Adjust opcode index assertion. opcodes/ * ppc-dis.c (skip_optional_operands): Use ppc_opindex_t for operand pointer. (lookup_powerpc, lookup_prefix, lookup_vle, lookup_spe2): Likewise. (print_insn_powerpc): Likewise.
2022-05-19arm: Fix system register fpcxt_ns and fpcxt_s naming convention.Srinath Parvathaneni1-3/+11
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M Mainline Instructions VSTR, VLDR, VMRS and VMSR. Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s and fpcxts. This patch fixes the issue.
2022-05-19Arm64: force emission of ILP32-dependent relocsJan Beulich1-1/+1
Like the placeholder types added in 04dfe7aa5217 ("Arm64: follow-on to PR gas/27217 fix"), these are also placeholders which are subsequently resolved (albeit later, hence this being a separate issue). As for the resolved types 1 is returned, these pseudo-relocs should also have 1 returned to force retaining of the [eventual] relocations. This is also spelled out individually for each of them in md_apply_fix().
2022-05-18Arm64: follow-on to PR gas/27217 fixJan Beulich1-2/+7
PR gas/27217 Prior to trying to address PR gas/28888 I noticed anomalies in how certain insns would / wouldn't be affected in similar ways. Commit eac4eb8ecb26 ("Fix a problem assembling AArch64 sources when a relocation is generated against a symbol that has a defined value") had two copy-and-paste mistakes, passing the wrong type to aarch64_force_reloc(). It further failed to add placeholder relocation types to that function's block of case labels leading to a return of 1. While not of interest for aarch64_force_relocation() (these placeholders are resolved right in parse_operands()), calls to aarch64_force_reloc() happen before that resolution would take place.
2022-05-18arm: Add unwind support for mixed register listsVictor Do Nascimento1-33/+84
* config/tc-arm.c (parse_reg_list): Add handling of mixed register types. (reg_names): Enumerate pseudoregister according to mapped physical register number. (s_arm_unwind_save_pseudo): Modify function signature. (s_arm_unwind_save_core): Likewise. (s_arm_unwind_save_mixed): New function. (s_arm_unwind_save): Generate register list mask to pass to nested functions. * testsuite/gas/arm/unwind-pacbti-m.s: Expand test for mixed register type lists. * testsuite/gas/arm/unwind-pacbti-m.d: Likewise. * testsuite/gas/arm/unwind-pacbti-m-readelf.d: Likewise.
2022-05-18gas: fold do_repeat{,_with_expander}()Jan Beulich2-2/+2
do_repeat_with_expander() already deals with the "no expander" case quite fine, so there's really little point having two functions. What it lacks compared with do_repeat() is a call to sb_build(), which can simply be moved (and the then redundant sb_new() be avoided). Along with this moving also flip if the main if()'s condition such that the "no expander" case is handled first.
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu1-1/+11
bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added implicit f and zicsr for zfh. (riscv_supported_std_z_ext): Added default v1.0 version for zfh. (riscv_multi_subset_supports): Handle INSN_CLASS_ZFH, INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH. gas/ * config/tc-riscv.c (FLT_CHARS): Added "hH". (macro): Expand Pseudo M_FLH and M_FSH. (riscv_pseudo_table): Added .float16 directive. * testsuite/gas/riscv/float16-be.d: New testcase for .float16. * testsuite/gas/riscv/float16-le.d: Likewise. * testsuite/gas/riscv/float16.s: Likewise. * testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh. * testsuite/gas/riscv/fp-zfh-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh. * opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh. opcodes/ * riscv-opc.c (riscv_opcodes): Added zfh instructions.
2022-05-16IBM zSystems: Fix left-shifting negative PCRel32 values (PR gas/29152)Ilya Leoshkevich1-3/+3
s390_insert_operand ()'s val, min and max are encoded PCRel32 values and need to be left-shifted by 1 before being shown to the user. Left-shifting negative values is undefined behavior in C, but the current code does not try to prevent it, causing UBSan to complain. Fix by casting the values to their unsigned equivalents before shifting.
2022-05-12Re: IBM zSystems: Accept (. - 0x100000000) PCRel32 operandsAlan Modra1-5/+5
The new test failed on s390-linux due to bfd_sprintf_vma trimming output to 32 bits for 32-bit targets. The test was faulty anyway, expecting zero as the min end of the range is plainly wrong, but that's what you get if you cast min to int. * config/tc-s390.c (s390_insert_operand): Print range error using PRId64. * testsuite/gas/s390/zarch-z900-err.l: Correct expected output.
2022-05-10gas: remove use of PTRAlan Modra1-1/+1
* config/obj-evax.c (evax_symbol_new_hook): Don't cast to PTR.
2022-05-09IBM zSystems: Accept (. - 0x100000000) PCRel32 operandsIlya Leoshkevich1-5/+9
as does not accept instructions like brasl %r0,.-0x100000000, because of two problems with the generic overflow check: 1. PCRel32 operands are signed, but are treated as unsigned. 2. The allowed range for these operands is [-(1 << 32), (1 << 32) - 1], and not [-(1 << 31), (1 << 31) - 1]. Fix both by disabling the generic overflow check - it's not needed, because s390_insert_operand () performs its own. gas/ * config/tc-s390.c (md_gather_operands): Set fx_no_overflow. * testsuite/gas/s390/s390.exp: Add zarch-z900-err. * testsuite/gas/s390/esa-z900.d: New test. * testsuite/gas/s390/esa-z900.s: New test. * testsuite/gas/s390/zarch-z900-err.l: New test. * testsuite/gas/s390/zarch-z900-err.s: New test.
2022-04-21Delete unused COFF gas macroAlan Modra1-6/+3
* config/obj-coff.h (sy_obj): Don't define. (OBJ_SYMFIELD_TYPE): Revise comments.
2022-04-20x86: reject all invalid SAE variantsJan Beulich1-1/+1
So far an SAE-only specifier was accepted for static-rounding insns, while SAE-only insns didn't accept static rounding specifiers. If anything it would make sense the other way around, allowing SAE-only insns to have the (ignored) rounding mode specified individually rather than globally via -mevexrcig=. But for now make things match the SDM.
2022-04-19x86: don't mistake ordinary immediates for SAE / rounding controlJan Beulich1-0/+5
The way SAE templates are constructed was always puzzling me (including the need for separate templates in the first place), and expressing the extzra attribute via Imm8 actually has a bad effect: Ordinary immediates would also be accepted, leading to an extra byte being added after the instruction (i.e. generating bad code). Before re-working this (in particular to accept proper Intel syntax there), fix the immediate issue by adding the so far missing check.
2022-04-14M68K: avoid quadratic slowdlow in label alignment checkSergei Trofimovich2-34/+26
Before the change tc-m68k maintained a list of seen labels. Alignment check traversed label list to resolve symbol to label. This caused quadratic slowdown as each symbol was checked against each label. Worst affected files are the ones built with debugging enabled as DWARF generates many labels. The change embeds auxiliary label information right into symbol using TC_SYMFIELD_TYPE. Before the change test from PR 29058 did not finish in 10 minutes. After the change it finishes in 2 seconds. gas/ChangeLog: PR 29058 * config/tc-m68k.h (TC_SYMFIELD_TYPE): define as m68k_tc_sy. * config/tc-m68k.c (m68k_frob_label): Use TC_SYMFIELD_TYPE to store label information.
2022-04-12gas: new_logical_line{,_flags}() can return "void"Jan Beulich1-1/+1
With the sole user of the return value gone, convert the return type to void. This in turn allows simplifying another construct, by moving it slightly later in the function.
2022-04-12gas: drop .appfile and .applineJan Beulich10-53/+38
These were used originally to represent "# <line> <file>" constructs inserted by (typically) compilers when pre-processing. Quite some time ago they were replaced by .linefile though. Since the original directives were never documented, we ought to be able to remove support for them. As a result in a number of case function parameter aren't used anymore and can hence be dropped.
2022-04-12x86: make {disp16} work similarly to {disp32}Jan Beulich1-3/+3
In a few places {disp32} was handled specially when really {disp16} wants handling just the same.
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