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| author | Nelson Chu <nelson.chu@sifive.com> | 2020-03-26 18:38:27 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2022-05-17 13:31:38 +0800 |
| commit | 035784e3456d540444aaf7d8006f8e98bca79e5a (patch) | |
| tree | 4d4945ff79977223d15bb8e7a49ede2cb20955ca /gas/config | |
| parent | 626d0e40e55c35a4f143b70def498734e8ed3c2a (diff) | |
| download | gdb-035784e3456d540444aaf7d8006f8e98bca79e5a.zip gdb-035784e3456d540444aaf7d8006f8e98bca79e5a.tar.gz gdb-035784e3456d540444aaf7d8006f8e98bca79e5a.tar.bz2 | |
RISC-V: Added half-precision floating-point v1.0 instructions.
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit f
and zicsr for zfh.
(riscv_supported_std_z_ext): Added default v1.0 version for zfh.
(riscv_multi_subset_supports): Handle INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH and INSN_CLASS_Q_AND_ZFH.
gas/
* config/tc-riscv.c (FLT_CHARS): Added "hH".
(macro): Expand Pseudo M_FLH and M_FSH.
(riscv_pseudo_table): Added .float16 directive.
* testsuite/gas/riscv/float16-be.d: New testcase for .float16.
* testsuite/gas/riscv/float16-le.d: Likewise.
* testsuite/gas/riscv/float16.s: Likewise.
* testsuite/gas/riscv/fp-zfh-insns.d: New testcase for zfh.
* testsuite/gas/riscv/fp-zfh-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Added MASK and MATCH encodings for zfh.
* opcode/riscv.h: Added INSN_CLASS and pseudo macros for zfh.
opcodes/
* riscv-opc.c (riscv_opcodes): Added zfh instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-riscv.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index fb3fc64..1b730b4 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -389,7 +389,7 @@ const char EXP_CHARS[] = "eE"; /* Chars that mean this number is a floating point constant. As in 0f12.456 or 0d1.2345e12. */ -const char FLT_CHARS[] = "rRsSfFdDxXpP"; +const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; /* Indicate we are already assemble any instructions or not. */ static bool start_assemble = false; @@ -1908,6 +1908,15 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, vector_macro (ip); break; + case M_FLH: + pcrel_load (rd, rs1, imm_expr, "flh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + break; + case M_FSH: + pcrel_store (rs2, rs1, imm_expr, "fsh", + BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); + break; + default: as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); break; @@ -4569,6 +4578,7 @@ static const pseudo_typeS riscv_pseudo_table[] = {"insn", s_riscv_insn, 0}, {"attribute", s_riscv_attribute, 0}, {"variant_cc", s_variant_cc, 0}, + {"float16", float_cons, 'h'}, { NULL, NULL, 0 }, }; |