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authorJan Beulich <jbeulich@suse.com>2022-06-03 10:17:35 +0200
committerJan Beulich <jbeulich@suse.com>2022-06-03 10:17:35 +0200
commita98600052eb680249abae0083a7c24d7e57f7379 (patch)
tree69c2b0a596fc44baf0f8e7cfb514b92ca5e82eb6 /gas/config
parentd9ad47747aacc9326f9e880cbe6077e5c4988456 (diff)
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x86: exclude certain ISA extensions from v3/v4 ISA
Like TBM and LWP, XOP and FMA4 also shouldn't be included in v3. Like AVX512-4VNNIW, AVX512-4FMAPS also shouldn't be included in v4.
Diffstat (limited to 'gas/config')
-rw-r--r--gas/config/tc-i386.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a3c6443..5d48657 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -9579,12 +9579,14 @@ output_insn (void)
x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2;
if (i.tm.cpu_flags.bitfield.cpuavx
|| i.tm.cpu_flags.bitfield.cpuavx2
- /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW,
- CpuAVX512DQ, LPW, TBM and AMX. */
+ /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
+ XOP, FMA4, LPW, TBM, and AMX. */
|| (i.tm.opcode_modifier.vex
&& !i.tm.cpu_flags.bitfield.cpuavx512f
&& !i.tm.cpu_flags.bitfield.cpuavx512bw
&& !i.tm.cpu_flags.bitfield.cpuavx512dq
+ && !i.tm.cpu_flags.bitfield.cpuxop
+ && !i.tm.cpu_flags.bitfield.cpufma4
&& !i.tm.cpu_flags.bitfield.cpulwp
&& !i.tm.cpu_flags.bitfield.cputbm
&& !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM))
@@ -9602,11 +9604,12 @@ output_insn (void)
|| i.tm.cpu_flags.bitfield.cpuavx512bw
|| i.tm.cpu_flags.bitfield.cpuavx512dq
|| i.tm.cpu_flags.bitfield.cpuavx512vl
- /* Any EVEX encoded insns except for AVX512ER, AVX512PF and
- VNNIW. */
+ /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
+ AVX512-4FMAPS, and AVX512-4VNNIW. */
|| (i.tm.opcode_modifier.evex
&& !i.tm.cpu_flags.bitfield.cpuavx512er
&& !i.tm.cpu_flags.bitfield.cpuavx512pf
+ && !i.tm.cpu_flags.bitfield.cpuavx512_4fmaps
&& !i.tm.cpu_flags.bitfield.cpuavx512_4vnniw))
x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4;
}