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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2022-05-19 16:51:10 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2022-05-19 16:51:21 +0100 |
| commit | ee3272d472e864bcbe86d6c647d7b48df715c72b (patch) | |
| tree | c30cf1f35f1b6a6f6aeefc5bb89378ceec65f1b8 /gas/config | |
| parent | ad8f56a7371620f94978efa32e1a26df88c20bb9 (diff) | |
| download | gdb-ee3272d472e864bcbe86d6c647d7b48df715c72b.zip gdb-ee3272d472e864bcbe86d6c647d7b48df715c72b.tar.gz gdb-ee3272d472e864bcbe86d6c647d7b48df715c72b.tar.bz2 | |
arm: Fix system register fpcxt_ns and fpcxt_s naming convention.
The current assembler accepts system registers FPCXTNS and FPCXTS for Armv8.1-M
Mainline Instructions VSTR, VLDR, VMRS and VMSR.
Assembler should be also allowing FPCXT_NS, fpcxt_ns, fpcxtns, FPCXT_S, fpcxt_s
and fpcxts. This patch fixes the issue.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-arm.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 8873269..538d83f 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -6565,7 +6565,13 @@ parse_sys_vldr_vstr (char **str) {"VPR", 0x4, 0x1}, {"P0", 0x5, 0x1}, {"FPCXTNS", 0x6, 0x1}, - {"FPCXTS", 0x7, 0x1} + {"FPCXT_NS", 0x6, 0x1}, + {"fpcxtns", 0x6, 0x1}, + {"fpcxt_ns", 0x6, 0x1}, + {"FPCXTS", 0x7, 0x1}, + {"FPCXT_S", 0x7, 0x1}, + {"fpcxts", 0x7, 0x1}, + {"fpcxt_s", 0x7, 0x1} }; char *op_end = strchr (*str, ','); size_t op_strlen = op_end - *str; @@ -10161,8 +10167,8 @@ do_vmrs (void) _(BAD_FPU)); break; - case 14: /* fpcxt_ns. */ - case 15: /* fpcxt_s. */ + case 14: /* fpcxt_ns, fpcxtns, FPCXT_NS, FPCXTNS. */ + case 15: /* fpcxt_s, fpcxts, FPCXT_S, FPCXTS. */ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main), _("selected processor does not support instruction")); break; @@ -23991,6 +23997,8 @@ static const struct reg_entry reg_names[] = REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC), REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC), REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC), + REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC), + REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC), /* Maverick DSP coprocessor registers. */ REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX), |