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2024-12-20RISC-V: Refine strided load/store testcase dump check to tree optimizedPan Li11-63/+63
Like the sat alu related testcase, the dump check of strided load/store takes the rtl dump for the standard name MASK_LEN_STRIDED_LOAD for times. But the rtl pass expand is somehow mutable by the middle-end change or debug information. After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-19RISC-V: Adjust the strided store testcases check times on optionsPan Li3-3/+6
The vsse* dump check times changes on options (O2, O3) after we add (mem:BLK (scratch)) to the define_insn of strided load. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Adjust the vsse check times based on optimization option. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-19RISC-V: Make vector strided store alias all other memoriesPan Li1-0/+24
Almost the same as the RVV strided load, the vector strided store doesn't involve the (mem:BLK (scratch)) to alias all other memories. It will make the alias analysis only consider the base address of strided store. PR target/118075 gcc/ChangeLog: * config/riscv/vector.md: Add the (mem:BLK (scratch)) as the lhs of strided store define insn. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr118075-run-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-17[PATCH] RISC-V: optimization on checking certain bits set ((x & mask) == val)Oliver Kozul1-0/+16
The patch optimizes code generation for comparisons of the form X & C1 == C2 by converting them to (X | ~C1) == (C2 | ~C1). C1 is a constant that requires li and addi to be loaded, while ~C1 requires a single lui instruction. As the values of C1 and C2 are not visible within the equality expression, a plus pattern is matched instead.       PR target/114087 gcc/ChangeLog: * config/riscv/riscv.md (*lui_constraint<ANYI:mode>_and_to_or): New pattern gcc/testsuite/ChangeLog: * gcc.target/riscv/pr114087-1.c: New test.
2024-12-17[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architectureAnton Blanchard1-0/+76
This adds the Tenstorrent Ascalon 8 wide architecture (tt-ascalon-d8) to the list of known cores. gcc/ChangeLog: * config/riscv/riscv-cores.def: Add tt-ascalon-d8. * config/riscv/riscv.cc (tt_ascalon_d8_tune_info): New. * doc/invoke.texi (RISC-V): Add tt-ascalon-d8 to -mcpu. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-tt-ascalon-d8.c: New test.
2024-12-17RISC-V: Add new constraint R for register even-odd pairsKito Cheng1-0/+23
Although this constraint is not currently used for any instructions, it is very useful for custom instructions. Additionally, some new standard extensions (not yet upstream), such as `Zilsd` and `Zclsd`, are potential users of this constraint. Therefore, I believe there is sufficient justification to add it now. gcc/ChangeLog: * config/riscv/constraints.md (R): New constraint. * doc/md.texi: Document new constraint `R`. gcc/testsuite/ChangeLog: * gcc.target/riscv/constraint-R.c: New.
2024-12-17RISC-V: Implment N modifier for printing the register number rather than the ↵Kito Cheng3-0/+50
register name The modifier `N`, to print the raw encoding of a register. This is used when using `.insn <length>, <encoding>`, where the user wants to pass a value to the instruction in a known register, but where the instruction doesn't follow the existing instruction formats, so the assembly parser is not expecting a register name, just a raw integer. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_print_operand): Add N. * doc/extend.texi: Document for N, gcc/testsuite/ChangeLog: * gcc.target/riscv/modifier-N-fpr.c: New. * gcc.target/riscv/modifier-N-vr.c: New. * gcc.target/riscv/modifier-N.c: New.
2024-12-17RISC-V: Add cr and cf constraintKito Cheng3-0/+41
gcc/ChangeLog: * config/riscv/constraints.md (cr): New. (cf): New. * config/riscv/riscv.h (reg_class): Add RVC_GR_REGS and RVC_FP_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. * doc/md.texi: Document cr and cf constraint. * config/riscv/riscv.cc (riscv_regno_to_class): Update FP_REGS to RVC_FP_REGS since it smaller set. (riscv_secondary_memory_needed): Handle RVC_FP_REGS. (riscv_register_move_cost): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/constraint-cf-zfinx.c: New. * gcc.target/riscv/constraint-cf.c: New. * gcc.target/riscv/constraint-cr.c: New.
2024-12-16RISC-V: Fix compress shuffle pattern [PR117383].Robin Dapp2-1/+49
This patch makes vcompress use the tail-undisturbed policy by default and also uses the proper VL. PR target/117383 gcc/ChangeLog: * config/riscv/riscv-protos.h (enum insn_type): Use TU policy. * config/riscv/riscv-v.cc (shuffle_compress_patterns): Set VL. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Expect tu. * gcc.target/riscv/rvv/autovec/pr117383.c: New test.
2024-12-16RISC-V: Increase cost for vec_construct [PR118019].Robin Dapp1-0/+52
For a generic vec_construct from scalar elements we need to load each scalar element and move it over to a vector register. Right now we only use a cost of 1 per element. This patch uses register-move cost as well as scalar_to_vec and multiplies it with the number of elements in the vector instead. PR target/118019 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Increase vec_construct cost. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr118019.c: New test.
2024-12-13RISC-V: Improve slide1up pattern.Robin Dapp1-1/+1
This patch adds a second variant to implement the extract/slide1up pattern. In order to do a permutation like <3, 4, 5, 6> from vectors <0, 1, 2, 3> and <4, 5, 6, 7> we currently extract <3> from the first vector and re-insert it into the second vector. Unless register-file crossing latency is essentially zero it should be preferable to first slide the second vector up by one, then slide down the first vector by (nunits - 1). gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_register_move_cost): Export. * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns): Rename... (shuffle_off_by_one_patterns): ... to this and add slideup/slidedown variant. (expand_vec_perm_const_1): Call renamed function. * config/riscv/riscv.cc (riscv_secondary_memory_needed): Remove static. (riscv_register_move_cost): Add VR<->GR/FR handling. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112599-2.c: Adjust test expectation.
2024-12-13RISC-V: Add even/odd vec_perm_const pattern.Robin Dapp2-0/+190
This adds handling for even/odd patterns. gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_even_odd_patterns): New function. (expand_vec_perm_const_1): Use new function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd-run.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-evenodd.c: New test.
2024-12-13RISC-V: Add interleave pattern.Robin Dapp2-0/+191
This patch adds efficient handling of interleaving patterns like [0 4 1 5] to vec_perm_const. It is implemented by a slideup and a gather. gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_interleave_patterns): New function. (expand_vec_perm_const_1): Use new function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave-run.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-interleave.c: New test.
2024-12-13RISC-V: Add slide to perm_const strategies.Robin Dapp2-0/+473
This patch adds a shuffle_slide_patterns to expand_vec_perm_const. It recognizes permutations like {0, 1, 4, 5} or {2, 3, 6, 7} which can be constructed by a slideup or slidedown of one of the vectors into the other one. gcc/ChangeLog: * config/riscv/riscv-v.cc (shuffle_slide_patterns): New. (expand_vec_perm_const_1): Call new function. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide-run.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/shuffle-slide.c: New test.
2024-12-13RISC-V: Emit vector shift pattern for const_vector [PR117353].Robin Dapp1-0/+29
In PR117353 and PR117878 we expand a const vector during reload. For this we use an unpredicated left shift. Normally an insn like this is split but as we introduce it late and cannot create pseudos anymore it remains unpredicated and is not recognized by the vsetvl pass (where we expect all insns to be in predicated RVV format). This patch directly emits a predicated shift instead. We could distinguish between !lra_in_progress and lra_in_progress and emit an unpredicated shift in the former case but we're not very likely to optimize it anyway so it doesn't seem worth it. PR target/117353 PR target/117878 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use predicated instead of simple shift. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr117353.c: New test.
2024-12-13RISC-V: Make vector strided load alias all other memoriesPan Li1-0/+24
The vector strided load doesn't include the (mem:BLK (scratch)) to alias all other memories. It will make the alias analysis only consider the base address of strided load and promopt the store before the strided load. For example as below #define STEP 10 char d[225]; int e[STEP]; int main() { // store 0, 10, 20, 30, 40, 50, 60, 70, 80, 90 for (long h = 0; h < STEP; ++h) d[h * STEP] = 9; // load 30, 40, 50, 60, 70, 80, 90 // store 3, 4, 5, 6, 7, 8, 9 for (int h = 3; h < STEP; h += 1) e[h] = d[h * STEP]; if (e[5] != 9) { __builtin_abort (); } return 0; } The asm dump will be: main: lui a5,%hi(.LANCHOR0) addi a5,a5,%lo(.LANCHOR0) li a4,9 sb a4,30(a5) addi a3,a5,30 vsetivli zero,7,e32,m1,ta,ma li a2,10 vlse8.v v2,0(a3),a2 // depends on 30(a5), 40(a5), ... 90(a5) but // only 30(a5) has been promoted before vlse. // It is store after load mistake. addi a3,a5,252 sb a4,0(a5) sb a4,10(a5) sb a4,20(a5) sb a4,40(a5) vzext.vf4 v1,v2 sb a4,50(a5) sb a4,60(a5) vse32.v v1,0(a3) li a0,0 sb a4,70(a5) sb a4,80(a5) sb a4,90(a5) lw a5,260(a5) beq a5,a4,.L4 li a0,123 After this patch: main: vsetivli zero,4,e32,m1,ta,ma vmv.v.i v1,9 lui a5,%hi(.LANCHOR0) addi a5,a5,%lo(.LANCHOR0) addi a4,a5,244 vse32.v v1,0(a4) li a4,9 sb a4,0(a5) sb a4,10(a5) sb a4,20(a5) sb a4,30(a5) sb a4,40(a5) sb a4,50(a5) sb a4,60(a5) sb a4,70(a5) sb a4,80(a5) sb a4,90(a5) vsetivli zero,3,e32,m1,ta,ma addi a4,a5,70 li a3,10 vlse8.v v2,0(a4),a3 addi a5,a5,260 li a0,0 vzext.vf4 v1,v2 vse32.v v1,0(a5) ret The below test suites are passed for this patch. * The rv64gcv fully regression test. PR target/117990 gcc/ChangeLog: * config/riscv/vector.md: Add the (mem:BLK (scratch)) to the vector strided load. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr117990-run-1.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine signed vector SAT_SUB testcase dump check to tree optimizedPan Li16-48/+48
The sat alu related testcase check the rtl dump for the standard name like .SAT_SUB exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-1-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-2-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-3-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_sub-4-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine signed vector SAT_TRUNC testcase dump check to tree optimizedPan Li48-141/+141
The sat alu related testcase check the rtl dump for the standard name like .SAT_TRUNC exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i16-to-i8.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-1-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-2-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-3-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-4-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-5-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-6-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-7-i64-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i16-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i32-to-i8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_trunc-8-i64-to-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine signed vector SAT_ADD testcase dump check to tree optimizedPan Li16-48/+48
The sat alu related testcase check the rtl dump for the standard name like .SAT_ADD exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-1-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-2-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-3-s8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add-4-s8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine unsigned vector SAT_TRUNC testcase dump check to tree optimizedPan Li24-48/+48
The sat alu related testcase check the rtl dump for the standard name like .SAT_TRUNC exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine unsigned vector SAT_SUB testcase dump check to tree optimizedPan Li48-100/+100
The sat alu related testcase check the rtl dump for the standard name like .SAT_SUB exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-10-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-9-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_zip.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-10RISC-V: Refine unsigned vector SAT_ADD testcase dump check to tree optimizedPan Li63-127/+127
The sat alu related testcase check the rtl dump for the standard name like .SAT_ADD exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-5-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-6-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-7-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-8-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm-4-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add_imm_reconcile-4-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09[committed] RISC-V testsuite changes to test clmul expansion of CRCsMariam Arutunian42-0/+419
This testsuite only patch allows us to test code generation for CRC functions using clmul instructions. Conceptually it's trivial. We already have various execution tests in gcc.dg/torture. We just define a new set of dg directives and include the testcase in gcc.dg/torture. The only gotcha in here is the need to change target-supports.exp. It was passing the default set of arguments down to the check_runtime routine, so they always failed to assemble the testcase and we never claimed the ability to execute Zbc, Zbkb or Zbkc extension code. Again, NFC, just testsuite bits. Pushing to the trunk. Only aarch64 and x86 bits left ;-) gcc/testsuite * gcc.target/riscv/crc-1-zbc.c: New test. * gcc.target/riscv/crc-1-zbkc.c: Likewise. * gcc.target/riscv/crc-10-zbc.c: Likewise. * gcc.target/riscv/crc-10-zbkc.c: Likewise. * gcc.target/riscv/crc-12-zbc.c: Likewise. * gcc.target/riscv/crc-12-zbkc.c: Likewise. * gcc.target/riscv/crc-13-zbc.c: Likewise. * gcc.target/riscv/crc-13-zbkc.c: Likewise. * gcc.target/riscv/crc-14-zbc.c: Likewise. * gcc.target/riscv/crc-14-zbkc.c: Likewise. * gcc.target/riscv/crc-17-zbc.c: Likewise. * gcc.target/riscv/crc-17-zbkc.c: Likewise. * gcc.target/riscv/crc-18-zbc.c: Likewise. * gcc.target/riscv/crc-18-zbkc.c: Likewise. * gcc.target/riscv/crc-21-rv64-zbc.c: Likewise. * gcc.target/riscv/crc-21-rv64-zbkc.c: Likewise. * gcc.target/riscv/crc-22-zbc.c: Likewise. * gcc.target/riscv/crc-22-zbkc.c: Likewise. * gcc.target/riscv/crc-23-zbc.c: Likewise. * gcc.target/riscv/crc-23-zbkc.c: Likewise. * gcc.target/riscv/crc-4-zbc.c: Likewise. * gcc.target/riscv/crc-4-zbkb.c: Likewise. * gcc.target/riscv/crc-4-zbkc.c: Likewise. * gcc.target/riscv/crc-5-zbc.c: Likewise. * gcc.target/riscv/crc-5-zbkb.c: Likewise. * gcc.target/riscv/crc-5-zbkc.c: Likewise. * gcc.target/riscv/crc-6-zbc.c: Likewise. * gcc.target/riscv/crc-6-zbkc.c: Likewise. * gcc.target/riscv/crc-7-zbc.c: Likewise. * gcc.target/riscv/crc-7-zbkc.c: Likewise. * gcc.target/riscv/crc-8-zbc.c: Likewise. * gcc.target/riscv/crc-8-zbkc.c: Likewise. * gcc.target/riscv/crc-9-zbc.c: Likewise. * gcc.target/riscv/crc-9-zbkc.c: Likewise. * gcc.target/riscv/crc-CCIT-data16-zbc.c: Likewise. * gcc.target/riscv/crc-CCIT-data16-zbkc.c: Likewise. * gcc.target/riscv/crc-CCIT-data8-zbc.c: Likewise. * gcc.target/riscv/crc-CCIT-data8-zbkc.c: Likewise. * gcc.target/riscv/crc-coremark-16bitdata-zbc.c: Likewise. * gcc.target/riscv/crc-coremark-16bitdata-zbkc.c: Likewise. * lib/target-supports.exp (check_effective_target_riscv_zbc_ok): Set gcc_march before compiling test program. (check_effective_target_riscv_zbkc_ok): Likewise. (check_effective_target_riscv_zbkb_ok): Likewise. Co-authored-by: Jeff Law <jlaw@ventanamicro.com>
2024-12-09RISC-V: Refine signed SAT_TRUNC testcase dump check to tree optimizedPan Li48-96/+96
The sat alu related testcase check the rtl dump for the standard name like .SAT_TRUNC exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refine signed SAT_SUB testcase dump check to tree optimizedPan Li16-32/+32
The sat alu related testcase check the rtl dump for the standard name like .SAT_SUB exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_s_sub-1-i16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_s_sub-1-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-1-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-1-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-2-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-3-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_sub-4-i8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refine signed SAT_ADD testcase dump check to tree optimizedPan Li23-46/+46
The sat alu related testcase check the rtl dump for the standard name like .SAT_ADD exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_s_add-1-i16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_s_add-1-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-1-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-1-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-2-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-3-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i16.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i32.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i64.c: Ditto. * gcc.target/riscv/sat/sat_s_add-4-i8.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-2.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-3.c: Ditto. * gcc.target/riscv/sat/sat_s_add_imm-4.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refine unsigned SAT_TRUNC testcase dump check to tree optimizedPan Li24-48/+48
The sat alu related testcase check the rtl dump for the standard name like .SAT_TRUNC exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_TRUNC (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_u_trunc-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_u_trunc-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-5-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-5-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-5-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-5-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-6-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-6-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-6-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_trunc-6-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refine unsigned SAT_SUB testcase dump check to tree optimizedPan Li100-200/+200
The sat alu related testcase check the rtl dump for the standard name like .SAT_SUB exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_SUB (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_u_sub-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_u_sub-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-10-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-10-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-10-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-10-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-11-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-11-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-11-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-11-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-12-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-12-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-12-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-12-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-5-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-5-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-5-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-5-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-6-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-6-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-6-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-6-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-7-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-7-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-7-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-7-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-8-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-8-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-8-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-8-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-9-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-9-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-9-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub-9-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c: Ditto. * gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refine unsigned SAT_ADD testcase dump check to tree optimizedPan Li100-200/+200
The sat alu related testcase check the rtl dump for the standard name like .SAT_ADD exist or not. But the rtl pass expand is somehow impressionable by the middle-end change or debug information. Like below new appearance recently. Replacing Expressions _5 replace with --> _5 = .SAT_ADD (x_3(D), y_4(D)); [tail call] After that we need to adjust the dump check time and again. This patch would like to switch to tree optimized pass for the standard name check, which is more stable up to a point. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_u_add-1-u16.c: Take tree-optimized pass for standard name check, and adjust the times. * gcc.target/riscv/sat/sat_u_add-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-5-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add-6-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-1.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-10.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-11.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-12.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-13.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-14.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-15.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-16.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-17.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-18.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-19.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-2.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-20.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-21.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-22.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-23.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-24.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-25.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-26.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-27.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-28.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-29.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-3.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-30.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-31.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-32.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-33.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-34.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-35.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-36.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-37.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-38.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-39.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-4.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-40.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-41.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-42.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-43.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-44.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-45.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-46.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-47.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-48.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-49.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-5.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-50.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-51.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-52.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-53.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-54.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-55.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-56.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-57.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-58.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-59.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-6.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-60.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-7.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-8.c: Ditto. * gcc.target/riscv/sat/sat_u_add_imm_type_check-9.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Fix incorrect optimization options passing to partialPan Li1-1/+1
Like the strided load/store, the testcases of vector partial are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of the gcc.log. This patch would like to make it correct almost the same as how we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Refactor the testcases for rvv binop and cmpPan Li6-6/+70
This patch would like to refactor the testcases for rvv binop and cmp after sorts of optimization option passing to testcase. To fits different optimization option asm dump checks. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c: Skip m8 as it has different body layout. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-1.c: Add build option condition when check asm dumps. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-5.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-6.c: Ditto. * gcc.target/riscv/rvv/autovec/cmp/cmp_vi-9.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-09RISC-V: Fix incorrect optimization options passing to binop and cmpPan Li1-2/+2
Like the strided load/store, the testcases of vector binop and cmp are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of the gcc.log. This patch would like to make it correct almost the same as how we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-06RISC-V: Refactor the testcases for bswap16-0Pan Li1-1/+1
This patch would like to refactor the testcases of bswap16-0 after sorts of optimization option passing to testcase. To fits the big lmul like m8 for asm dump check. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/bswap16-0.c: Update the vector register RE to cover v10 - v31. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-06RISC-V: Fix incorrect optimization options passing to convert and unopPan Li1-2/+2
Like the strided load/store, the testcases of vector convert and unop are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of the gcc.log. This patch would like to make it correct almost the same as how we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-04sched1: parameterize pressure scheduling spilling aggressiveness [PR/114729]Vineet Gupta2-0/+34
sched1 computes ECC (Excess Change Cost) for each insn, which represents the register pressure attributed to the insn. Currently the pressure sensitive scheduling algorithm deliberately ignores negative ECC values (pressure reduction), making them 0 (neutral), leading to more spills. This happens due to the assumption that the compiler has a reasonably accurate processor pipeline scheduling model and thus tries to aggresively fill pipeline bubbles with spill slots. This however might not be true, as the model might not be available for certains uarches or even applicable especially for modern out-of-order cores. The existing heuristic induces spill frenzy on RISC-V, noticably so on SPEC2017 507.Cactu. If insn scheduling is disabled completely, the total dynamic icounts for this workload are reduced in half from ~2.5 trillion insns to ~1.3 (w/ -fno-schedule-insns). This patch adds --param=cycle-accurate-model={0,1} to gate the spill behavior. - The default (1) preserves existing spill behavior. - targets/uarches sensitive to spilling can override the param to (0) to get the reverse effect. RISC-V backend does so too. The actual perf numbers are very promising. (1) On RISC-V BPI-F3 in-order CPU, -Ofast -march=rv64gcv_zba_zbb_zbs: Before: ------ Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par': 4,917,712.97 msec task-clock:u # 1.000 CPUs utilized 5,314 context-switches:u # 1.081 /sec 3 cpu-migrations:u # 0.001 /sec 204,784 page-faults:u # 41.642 /sec 7,868,291,222,513 cycles:u # 1.600 GHz 2,615,069,866,153 instructions:u # 0.33 insn per cycle 10,799,381,890 branches:u # 2.196 M/sec 15,714,572 branch-misses:u # 0.15% of all branches After: ----- Performance counter stats for './cactusBSSN_r_base.rivos spec_ref.par': 4,552,979.58 msec task-clock:u # 0.998 CPUs utilized 205,020 context-switches:u # 45.030 /sec 2 cpu-migrations:u # 0.000 /sec 204,221 page-faults:u # 44.854 /sec 7,285,176,204,764 cycles:u (7.4% faster) # 1.600 GHz 2,145,284,345,397 instructions:u (17.96% fewer) # 0.29 insn per cycle 10,799,382,011 branches:u # 2.372 M/sec 16,235,628 branch-misses:u # 0.15% of all branches (2) Wilco reported 20% perf gains on aarch64 Neoverse V2 runs. gcc/ChangeLog: PR target/11472 * params.opt (--param=cycle-accurate-model=): New opt. * doc/invoke.texi (cycle-accurate-model): Document. * haifa-sched.cc (model_excess_group_cost): Return negative delta if param_cycle_accurate_model is 0. (model_excess_cost): Ceil negative baseECC to 0 only if param_cycle_accurate_model is 1. Dump the actual ECC value. * config/riscv/riscv.cc (riscv_option_override): Set param to 0. gcc/testsuite/ChangeLog: PR target/114729 * gcc.target/riscv/riscv.exp: Enable new tests to build. * gcc.target/riscv/sched1-spills/spill1.cpp: Add new test. Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
2024-12-03RISC-V: Fix test target selectorEdwin Lu2-2/+2
The previous target selector was not properly gating the tests to rv32 and rv64 targets. This was triggering an excess failure on rv32 targets where it would try to run the zbc64 tests. Fix selector gcc/testsuite/ChangeLog: * gcc.target/riscv/crc-builtin-zbc32.c: Fix selector. * gcc.target/riscv/crc-builtin-zbc64.c: Ditto. Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
2024-12-03RISC-V: Fix incorrect optimization options passing to reduc and ternopPan Li1-2/+2
Like the strided load/store, the testcases of vector reduce and ternop are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of the gcc.log. This patch would like to make it correct almost the same as what we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-03RISC-V: Fix incorrect optimization options passing to cond and builtinPan Li1-2/+2
Like the strided load/store, the testcases of vector cond and builtin are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of gcc.log. This patch would like to make it correct almost the same as what we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-02Add trailing newlines where neededJakub Jelinek6-6/+6
Especially in the recent CRC commits, I see \ No newline at end of file in almost every second file. So, I went through the diff between r15-1 and current trunk in gcc/, looking for additions of such problems which don't intentional (e.g. Wtrailing-whitespace* tests had it there intentionally) and just added the missing newline elsewhere. 2024-12-02 Jakub Jelinek <jakub@redhat.com> gcc/ * config/mingw/mingw-stdint.h: Add newline at the end of the file. * config/mingw/winnt-dll.cc: Likewise. * sym-exec/sym-exec-expression.h: Likewise. * sym-exec/sym-exec-expression.cc: Likewise. * sym-exec/sym-exec-condition.cc: Likewise. * sym-exec/sym-exec-expr-is-a-helper.h: Likewise. * sym-exec/sym-exec-condition.h: Likewise. * hwint.cc: Likewise. * crc-verification.cc: Likewise. * sarif-spec-urls.def: Likewise. gcc/testsuite/ * g++.target/aarch64/pr94515-2.C: Add newline at the end of the file. * g++.target/aarch64/return_address_sign_ab_exception.C: Likewise. * gcc.target/arm/thumb2-switchstatement.c: Likewise. * gcc.target/riscv/rvv/base/vssubu-2.c: Likewise. * gcc.target/riscv/rvv/base/vssubu-1.c: Likewise. * gcc.target/riscv/and-shift32.c: Likewise. * gcc.target/riscv/crc-builtin-zbc32.c: Likewise. * gcc.target/riscv/and-shift64.c: Likewise. * gcc.target/riscv/xtheadbb-extu-4.c: Likewise. * gcc.target/i386/avx2-bf16-vec-absneg.c: Likewise. * gcc.target/i386/avx512f-bf16-vec-absneg.c: Likewise. * gcc.target/aarch64/cpunative/native_cpu_26.c: Likewise. * gcc.target/aarch64/cpunative/info_26: Likewise. * gcc.target/aarch64/cpunative/info_25: Likewise. * g++.dg/contracts/pr116607.C: Likewise. * gfortran.dg/pr108889.f90: Likewise. * gcc.dg/crc-not-crc-14.c: Likewise. * gcc.dg/crc-from-fedora-packages-13.c: Likewise. * gcc.dg/crc-not-crc-25.c: Likewise. * gcc.dg/crc-from-fedora-packages-29.c: Likewise. * gcc.dg/crc-from-fedora-packages-10.c: Likewise. * gcc.dg/crc-side-instr-10.c: Likewise. * gcc.dg/crc-side-instr-1.c: Likewise. * gcc.dg/crc-side-instr-3.c: Likewise. * gcc.dg/crc-side-instr-2.c: Likewise. * gcc.dg/crc-not-crc-17.c: Likewise. * gcc.dg/crc-from-fedora-packages-7.c: Likewise. * gcc.dg/crc-side-instr-12.c: Likewise. * gcc.dg/crc-side-instr-16.c: Likewise. * gcc.dg/crc-not-crc-16.c: Likewise. * gcc.dg/crc-from-fedora-packages-4.c: Likewise. * gcc.dg/crc-not-crc-20.c: Likewise. * gcc.dg/crc-linux-3.c: Likewise. * gcc.dg/crc-from-fedora-packages-27.c: Likewise. * gcc.dg/pr109393.c: Likewise. * gcc.dg/crc-side-instr-7.c: Likewise. * gcc.dg/crc-side-instr-4.c: Likewise. * gcc.dg/tree-ssa/ldexp.c: Likewise. * gcc.dg/tree-ssa/pr114760-2.c: Likewise. * gcc.dg/tree-ssa/pr114760-1.c: Likewise. * gcc.dg/crc-side-instr-15.c: Likewise. * gcc.dg/crc-side-instr-9.c: Likewise. * gcc.dg/crc-not-crc-26.c: Likewise. * gcc.dg/crc-side-instr-8.c: Likewise. * gcc.dg/crc-not-crc-23.c: Likewise. * gcc.dg/crc-not-crc-19.c: Likewise. * gcc.dg/crc-from-fedora-packages-22.c: Likewise. * gcc.dg/crc-from-fedora-packages-16.c: Likewise. * gcc.dg/crc-side-instr-11.c: Likewise. * gcc.dg/crc-from-fedora-packages-5.c: Likewise. * gcc.dg/crc-not-crc-22.c: Likewise. * gcc.dg/crc-side-instr-17.c: Likewise. * gcc.dg/crc-linux-4.c: Likewise. * gcc.dg/crc-side-instr-14.c: Likewise. * gcc.dg/crc-not-crc-18.c: Likewise. * gcc.dg/crc-from-fedora-packages-23.c: Likewise. * gcc.dg/crc-not-crc-21.c: Likewise. * gcc.dg/crc-linux-2.c: Likewise. * gcc.dg/crc-from-fedora-packages-1.c: Likewise. * gcc.dg/crc-from-fedora-packages-30.c: Likewise. * gcc.dg/torture/crc-11.c: Likewise. * gcc.dg/torture/crc-27.c: Likewise. * gcc.dg/torture/crc-2.c: Likewise. * gcc.dg/torture/crc-24.c: Likewise. * gcc.dg/torture/crc-crc8.c: Likewise. * gcc.dg/torture/crc-crc8-data8-xorOustideFor.c: Likewise. * gcc.dg/torture/crc-16.c: Likewise. * gcc.dg/torture/crc-crc64-data64.c: Likewise. * gcc.dg/crc-from-fedora-packages-32.c: Likewise. * gcc.dg/crc-side-instr-6.c: Likewise. * gcc.dg/crc-side-instr-5.c: Likewise. * gcc.dg/crc-side-instr-13.c: Likewise. * gcc.dg/crc-not-crc-15.c: Likewise. * gcc.dg/crc-not-crc-13.c: Likewise. * gcc.dg/crc-from-fedora-packages-6.c: Likewise. * gcc.dg/crc-not-crc-24.c: Likewise.
2024-12-02RISC-V: Add intrinsics testcases for SiFive Xsfvfnrclipxfqf extensions.yulong2-0/+1211
This commit adds testcases for Xsfvfnrclipxfqf. Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_x_f_qf.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vfnrclip_xu_f_qf.c: New test.
2024-12-02RISC-V: Fix incorrect optimization options passing to widdenPan Li1-1/+1
Like the strided load/store, the testcases of vector widen are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of gcc.log. This patch would like to make it correct almost the same as what we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-12-02RISC-V: Fix RVV strided load/store testcases failurePan Li11-59/+231
This patch would like to fix the testcases failures of strided load/store after sorts of optimization option passing to testcase. * Add no strict align for vector option. * Adjust dg-final by any-opts and/or no-opts if the rtl dump changes on different optimization options (like O2, O3, zvl). The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Fix the failed test by target any-opts and/or no-opts. * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto * gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto Signed-off-by: Pan Li <pan2.li@intel.com>
2024-11-30[PATCH v3] zero_extend(not) -> xor optimization [PR112398]Alexey Merzlyakov1-0/+14
This patch adds optimization of the following patterns: (zero_extend:M (subreg:N (not:O==M (X:Q==M)))) -> (xor:M (zero_extend:M (subreg:N (X:M)), mask)) ... where the mask is GET_MODE_MASK (N). For the cases when X:M doesn't have any non-zero bits outside of mode N, (zero_extend:M (subreg:N (X:M)) could be simplified to just (X:M) and whole optimization will be: (zero_extend:M (subreg:N (not:M (X:M)))) -> (xor:M (X:M, mask)) Patch targets to handle code patterns like: not a0,a0 andi a0,a0,0xff to be optimized to: xori a0,a0,255 PR rtl-optimization/112398 PR rtl-optimization/117476 gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_unary_operation_1): Simplify ZERO_EXTEND (SUBREG (NOT X)) to XOR (X, GET_MODE_MASK(SUBREG)) when X doesn't have any non-zero bits outside of SUBREG mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr112398.c: New test. * gcc.dg/torture/pr117476-1.c: New test. From Zhendong Su. * gcc.dg/torture/pr117476-2.c: New test. From Zdenek Sojka.
2024-11-29[PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC.Mariam Arutunian2-0/+87
If the target is ZBC or ZBKC, it uses clmul instruction for the CRC calculation. Otherwise, if the target is ZBKB, generates table-based CRC, but for reversing inputs and the output uses bswap and brev8 instructions. Add new tests to check CRC generation for ZBC, ZBKC and ZBKB targets. gcc/ * expr.cc (gf2n_poly_long_div_quotient): New function. * expr.h (gf2n_poly_long_div_quotient): New function declaration. * hwint.cc (reflect_hwi): New function. * hwint.h (reflect_hwi): New function declaration. * config/riscv/bitmanip.md (crc_rev<ANYI1:mode><ANYI:mode>4): New expander for reversed CRC. (crc<SUBX1:mode><SUBX:mode>4): New expander for bit-forward CRC. * config/riscv/iterators.md (SUBX1, ANYI1): New iterators. * config/riscv/riscv-protos.h (generate_reflecting_code_using_brev): New function declaration. (expand_crc_using_clmul): Likewise. (expand_reversed_crc_using_clmul): Likewise. * config/riscv/riscv.cc (generate_reflecting_code_using_brev): New function. (expand_crc_using_clmul): Likewise. (expand_reversed_crc_using_clmul): Likewise. * config/riscv/riscv.md (UNSPEC_CRC, UNSPEC_CRC_REV): New unspecs. * doc/sourcebuild.texi: Document new target selectors. gcc/testsuite * lib/target-supports.exp (check_effective_target_riscv_zbc): New target supports predicate. (check_effective_target_riscv_zbkb): Likewise. (check_effective_target_riscv_zbkc): Likewise. (check_effective_target_zbc_ok): Likewise. (check_effective_target_zbkb_ok): Likewise. (check_effective_target_zbkc_ok): Likewise. (riscv_get_arch): Add zbkb and zbkc support. * gcc.target/riscv/crc-builtin-zbc32.c: New file. * gcc.target/riscv/crc-builtin-zbc64.c: Likewise. Co-author: Jeff Law <jlaw@ventanamicro.com>
2024-11-29RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.yulong9-0/+1706
This commit adds testcases for Xsfvqmaccqoq/dod. Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c: New test.
2024-11-26[PATCH] testsuite:RISC-V:Modify the char string.yulong1-1/+1
From: yulong <shiyulong@iscas.ac.cn> This patch modifies the char string from __riscv_xsfvcp to __riscv_xsfcease. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-sf-2.c: Modify the char string.
2024-11-26RISC-V: Refactor the testcases for RVV gather/scatterPan Li5-8/+30
This patch would like to refactor the testcases of gather/scatter after sorts of optimization option passing to testcase. Includes: * Remove unnecessary optimization options. * Adjust dg-final by any-opts and/or no-opts if the rtl dump changes on different optimization options (like O2, O3). The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12-zvbb.c: Adjust the dump check times. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c: Remove unnecessary option and add target no-opts/any-tops. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-11-26RISC-V: Fix incorrect optimization options passing to gather/scatterPan Li1-1/+1
Like the strided load/store, the testcases of vector gather/scatter are designed to pick up different sorts of optimization options but actually these option are ignored according to the Execution log of gcc.log. This patch would like to make it correct almost the same as what we fixed for strided load/store. The below test suites are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options passing to testcases. Signed-off-by: Pan Li <pan2.li@intel.com>
2024-11-25RISC-V: Ensure vtype for full-register moves [PR117544].Robin Dapp2-0/+15
As discussed in PR117544 the VTYPE register is not preserved across function calls. Even though vmv1r-like instructions operate independently of the actual vtype they still require a valid vtype. As we cannot guarantee that the vtype is valid we must make sure to emit a vsetvl between a function call and a vmv1r.v. This patch makes the necessary changes by splitting the full-reg-move insns into patterns that use the vtype register and adding vmov to the types of instructions requiring a vset. PR target/117544 gcc/ChangeLog: * config/riscv/vector.md (*mov<mode>_whole): Split. (*mov<mode>_fract): Ditto. (*mov<mode>): Ditto. (*mov<mode>_vls): Ditto. (*mov<mode>_reg_whole_vtype): New pattern with vtype use. (*mov<mode>_fract_vtype): Ditto. (*mov<mode>_vtype): Ditto. (*mov<mode>_vls_vtype): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/abi-call-args-4.c: Expect vsetvl. * gcc.target/riscv/rvv/base/pr117544.c: New test.
2024-11-25RISC-V: Minimal support for svvptc extension.Dongyan Chen1-0/+5
This patch support svvptc extension[1]. To enable GCC to recognize and process svvptc extension correctly at compile time. [1] https://github.com/riscv/riscv-svvptc gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extension. * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto. * config/riscv/riscv.opt: New mask. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-44.c: New test.
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