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| author | yulong <shiyulong@iscas.ac.cn> | 2024-11-28 10:36:05 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-11-29 05:21:51 -0800 |
| commit | fe29b03825c9971ef1726bf9c7288de3389511b3 (patch) | |
| tree | f2e61e4a204a0a3e88061d1befc26315903b0a12 /gcc/testsuite/gcc.target/riscv | |
| parent | 356bfe8ca123954e524a9d09dd8bba5ae8474a2d (diff) | |
| download | gcc-fe29b03825c9971ef1726bf9c7288de3389511b3.zip gcc-fe29b03825c9971ef1726bf9c7288de3389511b3.tar.gz gcc-fe29b03825c9971ef1726bf9c7288de3389511b3.tar.bz2 | |
RISC-V: Add intrinsics testcases for SiFive Xsfvqmaccqoq/dod extensions.
This commit adds testcases for Xsfvqmaccqoq/dod.
Co-Authored by: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yixuan Chen <chenyixuan@iscas.ac.cn>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c: New test.
* gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c: New test.
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
9 files changed, 1706 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 448374d..8f5860c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -37,6 +37,8 @@ dg-init set CFLAGS "$DEFAULT_CFLAGS -O3" dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \ "" $CFLAGS +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/xsfvector/*.\[cS\]]] \ + "" $CFLAGS gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \ "" $CFLAGS dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/*.\[cS\]]] \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c new file mode 100644 index 0000000..f2058a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_2x8x2.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmacc_2x8x2_i32m1_vint32m1_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m2_vint32m2_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m4_vint32m4_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m8_vint32m8_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_vint32m1_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_2x8x2_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_vint32m2_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_2x8x2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_vint32m4_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_2x8x2_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_vint32m8_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_2x8x2_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_tu_vint32m1_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_2x8x2_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_tu_vint32m2_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_2x8x2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_tu_vint32m4_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_2x8x2_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_2x8x2_tu_vint32m8_t: +** ... +** sf\.vqmacc\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_2x8x2_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_2x8x2_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c new file mode 100644 index 0000000..3bd6f1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmacc_4x8x4.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmacc_4x8x4_i32m1_vint32m1_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m2_vint32m2_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m4_vint32m4_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m8_vint32m8_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_vint32m1_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_4x8x4_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vint8mf2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_vint32m2_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_4x8x4_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_vint32m4_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_4x8x4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_vint32m8_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_4x8x4_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_tu_vint32m1_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmacc_4x8x4_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_tu_vint32m2_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmacc_4x8x4_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_tu_vint32m4_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmacc_4x8x4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmacc_4x8x4_tu_vint32m8_t: +** ... +** sf\.vqmacc\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmacc_4x8x4_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmacc_4x8x4_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c new file mode 100644 index 0000000..663c763 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_2x8x2.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccsu_2x8x2_i32m1_vint32m1_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m2_vint32m2_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m4_vint32m4_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m8_vint32m8_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_vint32m1_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_2x8x2_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_vint32m2_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_2x8x2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_vint32m4_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_2x8x2_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_vint32m8_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_2x8x2_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_tu_vint32m1_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_2x8x2_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_tu_vint32m2_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_2x8x2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_tu_vint32m4_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_2x8x2_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_2x8x2_tu_vint32m8_t: +** ... +** sf\.vqmaccsu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_2x8x2_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_2x8x2_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c new file mode 100644 index 0000000..0554e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccsu_4x8x4.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccsu_4x8x4_i32m1_vint32m1_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m2_vint32m2_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m4_vint32m4_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m8_vint32m8_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_vint32m1_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_4x8x4_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_vint32m2_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_4x8x4_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, vuint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_vint32m4_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_4x8x4_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, vuint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_vint32m8_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_4x8x4_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, vuint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_tu_vint32m1_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccsu_4x8x4_tu_vint32m1_t (vint32m1_t vd, vint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_tu_vint32m2_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccsu_4x8x4_tu_vint32m2_t (vint32m2_t vd, vint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_tu_vint32m4_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccsu_4x8x4_tu_vint32m4_t (vint32m4_t vd, vint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccsu_4x8x4_tu_vint32m8_t: +** ... +** sf\.vqmaccsu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccsu_4x8x4_tu_vint32m8_t (vint32m8_t vd, vint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccsu_4x8x4_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c new file mode 100644 index 0000000..dd15cc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_2x8x2.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccu_2x8x2_i32m1_vint32m1_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m2_vint32m2_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m4_vint32m4_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m8_vint32m8_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_vint32m1_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_2x8x2_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_vint32m2_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_2x8x2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_vint32m4_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_2x8x2_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_vint32m8_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_2x8x2_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_tu_vint32m1_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_2x8x2_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_tu_vint32m2_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_2x8x2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_tu_vint32m4_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_2x8x2_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_2x8x2_tu_vint32m8_t: +** ... +** sf\.vqmaccu\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_2x8x2_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_2x8x2_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c new file mode 100644 index 0000000..c386b4e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccu_4x8x4.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccu_4x8x4_i32m1_vint32m1_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m2_vint32m2_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m4_vint32m4_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m8_vint32m8_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_vint32m1_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_4x8x4_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_vint32m2_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_4x8x4_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vuint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_vint32m4_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_4x8x4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vuint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_vint32m8_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_4x8x4_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vuint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_tu_vint32m1_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccu_4x8x4_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vuint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_tu_vint32m2_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccu_4x8x4_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vuint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_tu_vint32m4_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccu_4x8x4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vuint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccu_4x8x4_tu_vint32m8_t: +** ... +** sf\.vqmaccu\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccu_4x8x4_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vuint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccu_4x8x4_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c new file mode 100644 index 0000000..db1650e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_2x8x2.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccdod -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccus_2x8x2_i32m1_vint32m1_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_2x8x2_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m2_vint32m2_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_2x8x2_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m4_vint32m4_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_2x8x2_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m8_vint32m8_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_2x8x2_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_vint32m1_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_2x8x2_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_vint32m2_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_2x8x2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_vint32m4_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_2x8x2_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_vint32m8_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_2x8x2_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vint8m8_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_2x8x2_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_2x8x2_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_2x8x2_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_2x8x2_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_tu_vint32m1_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_2x8x2_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_tu_vint32m2_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_2x8x2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_tu_vint32m4_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_2x8x2_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_2x8x2_tu_vint32m8_t: +** ... +** sf\.vqmaccus\.2x8x2\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_2x8x2_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m8_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_2x8x2_tu (vd, vs1, vs2, vl); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c new file mode 100644 index 0000000..5c5e1a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vqmaccus_4x8x4.c @@ -0,0 +1,213 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvqmaccqoq -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "riscv_vector.h" + +/* +** test_sf_vqmaccus_4x8x4_i32m1_vint32m1_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_4x8x4_i32m1_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m1 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m2_vint32m2_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_4x8x4_i32m2_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m2 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m4_vint32m4_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_4x8x4_i32m4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m8_vint32m8_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_4x8x4_i32m8_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m8 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_vint32m1_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_4x8x4_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_vint32m2_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_4x8x4_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, vint8m1_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_vint32m4_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_4x8x4_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, vint8m2_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_vint32m8_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_4x8x4_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, vint8m4_t vs2, + size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4 (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m1_tu_vint32m1_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_4x8x4_i32m1_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m1_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m2_tu_vint32m2_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_4x8x4_i32m2_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m2_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m4_tu_vint32m4_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_4x8x4_i32m4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_i32m8_tu_vint32m8_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_4x8x4_i32m8_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_i32m8_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_tu_vint32m1_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m1_t +test_sf_vqmaccus_4x8x4_tu_vint32m1_t (vint32m1_t vd, vuint8m1_t vs1, + vint8mf2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_tu_vint32m2_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m2_t +test_sf_vqmaccus_4x8x4_tu_vint32m2_t (vint32m2_t vd, vuint8m1_t vs1, + vint8m1_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_tu_vint32m4_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m4_t +test_sf_vqmaccus_4x8x4_tu_vint32m4_t (vint32m4_t vd, vuint8m1_t vs1, + vint8m2_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl); +} + +/* +** test_sf_vqmaccus_4x8x4_tu_vint32m8_t: +** ... +** sf\.vqmaccus\.4x8x4\tv[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vint32m8_t +test_sf_vqmaccus_4x8x4_tu_vint32m8_t (vint32m8_t vd, vuint8m1_t vs1, + vint8m4_t vs2, size_t vl) +{ + return __riscv_sf_vqmaccus_4x8x4_tu (vd, vs1, vs2, vl); +} |