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AgeCommit message (Expand)AuthorFilesLines
2024-04-18[testsuite] [arm] accept empty init for bfloat16Alexandre Oliva1-2/+2
2024-03-19arm: [MVE intrinsics] Fix support for loads [PR target/114323]Christophe Lyon1-0/+22
2024-03-18testsuite: Turn errors back into warnings in arm/acle/cde-mve-error-2.cThiago Jung Bauermann1-31/+32
2024-03-08arm: testsuite: tweak bics_3.c [PR113542]Richard Earnshaw1-11/+8
2024-03-08ARM: Fix builtin-bswap-1.c test [PR113915]Wilco Dijkstra1-4/+4
2024-03-06ARM: Fix conditional execution [PR113915]Wilco Dijkstra1-9/+6
2024-03-05Fix testcase pr112337.c to check the options [PR112337]Saurabh Jha1-1/+3
2024-02-23arm: fix ICE with vectorized reciprocal division [PR108120]Richard Earnshaw1-0/+16
2024-02-16Arm: Fix incorrect tailcall-generation for indirect calls [PR113780]Tejas Belagod1-0/+14
2024-02-15arm: testuite: Missing optimization pattern for rev16 with thumb1Matthieu Longo1-1/+1
2024-02-11testsuite: Update test case to comply with GCC14 changesTorbjörn SVENSSON1-7/+16
2024-02-08arm: testsuite: fix issues relating to fp16 alternative testingRichard Earnshaw15-15/+22
2024-01-29arm: Add pattern for bswap + rotate -> rev16 [Bug 108933]Matthieu Longo2-0/+20
2024-01-12arm: vld1_types_x4 ACLE intrinsicsEzra Sitorus4-7/+77
2024-01-12arm: vld1_types_x3 ACLE intrinsicsEzra Sitorus4-7/+77
2024-01-12arm: vld1_types_x2 ACLE intrinsicsEzra Sitorus4-0/+105
2024-01-12arm: vst1q_types_x4 ACLE intrinsicsEzra Sitorus4-18/+88
2024-01-12arm: vst1q_types_x3 ACLE intrinsicsEzra Sitorus4-7/+85
2024-01-12arm: vst1q_types_x2 ACLE intrinsicsEzra Sitorus4-0/+109
2024-01-12arm: vst1_types_x4 ACLE intrinsicsEzra Sitorus4-7/+75
2024-01-12arm: vst1_types_x3 ACLE intrinsicsEzra Sitorus4-7/+77
2024-01-12arm: vst1_types_x2 ACLE intrinsicsEzra Sitorus4-0/+106
2024-01-12arm: vld1q_types_x4 ACLE intrinsicsEzra Sitorus4-14/+84
2024-01-12arm: vld1q_types_x3 ACLE intrinsicsEzra Sitorus4-7/+84
2024-01-12arm: vld1q_types_x2 ACLE intrinsicsEzra Sitorus4-0/+108
2024-01-09arm: Update early-break tests to accept thumb output too.Tamar Christina1-0/+24
2024-01-07arm: Add Advanced SIMD cbranch implementationTamar Christina1-0/+138
2024-01-03Update copyright years.Jakub Jelinek9-9/+9
2023-12-08Revert "arm: vld1q_types_x2 ACLE intrinsics"Richard Earnshaw4-108/+0
2023-12-08Revert "arm: vld1q_types_x3 ACLE intrinsics"Richard Earnshaw4-80/+3
2023-12-08Revert "arm: vld1q_types_x4 ACLE intrinsics"Richard Earnshaw4-77/+0
2023-12-08Revert "arm: vst1_types_x2 ACLE intrinsics"Richard Earnshaw4-106/+0
2023-12-08Revert "arm: vst1_types_x3 ACLE intrinsics"Richard Earnshaw4-77/+7
2023-12-08Revert "arm: vst1_types_x4 ACLE intrinsics"Richard Earnshaw4-75/+7
2023-12-08Revert "arm: vst1q_types_x2 ACLE intrinsics"Richard Earnshaw4-108/+0
2023-12-08Revert "arm: vst1q_types_x3 ACLE intrinsics"Richard Earnshaw4-78/+0
2023-12-08Revert "arm: vst1q_types_x4 ACLE intrinsics"Richard Earnshaw4-78/+1
2023-12-08Revert "arm: vld1_types_x2 ACLE intrinsics"Richard Earnshaw4-105/+0
2023-12-08Revert "arm: vld1_types_x3 ACLE intrinsics"Richard Earnshaw4-77/+7
2023-12-08Revert "arm: vld1_types_x4 ACLE intrinsics"Richard Earnshaw4-77/+7
2023-12-07arm: vld1_types_x4 ACLE intrinsicsEzra Sitorus4-7/+77
2023-12-07arm: vld1_types_x3 ACLE intrinsicsEzra Sitorus4-7/+77
2023-12-07arm: vld1_types_x2 ACLE intrinsicsEzra Sitorus4-0/+105
2023-12-07arm: vst1q_types_x4 ACLE intrinsicsEzra Sitorus4-1/+78
2023-12-07arm: vst1q_types_x3 ACLE intrinsicsEzra Sitorus4-0/+78
2023-12-07arm: vst1q_types_x2 ACLE intrinsicsEzra Sitorus4-0/+108
2023-12-07arm: vst1_types_x4 ACLE intrinsicsEzra Sitorus4-7/+75
2023-12-07arm: vst1_types_x3 ACLE intrinsicsEzra Sitorus4-7/+77
2023-12-07arm: vst1_types_x2 ACLE intrinsicsEzra Sitorus4-0/+106
2023-12-07arm: vld1q_types_x4 ACLE intrinsicsEzra Sitorus4-0/+77
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