arm: vld1_types_x2 ACLE intrinsics

This patch is part of a series of patches implementing the _xN
variants of the vld1 intrinsic for the arm port. This patch adds the
_x2 variants of the vld1 intrinsic.

The previous vld1_x2 has been updated to vld1q_x2 to take into
account that it works with 4-word-length types. vld1_x2 is now
only for 2-word-length types.

ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/

ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/

gcc/ChangeLog:
	* config/arm/arm_neon.h
	(vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New
	(vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
	(vld1_f16_x2, vld1_f32_x2): New.
	(vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
	(vld1_bf16_x2): New.
	(vld1q_types_x2): Updated to use vld1q_x2 from
	arm_neon_builtins.def
	* config/arm/arm_neon_builtins.def
	(vld1_x2): Updated entries.
	(vld1q_x2): New entries, but comes from the old vld1_x2
	* config/arm/neon.md
	(neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated
	from neon_vld1_x2<mode>.

gcc/testsuite/ChangeLog:
	* gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests.

4 files changed, 105 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
new file mode 100644
index 0000000..6b0e78d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c
@@ -0,0 +1,66 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+
+uint8x8x2_t test_vld1_u8_x2 (uint8_t * a)
+{
+    return vld1_u8_x2 (a);
+}
+
+uint16x4x2_t test_vld1_u16_x2 (uint16_t * a)
+{
+    return vld1_u16_x2 (a);
+}
+
+uint32x2x2_t test_vld1_u32_x2 (uint32_t * a)
+{
+    return vld1_u32_x2 (a);
+}
+
+uint64x1x2_t test_vld1_u64_x2 (uint64_t * a)
+{
+    return vld1_u64_x2 (a);
+}
+
+int8x8x2_t test_vld1_s8_x2 (int8_t * a)
+{
+    return vld1_s8_x2 (a);
+}
+
+int16x4x2_t test_vld1_s16_x2 (int16_t * a)
+{
+    return vld1_s16_x2 (a);
+}
+
+int32x2x2_t test_vld1_s32_x2 (int32_t * a)
+{
+    return vld1_s32_x2 (a);
+}
+
+int64x1x2_t test_vld1_s64_x2 (int64_t * a)
+{
+    return vld1_s64_x2 (a);
+}
+
+float32x2x2_t test_vld1_f32_x2 (float32_t * a)
+{
+    return vld1_f32_x2 (a);
+}
+
+poly8x8x2_t test_vld1_p8_x2 (poly8_t * a)
+{
+    return vld1_p8_x2 (a);
+}
+
+poly16x4x2_t test_vld1_p16_x2 (poly16_t * a)
+{
+    return vld1_p16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
new file mode 100644
index 0000000..3ec7a5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_v8_2a_bf16_neon } */
+
+#include "arm_neon.h"
+
+bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a)
+{
+    return vld1_bf16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
new file mode 100644
index 0000000..c0e5ea4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_neon_fp16 } */
+
+#include "arm_neon.h"
+
+float16x4x2_t test_vld1_f16_x2 (float16_t * a)
+{
+    return vld1_f16_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
new file mode 100644
index 0000000..3ccea52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c
@@ -0,0 +1,13 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_crypto_ok } */
+/* { dg-options "-save-temps -O2" } */
+/* { dg-add-options arm_crypto } */
+
+#include "arm_neon.h"
+
+poly64x1x2_t test_vld1_p64_x2 (poly64_t * a)
+{
+    return vld1_p64_x2 (a);
+}
+
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */