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2018-11-04Enable support for next generation AMD Zen CPU, via -march=znver2.Venkataramanan Kumar8-16/+170
gcc/ChangeLog: * common/config/i386/i386-common.c (processor_alias_table): Add znver2 entry. * config.gcc (i[34567]86-*-linux* | ...): Add znver2. (case ${target}): Add znver2. * config/i386/driver-i386.c: (host_detect_local_cpu): Let -march=native recognize znver2 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add znver2. * config/i386/i386.c (m_znver2): New definition. (m_ZNVER): New definition. (m_AMD_MULTIPLE): Includes m_znver2. (processor_cost_table): Add znver2 entry. (processor_target_table): Add znver2 entry. (get_builtin_code_for_version): Set priority for PROCESSOR_ZNVER2. (processor_model): Add M_AMDFAM17H_ZNVER2. (arch_names_table): Ditto. (ix86_reassociation_width): Include znver2. * config/i386/i386.h (TARGET_znver2): New definition. (struct ix86_size_cost): Add TARGET_ZNVER2. (enum processor_type): Add PROCESSOR_ZNVER2. * config/i386/i386.md (define_attr "cpu"): Add znver2. * config/i386/x86-tune-costs.h: (processor_costs) Add znver2 costs. * config/i386/x86-tune-sched.c: (ix86_issue_rate): Add znver2. (ix86_adjust_cost): Add znver2. * config/i386/x86-tune.def: Replace m_ZNVER1 by m_ZNVER * gcc/doc/extend.texi: Add details about znver2. * gcc/doc/invoke.texi: Add details about znver2. libgcc/ChangeLog * config/i386/cpuinfo.c: (get_amd_cpu): Add znver2. * config/i386/cpuinfo.h(processor_subtypes): Ditto. From-SVN: r265775
2018-11-03re PR target/87079 (nios2 optimization for size - case of regression ↵Sandra Loosemore1-0/+13
relatively to 5.3.0) 2018-11-03 Sandra Loosemore <sandra@codesourcery.com> PR target/87079 gcc/ * config/nios2/nios2.c (nios2_rtx_costs): Recognize <mul>sidi3 pattern. gcc/testsuite/ * gcc.target/nios2/pr87079-1.c: New. * gcc.target/nios2/pr87079-2.c: New. From-SVN: r265770
2018-11-02rs6000-string.c (expand_strncmp_gpr_sequence): Pay attention to ↵Aaron Sawdey1-5/+11
TARGET_AVOID_XFORM and BYTES_BIG_ENDIAN. 2018-11-02 Aaron Sawdey <acsawdey@linux.ibm.com> * config/rs6000/rs6000-string.c (expand_strncmp_gpr_sequence): Pay attention to TARGET_AVOID_XFORM and BYTES_BIG_ENDIAN. From-SVN: r265751
2018-11-02Although there's no fundamental reason why shrink wrapping and speculation ↵Richard Earnshaw1-0/+6
tracking are incompatible... Although there's no fundamental reason why shrink wrapping and speculation tracking are incompatible, a phase-ordering requirement (we need to do speculation tracking before the final basic block clean-up) means that the shrink wrapping pass can undo some of the changes the speculation tracking pass makes. The result is that the tracking, while still safe is less comprehensive than we really want. So to keep things simple, and because the tracking code is quite expensive anyway, it seems best to just disable that pass when we are tracking speculative execution. * config/aarch64/aarch64.c (aarch64_override_options): Disable shrink-wrapping when -mtrack-speculation. From-SVN: r265747
2018-11-02Remove SPARC HAVE_AS_REGISTER_PSEUDO_OPRainer Orth2-9/+0
* configure.ac (gcc_cv_as_sparc_register_op): Remove. * configure: Regenerate. * config.in: Regenerate. * config/sparc/sparc.c (sparc_output_scratch_registers): Remove HAVE_AS_REGISTER_PSEUDO_OP guard. * config/sparc/sparc.h (ASM_ARCH64_SPEC): Remove !HAVE_AS_REGISTER_PSEUDO_OP support. (ASM_DECLARE_REGISTER_GLOBAL): Remove HAVE_AS_REGISTER_PSEUDO_OP guard. From-SVN: r265743
2018-11-01rs6000-protos.h (rs6000_address_for_fpconvert): Remove prototype.Aaron Sawdey4-42/+22
2018-11-01 Aaron Sawdey <acsawdey@linux.ibm.com> * config/rs6000/rs6000-protos.h (rs6000_address_for_fpconvert): Remove prototype. * config/rs6000/rs6000.c (rs6000_force_indexed_or_indirect_mem): Combine with rs6000_address_for_fpconvert. (rs6000_address_for_fpconvert): Combine with rs6000_force_indexed_or_indirect_mem. (rs6000_expand_vector_init): Change function call from rs6000_address_for_fpconvert to rs6000_force_indexed_or_indirect_mem. * config/rs6000/rs6000.md (floatsi<mode>2_lfiwax): Change call from rs6000_address_for_fpconvert to rs6000_force_indexed_or_indirect_mem. (floatsi<mode>2_lfiwax_mem): Ditto. (floatunssi<mode>2_lfiwzx): Ditto. (floatunssi<mode>2_lfiwzx_mem): Ditto. (float<QHI:mode><FP_ISA3:mode>2): Ditto. (floatuns<QHI:mode><FP_ISA3:mode>2): Ditto. (fix_trunc<mode>si2_stfiwx): Ditto. (fixuns_trunc<mode>si2_stfiwx): Ditto. (float_<mode>si2_hw): Ditto. (floatuns_<mode>si2_hw): Ditto. * config/rs6000/vsx.md (*vsx_extract_si): Ditto. (vsx_splat_<mode>): Ditto. From-SVN: r265733
2018-10-31aarch64: Remove early clobber from ATOMIC_LDOP scratchRichard Henderson1-1/+13
* config/aarch64/atomics.md (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse): The scratch register need not be early-clobber. Document the reason why we cannot use ST<OP>. From-SVN: r265703
2018-10-31Provide extension hint for aarch64 target (PR driver/83193).Martin Liska2-17/+57
2018-10-31 Martin Liska <mliska@suse.cz> PR driver/83193 * common/config/aarch64/aarch64-common.c (aarch64_parse_extension): Add new argument invalid_extension. (aarch64_get_all_extension_candidates): New function. (aarch64_rewrite_selected_cpu): Add NULL to function call. * config/aarch64/aarch64-protos.h (aarch64_parse_extension): Add new argument. (aarch64_get_all_extension_candidates): New function. * config/aarch64/aarch64.c (aarch64_parse_arch): Add new argument invalid_extension. (aarch64_parse_cpu): Likewise. (aarch64_print_hint_for_extensions): New function. (aarch64_validate_mcpu): Provide hint about invalid extension. (aarch64_validate_march): Likewise. (aarch64_handle_attr_arch): Pass new argument. (aarch64_handle_attr_cpu): Provide hint about invalid extension. (aarch64_handle_attr_isa_flags): Likewise. 2018-10-31 Martin Liska <mliska@suse.cz> PR driver/83193 * gcc.target/aarch64/spellcheck_7.c: New test. * gcc.target/aarch64/spellcheck_8.c: New test. * gcc.target/aarch64/spellcheck_9.c: New test. From-SVN: r265686
2018-10-31[ARC] Handle store cacheline hazard.Claudiu Zissulescu5-40/+133
Handle store cacheline hazard for A700 cpus by inserting two NOP_S between ST ST LD or their logical equivalent (like ST ST NOP_S NOP_S J_L.D LD) gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-arch.h (ARC_TUNE_ARC7XX): New tune value. * config/arc/arc.c (arc_active_insn): New function. (check_store_cacheline_hazard): Likewise. (workaround_arc_anomaly): Use check_store_cacheline_hazard. (arc_override_options): Disable delay slot scheduler for older A7. (arc_store_addr_hazard_p): New implementation, old one renamed to ... (arc_store_addr_hazard_internal_p): Renamed. (arc_reorg): Don't combine into brcc instructions which are part of hardware hazard solution. * config/arc/arc.md (attr tune): Consider new arc7xx tune value. (tune_arc700): Likewise. * config/arc/arc.opt (arc7xx): New tune value. * config/arc/arc700.md: Improve A7 scheduler. From-SVN: r265676
2018-10-31[ARC] Add BI/BIH instruction support.Claudiu Zissulescu4-214/+125
Use BI/BIH instruction to implement casesi pattern. Only ARC V2. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_override_options): Remove TARGET_COMPACT_CASESI. * config/arc/arc.h (ASM_OUTPUT_ADDR_DIFF_ELT): Update. (CASE_VECTOR_MODE): Likewise. (CASE_VECTOR_PC_RELATIVE): Likewise. (CASE_VECTOR_SHORTEN_MODE): Likewise. (CASE_VECTOR_SHORTEN_MODE1): Delete. (ADDR_VEC_ALIGN): Update. (ASM_OUTPUT_CASE_LABEL): Undefine. (ASM_OUTPUT_BEFORE_CASE_LABEL): Undefine. (TARGET_BI_BIH): Define. (DEFAULT_BRANCH_INDEX): Likewise. * config/arc/arc.md (casesi): Rework to accept BI/BIH instructions, remove compact_casesi use case. (casesi_compact_jump): Remove. (casesi_dispatch): New pattern. * config/arc/arc.opt: Add mbranch-index option. Deprecate compact_casesi option. * doc/invoke.texi: Document mbranch-index option. gcc/testsuite xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/jumptable.c: New test. From-SVN: r265675
2018-10-31[ARC] Cleanup TLS implementation and add a number of tests.Claudiu Zissulescu2-78/+38
gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_get_tp): Remove function. (arc_emit_call_tls_get_addr): Likewise. (arc_call_tls_get_addr): New function. (arc_legitimize_tls_address): Make use of arc_call_tls_get_addr. * config/arc/arc.md (tls_load_tp_soft): Remove. (tls_gd_get_addr): Likewise. testsuite/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/tls-gd.c: New file. * gcc.target/arc/tls-ie.c: Likewise. * gcc.target/arc/tls-ld.c: Likewise. * gcc.target/arc/tls-le.c: Likewise. * gcc.target/arc/tls-1.c: Update test. From-SVN: r265674
2018-10-31[ARC] Remove non standard funcions calls.Claudiu Zissulescu1-148/+10
Replace all custom "library" calls with compiler known patterns. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (mulsi3): Remove call to mulsi_600_lib. (mulsi3_600_lib): Remove pattern. (umulsi3_highpart_600_lib_le): Likewise. (umulsi3_highpart): Remove call to umulsi3_highpart_600_lib_le. (umulsidi3): Remove call to umulsidi3_600_lib. (umulsidi3_600_lib): Remove pattern. (peephole2): Remove peephole using the above deprecated patterns. testsuite/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/mulsi3_highpart-2.c: Update test. libgcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/lib1funcs.S (_muldi3): New function. * config/arc/t-arc (LIB1ASMFUNCS): Add _muldi3. From-SVN: r265672
2018-10-31Fix PR87374: ICE with -mslow-flash-data and -mword-relocationsThomas Preud'homme2-8/+16
GCC ICEs under -mslow-flash-data and -mword-relocations because there is no way to load an address, both literal pools and MOVW/MOVT being forbidden. This patch gives an error message when both options are specified by the user and adds the according dg-skip-if directives for tests that use either of these options. It also explicitely set the option when in PIC mode as per documentation rather than always check for target_word_relocation together with flag_pic. 2018-10-31 Thomas Preud'homme <thomas.preudhomme@linaro.org> gcc/ PR target/87374 * config/arm/arm.c (arm_option_check_internal): Disable the combined use of -mslow-flash-data and -mword-relocations. (arm_option_override): Enable -mword-relocations if -fpic or -fPIC. * config/arm/arm.md (SYMBOL_REF MOVT splitter): Stop checking for flag_pic. * doc/invoke.texi (-mword-relocations): Mention conflict with -mslow-flash-data. (-mslow-flash-data): Reciprocally. gcc/testsuite/ PR target/87374 * gcc.target/arm/movdi_movt.c: Skip if both -mslow-flash-data and -mword-relocations would be passed when compiling the test. * gcc.target/arm/movsi_movt.c: Likewise. * gcc.target/arm/pr81863.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-1.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-2.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-3.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-4.c: Likewise. * gcc.target/arm/thumb2-slow-flash-data-5.c: Likewise. * gcc.target/arm/tls-disable-literal-pool.c: Likewise. From-SVN: r265662
2018-10-31aarch64: Force TImode values into even registersRichard Henderson1-4/+8
The LSE CASP instruction requires values to be placed in even register pairs. A solution involving two additional register classes was rejected in favor of the much simpler solution of simply requiring all TImode values to be aligned. * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force 16-byte modes held in GP registers to use an even regno. From-SVN: r265661
2018-10-31aarch64: Improve atomic-op lse generationRichard Henderson4-272/+108
Fix constraints; avoid unnecessary split. Drop the use of the atomic_op iterator in favor of the ATOMIC_LDOP iterator; this is simplier and more logical for ldclr aka bic. * config/aarch64/aarch64.c (aarch64_emit_bic): Remove. (aarch64_atomic_ldop_supported_p): Remove. (aarch64_gen_atomic_ldop): Remove. * config/aarch64/atomic.md (atomic_<atomic_optab><ALLI>): Fully expand LSE operations here. (atomic_fetch_<atomic_optab><ALLI>): Likewise. (atomic_<atomic_optab>_fetch<ALLI>): Likewise. (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse): Drop atomic_op iterator and use ATOMIC_LDOP instead; use register_operand for the input; drop the split and emit insns directly. (aarch64_atomic_fetch_<ATOMIC_LDOP><ALLI>_lse): Likewise. (aarch64_atomic_<atomic_op>_fetch<ALLI>_lse): Remove. (@aarch64_atomic_load<ATOMIC_LDOP><ALLI>): Remove. From-SVN: r265660
2018-10-31aarch64: Improve swp generationRichard Henderson2-47/+15
Allow zero as an input; fix constraints; avoid unnecessary split. * config/aarch64/aarch64.c (aarch64_emit_atomic_swap): Remove. (aarch64_gen_atomic_ldop): Don't call it. * config/aarch64/atomics.md (atomic_exchange<ALLI>): Use aarch64_reg_or_zero. (aarch64_atomic_exchange<ALLI>): Likewise. (aarch64_atomic_exchange<ALLI>_lse): Remove split; remove & from operand 0; use aarch64_reg_or_zero for input; merge ... (@aarch64_atomic_swp<ALLI>): ... this and remove. From-SVN: r265659
2018-10-31aarch64: Improve cas generationRichard Henderson3-44/+75
Do not zero-extend the input to the cas for subword operations; instead, use the appropriate zero-extending compare insns. Correct the predicates and constraints for immediate expected operand. * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New. (aarch64_split_compare_and_swap): Use it. (aarch64_expand_compare_and_swap): Likewise. Remove convert_modes; test oldval against the proper predicate. * config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI>): Use nonmemory_operand for expected. (cas_short_expected_pred): New. (@aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match. (@aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected. * config/aarch64/predicates.md (aarch64_plushi_immediate): New. (aarch64_plushi_operand): New. From-SVN: r265657
2018-10-31aarch64: Simplify LSE cas generationRichard Henderson3-119/+49
The cas insn is a single insn, and if expanded properly need not be split after reload. Use the proper inputs for the insn. * config/aarch64/aarch64.c (aarch64_expand_compare_and_swap): Force oldval into the rval register for TARGET_LSE; emit the compare during initial expansion so that it may be deleted if unused. (aarch64_gen_atomic_cas): Remove. * config/aarch64/atomics.md (@aarch64_compare_and_swap<SHORT>_lse): Change =&r to +r for operand 0; use match_dup for operand 2; remove is_weak and mod_f operands as unused. Drop the split and merge with... (@aarch64_atomic_cas<SHORT>): ... this pattern's output; remove. (@aarch64_compare_and_swap<GPI>_lse): Similarly. (@aarch64_atomic_cas<GPI>): Similarly. From-SVN: r265656
2018-10-31Add pipeline description for Qualcomm Saphira core.Sameera Deshpande3-1/+562
From-SVN: r265653
2018-10-30rs6000.md (bswapdi2): Force address into register if not in indexed or ↵Aaron Sawdey3-4/+27
indirect form. 2018-10-30 Aaron Sawdey <acsawdey@linux.ibm.com> * config/rs6000/rs6000.md (bswapdi2): Force address into register if not in indexed or indirect form. (bswapdi2_load): Change predicate to indexed_or_indirect_operand. (bswapdi2_store): Ditto. * config/rs6000/rs6000.c (rs6000_force_indexed_or_indirect_mem): New helper function. * config/rs6000/rs6000-protos.h (rs6000_force_indexed_or_indirect_mem): Prototype for helper function. From-SVN: r265632
2018-10-30Avoid unnecessarily numbering cloned symbols.Michael Ploujnikov1-1/+1
2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com> * cgraph.h (clone_function_name_1): Replaced by new clone_function_name_numbered that takes name as string; for privatize_symbol_name_1 use only. (clone_function_name): Renamed to clone_function_name_numbered to be explicit about numbering. (clone_function_name): New two-argument function that does not number its output. (clone_function_name): New three-argument function that takes a number to append to its output. * cgraphclones.c (duplicate_thunk_for_node): (clone_function_name_1): Renamed. (clone_function_name_numbered): Two new functions. (clone_function_name): Improved documentation. (cgraph_node::create_virtual_clone): Use clone_function_name_numbered. * config/rs6000/rs6000.c (make_resolver_func): Ditto. * final.c (final_scan_insn_1): Use the new clone_function_name without numbering. * multiple_target.c (create_dispatcher_calls): Ditto. (create_target_clone): Ditto. * omp-expand.c (grid_expand_target_grid_body): Ditto. * omp-low.c (create_omp_child_function_name): Ditto. * omp-simd-clone.c (simd_clone_create): Ditto. * symtab.c (simd_symtab_node::noninterposable_alias): Use the new clone_function_name without numbering. 2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com> * lto-partition.c (privatize_symbol_name_1): Use clone_function_name_numbered. 2018-10-30 Michael Ploujnikov <michael.ploujnikov@oracle.com> * gcc.dg/tree-prof/cold_partition_label.c: Update for cold section names without numbers. * gcc.dg/tree-prof/section-attr-1.c: Ditto. * gcc.dg/tree-prof/section-attr-2.c: Ditto. * gcc.dg/tree-prof/section-attr-3.c: Ditto. From-SVN: r265621
2018-10-30Fixes bug 87330 by invoking df_note_add_problem to recompute REG_DEAD and ↵Sameera Deshpande1-0/+1
REG_UNUSED notes before analysis. From-SVN: r265618
2018-10-29[rs6000] Consistently use '__vector' instead of 'vector'Paul A. Clarke2-47/+47
Revision r265535 committed changes that used 'vector' instead of the preferred '__vector'. There is a reason that '__vector' is preferred, because it ensures no conflicts with C++ namespace. Indeed, gcc/config/rs6000/xmmintrin.h undefines it, leading to errors: gcc/include/xmmintrin.h:999:20: error: 'vector' undeclared (first use in this function); did you mean 'vec_or'? gcc/include/xmmintrin.h:999:20: note: each undeclared identifier is reported only once for each function it appears in gcc/include/xmmintrin.h:999:26: error: expected ')' before 'long' gcc/include/xmmintrin.h:999:37: error: expected ')' before 'result' Also fixed a few whitespace issues. [gcc] 2018-10-29 Paul A. Clarke <pc@us.ibm.com> * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. From-SVN: r265601
2018-10-29Extract VXWORKS_NET_LIBS_RTP from VXWORKS_LIBS_RTPOlivier Hainque1-3/+9
2018-10-29 Olivier Hainque <hainque@adacore.com> * VXWORKS_NET_LIBS_RTP: New macro, network part of VXWORKS_LIBS_RTP. From-SVN: r265595
2018-10-29Introduce notion of VXWORKS_PERSONALITYOlivier Hainque1-2/+10
2018-10-29 Olivier Hainque <hainque@adacore.com> * config/vxworks.h (VXWORKS_PERSONALITY): New VxWorks ports configuration macro, defaults to "gnu". (VXWORKS_OS_CPP_BUILTINS): Use it. Feed TOOL and TOOL_FAMILY instead of _VX_TOOL/_VXTOOL_FAMILY. From-SVN: r265594
2018-10-28Add D front-end, libphobos library, and D2 testsuite.Iain Buclaw54-4/+695
ChangeLog: * Makefile.def (target_modules): Add libphobos. (flags_to_pass): Add GDC, GDCFLAGS, GDC_FOR_TARGET and GDCFLAGS_FOR_TARGET. (dependencies): Make libphobos depend on libatomic, libbacktrace configure, and zlib configure. (language): Add language d. * Makefile.in: Rebuild. * Makefile.tpl (BUILD_EXPORTS): Add GDC and GDCFLAGS. (HOST_EXPORTS): Add GDC. (POSTSTAGE1_HOST_EXPORTS): Add GDC and GDC_FOR_BUILD. (BASE_TARGET_EXPORTS): Add GDC. (GDC_FOR_BUILD, GDC, GDCFLAGS): New variables. (GDC_FOR_TARGET, GDC_FLAGS_FOR_TARGET): New variables. (EXTRA_HOST_FLAGS): Add GDC. (STAGE1_FLAGS_TO_PASS): Add GDC. (EXTRA_TARGET_FLAGS): Add GDC and GDCFLAGS. * config-ml.in: Treat GDC and GDCFLAGS like other compiler/flag environment variables. * configure: Rebuild. * configure.ac: Add target-libphobos to target_libraries. Set and substitute GDC_FOR_BUILD and GDC_FOR_TARGET. config/ChangeLog: * multi.m4: Set GDC. gcc/ChangeLog: * Makefile.in (tm_d_file_list, tm_d_include_list): New variables. (TM_D_H, D_TARGET_DEF, D_TARGET_H, D_TARGET_OBJS): New variables. (tm_d.h, cs-tm_d.h, default-d.o): New rules. (d/d-target-hooks-def.h, s-d-target-hooks-def-h): New rules. (s-tm-texi): Also check timestamp on d-target.def. (generated_files): Add TM_D_H and d-target-hooks-def.h. (build/genhooks.o): Also depend on D_TARGET_DEF. * config.gcc (tm_d_file, d_target_objs, target_has_targetdm): New variables. * config/aarch64/aarch64-d.c: New file. * config/aarch64/aarch64-linux.h (GNU_USER_TARGET_D_CRITSEC_SIZE): Define. * config/aarch64/aarch64-protos.h (aarch64_d_target_versions): New prototype. * config/aarch64/aarch64.h (TARGET_D_CPU_VERSIONS): Define. * config/aarch64/t-aarch64 (aarch64-d.o): New rule. * config/arm/arm-d.c: New file. * config/arm/arm-protos.h (arm_d_target_versions): New prototype. * config/arm/arm.h (TARGET_D_CPU_VERSIONS): Define. * config/arm/linux-eabi.h (EXTRA_TARGET_D_OS_VERSIONS): Define. * config/arm/t-arm (arm-d.o): New rule. * config/default-d.c: New file. * config/glibc-d.c: New file. * config/gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/i386/i386-d.c: New file. * config/i386/i386-protos.h (ix86_d_target_versions): New prototype. * config/i386/i386.h (TARGET_D_CPU_VERSIONS): Define. * config/i386/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Define. (GNU_USER_TARGET_D_CRITSEC_SIZE): Define. * config/i386/t-i386 (i386-d.o): New rule. * config/kfreebsd-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/kopensolaris-gnu.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/linux-android.h (ANDROID_TARGET_D_OS_VERSIONS): Define. * config/linux.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/mips/linux-common.h (EXTRA_TARGET_D_OS_VERSIONS): Define. * config/mips/mips-d.c: New file. * config/mips/mips-protos.h (mips_d_target_versions): New prototype. * config/mips/mips.h (TARGET_D_CPU_VERSIONS): Define. * config/mips/t-mips (mips-d.o): New rule. * config/powerpcspe/linux.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/powerpcspe/linux64.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/powerpcspe/powerpcspe-d.c: New file. * config/powerpcspe/powerpcspe-protos.h (rs6000_d_target_versions): New prototype. * config/powerpcspe/powerpcspe.c (rs6000_output_function_epilogue): Support GNU D by using 0 as the language type. * config/powerpcspe/powerpcspe.h (TARGET_D_CPU_VERSIONS): Define. * config/powerpcspe/t-powerpcspe (powerpcspe-d.o): New rule. * config/riscv/riscv-d.c: New file. * config/riscv/riscv-protos.h (riscv_d_target_versions): New prototype. * config/riscv/riscv.h (TARGET_D_CPU_VERSIONS): Define. * config/riscv/t-riscv (riscv-d.o): New rule. * config/rs6000/linux.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/rs6000/linux64.h (GNU_USER_TARGET_D_OS_VERSIONS): Define. * config/rs6000/rs6000-d.c: New file. * config/rs6000/rs6000-protos.h (rs6000_d_target_versions): New prototype. * config/rs6000/rs6000.c (rs6000_output_function_epilogue): Support GNU D by using 0 as the language type. * config/rs6000/rs6000.h (TARGET_D_CPU_VERSIONS): Define. * config/rs6000/t-rs6000 (rs6000-d.o): New rule. * config/s390/s390-d.c: New file. * config/s390/s390-protos.h (s390_d_target_versions): New prototype. * config/s390/s390.h (TARGET_D_CPU_VERSIONS): Define. * config/s390/t-s390 (s390-d.o): New rule. * config/sparc/sparc-d.c: New file. * config/sparc/sparc-protos.h (sparc_d_target_versions): New prototype. * config/sparc/sparc.h (TARGET_D_CPU_VERSIONS): Define. * config/sparc/t-sparc (sparc-d.o): New rule. * config/t-glibc (glibc-d.o): New rule. * configure: Regenerated. * configure.ac (tm_d_file): New variable. (tm_d_file_list, tm_d_include_list, d_target_objs): Add substitutes. * doc/contrib.texi (Contributors): Add self for the D frontend. * doc/frontends.texi (G++ and GCC): Mention D as a supported language. * doc/install.texi (Configuration): Mention libphobos as an option for --enable-shared. Mention d as an option for --enable-languages. (Testing): Mention check-d as a target. * doc/invoke.texi (Overall Options): Mention .d, .dd, and .di as file name suffixes. Mention d as a -x option. * doc/sourcebuild.texi (Top Level): Mention libphobos. * doc/standards.texi (Standards): Add section on D language. * doc/tm.texi: Regenerated. * doc/tm.texi.in: Add @node for D language and ABI, and @hook for TARGET_CPU_VERSIONS, TARGET_D_OS_VERSIONS, and TARGET_D_CRITSEC_SIZE. * dwarf2out.c (is_dlang): New function. (gen_compile_unit_die): Use DW_LANG_D for D. (declare_in_namespace): Return module die for D, instead of adding extra declarations into the namespace. (gen_namespace_die): Generate DW_TAG_module for D. (gen_decl_die): Handle CONST_DECLSs for D. (dwarf2out_decl): Likewise. (prune_unused_types_walk_local_classes): Handle DW_tag_interface_type. (prune_unused_types_walk): Handle DW_tag_interface_type same as other kinds of aggregates. * gcc.c (default_compilers): Add entries for .d, .dd and .di. * genhooks.c: Include d/d-target.def. gcc/po/ChangeLog: * EXCLUDES: Add sources from d/dmd. gcc/testsuite/ChangeLog: * gcc.misc-tests/help.exp: Add D to option descriptions check. * gdc.dg/asan/asan.exp: New file. * gdc.dg/asan/gdc272.d: New test. * gdc.dg/compilable.d: New test. * gdc.dg/dg.exp: New file. * gdc.dg/gdc254.d: New test. * gdc.dg/gdc260.d: New test. * gdc.dg/gdc270a.d: New test. * gdc.dg/gdc270b.d: New test. * gdc.dg/gdc282.d: New test. * gdc.dg/gdc283.d: New test. * gdc.dg/imports/gdc170.d: New test. * gdc.dg/imports/gdc231.d: New test. * gdc.dg/imports/gdc239.d: New test. * gdc.dg/imports/gdc241a.d: New test. * gdc.dg/imports/gdc241b.d: New test. * gdc.dg/imports/gdc251a.d: New test. * gdc.dg/imports/gdc251b.d: New test. * gdc.dg/imports/gdc253.d: New test. * gdc.dg/imports/gdc254a.d: New test. * gdc.dg/imports/gdc256.d: New test. * gdc.dg/imports/gdc27.d: New test. * gdc.dg/imports/gdcpkg256/package.d: New test. * gdc.dg/imports/runnable.d: New test. * gdc.dg/link.d: New test. * gdc.dg/lto/lto.exp: New file. * gdc.dg/lto/ltotests_0.d: New test. * gdc.dg/lto/ltotests_1.d: New test. * gdc.dg/runnable.d: New test. * gdc.dg/simd.d: New test. * gdc.test/gdc-test.exp: New file. * lib/gdc-dg.exp: New file. * lib/gdc.exp: New file. libphobos/ChangeLog: * Makefile.am: New file. * Makefile.in: New file. * acinclude.m4: New file. * aclocal.m4: New file. * config.h.in: New file. * configure: New file. * configure.ac: New file. * d_rules.am: New file. * libdruntime/Makefile.am: New file. * libdruntime/Makefile.in: New file. * libdruntime/__entrypoint.di: New file. * libdruntime/__main.di: New file. * libdruntime/gcc/attribute.d: New file. * libdruntime/gcc/backtrace.d: New file. * libdruntime/gcc/builtins.d: New file. * libdruntime/gcc/config.d.in: New file. * libdruntime/gcc/deh.d: New file. * libdruntime/gcc/libbacktrace.d.in: New file. * libdruntime/gcc/unwind/arm.d: New file. * libdruntime/gcc/unwind/arm_common.d: New file. * libdruntime/gcc/unwind/c6x.d: New file. * libdruntime/gcc/unwind/generic.d: New file. * libdruntime/gcc/unwind/package.d: New file. * libdruntime/gcc/unwind/pe.d: New file. * m4/autoconf.m4: New file. * m4/druntime.m4: New file. * m4/druntime/cpu.m4: New file. * m4/druntime/libraries.m4: New file. * m4/druntime/os.m4: New file. * m4/gcc_support.m4: New file. * m4/gdc.m4: New file. * m4/libtool.m4: New file. * src/Makefile.am: New file. * src/Makefile.in: New file. * src/libgphobos.spec.in: New file. * testsuite/Makefile.am: New file. * testsuite/Makefile.in: New file. * testsuite/config/default.exp: New file. * testsuite/lib/libphobos-dg.exp: New file. * testsuite/lib/libphobos.exp: New file. * testsuite/testsuite_flags.in: New file. From-SVN: r265573
2018-10-28darwin - fix powerpc-darwin stack alignmentsIain Sandoe1-5/+33
2018-10-28 Iain Sandoe <iain@sandoe.co.uk> PR target/85669 * config/rs6000/darwin.h (STACK_BOUNDARY): New. (RS6000_STARTING_FRAME_OFFSET): Adjust to preserve 16byte alignment. (STACK_DYNAMIC_OFFSET): Likewise. From-SVN: r265568
2018-10-27re PR target/80024 (nios2: unclear wording "numeric digits" in diagnostic)Sandra Loosemore1-2/+2
2018-10-27 Sandra Loosemore <sandra@codesourcery.com> PR target/80024 gcc/ * config/nios2/nios2.c (nios2_valid_target_attribute_rec): Fix error message. From-SVN: r265561
2018-10-26rs6000-string.c (expand_strncmp_gpr_sequence): Change to a shorter sequence ↵Aaron Sawdey1-108/+137
with fewer branches. 2018-10-26 Aaron Sawdey <acsawdey@linux.ibm.com> * config/rs6000/rs6000-string.c (expand_strncmp_gpr_sequence): Change to a shorter sequence with fewer branches. (emit_final_str_compare_gpr): Ditto. From-SVN: r265546
2018-10-26[rs6000] Add compatible implementations of x86 SSSE3 intrinsicsPaul A. Clarke1-0/+502
This is a follow-on to earlier commits for adding compatibility implementations of x86 intrinsics for PPC64LE. This is the first of two patches. This patch adds the 32 x86 intrinsics from <tmmintrin.h> ("SSSE3"). (Patch 2/2 adds tests for these intrinsics, and briefly describes the tests performed.) gcc/ChangeLog: 2018-10-26 Paul A. Clarke <pc@us.ibm.com> * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. From-SVN: r265542
2018-10-26[rs6000] x86 vector intrinsics compatibility: clean-ups for 32bit support Paul A. Clarke2-61/+56
Implement various corrections in the compatibility implementations of the x86 vector intrinsics found after enabling 32bit mode for the associated test cases. (Actual enablement coming in a subsequent patch.) 2018-10-26 Paul A. Clarke <pc@us.ibm.com> gcc/ChangeLog: * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. From-SVN: r265535
2018-10-26[rs6000] Fix _mm_extract_pi16 for big-endianPaul A. Clarke1-2/+5
For compatibility implementation of x86 vector intrinsic, _mm_extract_pi16, adjust shift value for big-endian mode. gcc/ChangeLog: 2018-10-25 Paul A. Clarke <pc@us.ibm.com> * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. From-SVN: r265531
2018-10-25rs6000-c.c (P9V_BUILTIN_VEC_VSCEDPGT, [...]): Rename base overloaded name.Carl Love3-8/+58
gcc/ChangeLog: 2018-10-25 Carl Love <cel@us.ibm.com> * config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VEC_VSCEDPUO): Rename base overloaded name. Add quad precicion entry for each overloaded builtin. * config/rs6000/rs6000-builtin.def (VSCEDPGT, VSCEDPLT, VSCEDPEQ, VSCEDPUO): Rename overloaded name. (VSCEDPGT, VSCEQPGT, VSCEDPLT, VSCEQPLT, VSCEDPEQ, VSCEQPEQ, VSCEDPUO, VSCEQPUO): Add defitions for overloaded builtins. * config/rs6000/vsx.md (xscmpexpqp_<code>_<mode>): Add define_expand for xscmpexqp instruction. (*xscmpexpqp): Add define_insn for the xscmpexqp instruction. gcc/testsuite/ChangeLog: 2018-10-25 Carl Love <cel@us.ibm.com> * gcc.target/powerpc/float128-cmp2-runnable.c: New test file. From-SVN: r265509
2018-10-25emmintrin.h (_mm_slli_epi16): Replace deprecated function with vec_sl.Bill Schmidt1-16/+16
2018-10-25 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * config/rs6000/emmintrin.h (_mm_slli_epi16): Replace deprecated function with vec_sl. (_mm_slli_epi32): Likewise. (_mm_slli_epi64): Likewise. (_mm_srai_epi16): Replace deprecated function with vec_sra. (_mm_srai_epi32): Likewise. (_mm_srli_epi16): Replace deprecated function with vec_sr. (_mm_srli_epi32): Likewise. (_mm_srli_epi64): Likewise. (_mm_sll_epi16): Replace deprecated function with vec_sl. (_mm_sll_epi32): Likewise. (_mm_sll_epi64): Likewise. (_mm_sra_epi16): Replace deprecated function with vec_sra. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Replace deprecated function with vec_sr. (_mm_srl_epi32): Likewise. (_mm_srl_epi64): Likewise. Co-Authored-By: Jinsong Ji <jji@us.ibm.com> From-SVN: r265508
2018-10-25emmintrin.h (_mm_sll_epi16): Replace comparison operators with vec_cmp* for ↵Bill Schmidt1-28/+34
compatibility due to unfortunate... 2018-10-25 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * gcc/config/rs6000/emmintrin.h (_mm_sll_epi16): Replace comparison operators with vec_cmp* for compatibility due to unfortunate history; clean up formatting and use types more appropriately. (_mm_sll_epi32): Likewise. (_mm_sll_epi64): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_srl_epi64): Likewise. Co-Authored-By: Jinsong Ji <jji@us.ibm.com> From-SVN: r265507
2018-10-25emmintrin.h (_mm_sll_epi64): Remove wrong cast.Bill Schmidt2-4/+3
2018-10-25 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * config/rs6000/emmintrin.h (_mm_sll_epi64): Remove wrong cast. * config/rs6000/xmmintrin.h (_mm_min_ps): Change m's type to __vector __bool int. Use vec_cmpgt in preference to deprecated function vec_vcmpgtfp. (_mm_max_ps): Likewise. Co-Authored-By: Jinsong Ji <jji@us.ibm.com> From-SVN: r265506
2018-10-25rl78.c (insn_ok_now): Always re-recognize the insn if returning false.Jeff Law1-23/+29
* config/rl78/rl78.c (insn_ok_now): Always re-recognize the insn if returning false. From-SVN: r265505
2018-10-25S/390: Merge movdi_larl into movdi_64Ilya Leoshkevich3-17/+19
Consider the following RTL: (insn (set (mem/f/c:DI (reg/f:DI 60)) (const:DI (plus:DI (symbol_ref:DI ("*.LANCHOR0")) (const_int 8))))) generated by cse2 pass. It is matched to movdi_64, resulting in the following inefficient code: larl %r5,.L6 # Load literal pool@ lg %r1,.L7-.L6(%r5) # Load .LANCHOR0+8 stgrl %r1,.LANCHOR0 br %r14 Matching it to movdi_larl improves the code, eliminating one instruction and the literal pool entry: larl %r1,.LANCHOR0+8 stgrl %r1,.LANCHOR0 br %r14 Taking it one step further, there is no reason to keep movdi_64 and movdi_larl separate, since this could potentially improve code in other ways by giving lra one more alternative to choose from. gcc/ChangeLog: 2018-10-25 Ilya Leoshkevich <iii@linux.ibm.com> * config/s390/constraints.md (ZL): New constraint. * config/s390/s390.c (legitimate_pic_operand_p): Accept LARL operands. * config/s390/s390.md (movdi_larl): Remove. (movdi_64): Add the LARL alternative. gcc/testsuite/ChangeLog: 2018-10-25 Ilya Leoshkevich <iii@linux.ibm.com> * gcc.target/s390/global-array-almost-huge-element.c: New test. * gcc.target/s390/global-array-almost-negative-huge-element.c: New test. * gcc.target/s390/global-array-element-pic.c: New test. * gcc.target/s390/global-array-even-element.c: New test. * gcc.target/s390/global-array-huge-element.c: New test. * gcc.target/s390/global-array-negative-huge-element.c: New test. * gcc.target/s390/global-array-odd-element.c: New test. From-SVN: r265490
2018-10-24rs6000.c (TARGET_MANGLE_DECL_ASSEMBLER_NAME): Define as ↵Michael Meissner1-0/+73
rs6000_mangle_decl_assembler_name. [gcc] 2018-10-24 Michael Meissner <meissner@linux.ibm.com> * config/rs6000/rs6000.c (TARGET_MANGLE_DECL_ASSEMBLER_NAME): Define as rs6000_mangle_decl_assembler_name. (rs6000_mangle_decl_assembler_name): If the user switched from IBM long double to IEEE long double, switch the names of the long double built-in functions to be <func>f128 instead of <func>l. [gcc/testsuite] 2018-10-24 Michael Meissner <meissner@linux.ibm.com> * gcc.target/powerpc/float128-math.c: New test to make sure the long double built-in function names use the f128 form if the user switched from IBM long double to IEEE long double. * gcc.target/powerpc/ppc-fortran/ieee128-math.f90: Likewise. From-SVN: r265471
2018-10-24emmintrin.h (_mm_cvtpd_epi32): Change deprecated __vector long to __vector ↵William Schmidt1-6/+11
long long. 2018-10-24 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Change deprecated __vector long to __vector long long. (_mm_cvtpd_ps): Likewise. (_mm_cvttpd_epi32): Likewise. (_mm_cvtpi32_pd): Likewise. (_mm_unpackhi_epi64): Likewise. (_mm_unpacklo_epi64): Likewise. From-SVN: r265464
2018-10-24S/390: Fix ICE in s390_check_qrst_address ()Ilya Leoshkevich1-1/+3
In r265371 (S/390: Make "b" constraint match literal pool references) the CONSTANT_POOL_ADDRESS_P () check was moved from s390_loadrelative_operand_p () to s390_check_qrst_address (). However, in the original code it was guarded by SYMBOL_REF_P (), which was not added to the new code. gcc/ChangeLog: 2018-10-24 Ilya Leoshkevich <iii@linux.ibm.com> * config/s390/s390.c (s390_check_qrst_address): Add the missing SYMBOL_REF_P () check. gcc/testsuite/ChangeLog: 2018-10-24 Ilya Leoshkevich <iii@linux.ibm.com> * gcc.target/s390/20181024-1.c: New test. From-SVN: r265458
2018-10-23h8300.c (h8300_expand_prologue): Fix stm generation for H8/S.Jeff Law1-3/+3
* config/h8300/h8300.c (h8300_expand_prologue): Fix stm generation for H8/S. From-SVN: r265444
2018-10-23re PR target/87674 (AVX512: incorrect intrinsic signature)Jakub Jelinek3-6/+6
PR target/87674 * config/i386/avx512vlintrin.h (_mm_mask_mullo_epi32): Change type of second argument from __mmask16 to __mmask8. * config/i386/avx512vlbwintrin.h (_mm_mask_packus_epi32, _mm_mask_packs_epi32): Likewise. * config/i386/avx512pfintrin.h (_mm512_mask_prefetch_i64scatter_ps): Likewise. (_mm512_mask_prefetch_i64scatter_pd): Likewise. Formatting fix. From-SVN: r265416
2018-10-22rs6000: Handle print_operand_address for unexpected RTL (PR87598)Segher Boessenkool1-1/+1
As the PR shows, the user can force this to be called on at least some RTL that is not a valid address. Most targets treat this as if the user knows best; let's do the same. PR target/87598 * config/rs6000/rs6000.c (print_operand_address): For unexpected RTL call output_addr_const and hope for the best. From-SVN: r265392
2018-10-22Index...William Schmidt2-4/+8
Index: gcc/config/rs6000/emmintrin.h =================================================================== --- gcc/config/rs6000/emmintrin.h (revision 265318) +++ gcc/config/rs6000/emmintrin.h (working copy) @@ -85,7 +85,7 @@ typedef double __m128d __attribute__ ((__vector_si typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); -/* Define two value permute mask */ +/* Define two value permute mask. */ #define _MM_SHUFFLE2(x,y) (((x) << 1) | (y)) /* Create a vector with element 0 as F and the rest zero. */ @@ -201,7 +201,7 @@ _mm_store_pd (double *__P, __m128d __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_storeu_pd (double *__P, __m128d __A) { - *(__m128d *)__P = __A; + *(__m128d_u *)__P = __A; } /* Stores the lower DPFP value. */ @@ -2175,7 +2175,7 @@ _mm_maskmoveu_si128 (__m128i __A, __m128i __B, cha { __v2du hibit = { 0x7f7f7f7f7f7f7f7fUL, 0x7f7f7f7f7f7f7f7fUL}; __v16qu mask, tmp; - __m128i *p = (__m128i*)__C; + __m128i_u *p = (__m128i_u*)__C; tmp = (__v16qu)_mm_loadu_si128(p); mask = (__v16qu)vec_cmpgt ((__v16qu)__B, (__v16qu)hibit); Index: gcc/config/rs6000/xmmintrin.h =================================================================== --- gcc/config/rs6000/xmmintrin.h (revision 265318) +++ gcc/config/rs6000/xmmintrin.h (working copy) @@ -85,6 +85,10 @@ vector types, and their scalar components. */ typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +/* Unaligned version of the same type. */ +typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__, + __aligned__ (1))); + /* Internal data types for implementing the intrinsics. */ typedef float __v4sf __attribute__ ((__vector_size__ (16))); @@ -172,7 +176,7 @@ _mm_store_ps (float *__P, __m128 __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_storeu_ps (float *__P, __m128 __A) { - *(__m128 *)__P = __A; + *(__m128_u *)__P = __A; } /* Store four SPFP values in reverse order. The address must be aligned. */ From-SVN: r265389
2018-10-22S/390: Make "b" constraint match literal pool referencesIlya Leoshkevich1-4/+5
Improves the code generation by getting rid of redundant LAs, as seen in the following example: - la %r1,0(%r13) - lg %r4,0(%r1) + lg %r4,0(%r13) Also allows to proceed with the merge of movdi_64 and movdi_larl. Currently LRA decides to spill literal pool references back to the literal pool, because it preliminarily chooses alternatives with CT_MEMORY constraints without calling satisfies_memory_constraint_p (). Later on it notices that the constraint is wrong and fixes it by spilling. The constraint in this case is "b", and the operand is a literal pool reference. There is no reason to reject them. The current behavior was introduced, apparently unintentionally, by https://gcc.gnu.org/ml/gcc-patches/2010-09/msg00812.html The patch affects a little bit more than mentioned in the subject, because it changes s390_loadrelative_operand_p (), which is called not only for checking the "b" constraint. However, the only caller for which it should really not accept literal pool references is s390_check_qrst_address (), so it was changed to explicitly do so. gcc/ChangeLog: 2018-10-22 Ilya Leoshkevich <iii@linux.ibm.com> * config/s390/s390.c (s390_loadrelative_operand_p): Accept literal pool references. (s390_check_qrst_address): Adapt to the new behavior of s390_loadrelative_operand_p (). gcc/testsuite/ChangeLog: 2018-10-22 Ilya Leoshkevich <iii@linux.ibm.com> * gcc.target/s390/litpool-int.c: New test. From-SVN: r265371
2018-10-22i386: Enable AVX512 memory broadcast for INT andnotH.J. Lu1-0/+13
Many AVX512 vector operations can broadcast from a scalar memory source. This patch enables memory broadcast for INT andnot operations. gcc/ PR target/72782 * config/i386/sse.md (*andnot<mode>3_bcst): New. gcc/testsuite/ PR target/72782 * gcc.target/i386/avx512f-andn-di-zmm-1.c: New test. * gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise. * gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise. From-SVN: r265370
2018-10-22i386: Enable AVX512 memory broadcast for INT logicH.J. Lu1-0/+12
Many AVX512 vector operations can broadcast from a scalar memory source. This patch enables memory broadcast for INT logic operations. gcc/ PR target/72782 * config/i386/sse.md (*<code><mode>3_bcst): New. gcc/testsuite/ PR target/72782 * gcc.target/i386/avx512f-and-di-zmm-1.c: New test. * gcc.target/i386/avx512f-and-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-and-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-and-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-and-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-and-si-zmm-5.c: Likewise. * gcc.target/i386/avx512f-and-si-zmm-6.c: Likewise. * gcc.target/i386/avx512f-or-di-zmm-1.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-5.c: Likewise. * gcc.target/i386/avx512f-or-si-zmm-6.c: Likewise. * gcc.target/i386/avx512f-xor-di-zmm-1.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-5.c: Likewise. * gcc.target/i386/avx512f-xor-si-zmm-6.c: Likewise. * gcc.target/i386/avx512vl-and-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-and-si-ymm-1.c: Likewise. * gcc.target/i386/avx512vl-or-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-or-si-ymm-1.c: Likewise. * gcc.target/i386/avx512vl-xor-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-xor-si-ymm-1.c: Likewise. From-SVN: r265369
2018-10-22i386: Enable AVX512 memory broadcast for INT addH.J. Lu1-1/+28
Many AVX512 vector operations can broadcast from a scalar memory source. This patch enables memory broadcast for INT add operations. gcc/ PR target/72782 * config/i386/sse.md (avx512bcst): Updated for V4SI, V2DI, V8SI, V4DI, V16SI and V8DI. (*sub<mode>3<mask_name>_bcst): New. (*add<mode>3<mask_name>_bcst): Likewise. gcc/testsuite/ PR target/72782 * gcc.target/i386/avx512f-add-di-zmm-1.c: New test. * gcc.target/i386/avx512f-add-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-add-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-add-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-add-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-add-si-zmm-5.c: Likewise. * gcc.target/i386/avx512f-add-si-zmm-6.c: Likewise. * gcc.target/i386/avx512f-sub-di-zmm-1.c: Likewise. * gcc.target/i386/avx512f-sub-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-sub-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-sub-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-sub-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-sub-si-zmm-5.c: Likewise. * gcc.target/i386/avx512vl-add-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-add-si-ymm-1.c: Likewise. * gcc.target/i386/avx512vl-sub-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-sub-si-ymm-1.c: Likewise. From-SVN: r265368
2018-10-21emmintrin.h (_mm_movemask_pd): Replace __vector __m64 with __vector unsigned ↵William Schmidt2-26/+32
long long for compatibility. 2018-10-21 Bill Schmidt <wschmidt@linux.ibm.com> Jinsong Ji <jji@us.ibm.com> * config/rs6000/emmintrin.h (_mm_movemask_pd): Replace __vector __m64 with __vector unsigned long long for compatibility. (_mm_movemask_epi8): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtps_pi32): Likewise. (_mm_cvttps_pi32): Likewise. (_mm_cvtpi32_ps): Likewise. (_mm_cvtps_pi16): Likewise. (_mm_loadh_pi): Likewise. (_mm_storeh_pi): Likewise. (_mm_movehl_ps): Likewise. (_mm_movelh_ps): Likewise. (_mm_loadl_pi): Likewise. (_mm_storel_pi): Likewise. (_mm_movemask_ps): Likewise. (_mm_shuffle_pi16): Likewise. From-SVN: r265362
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