diff options
| author | H.J. Lu <hongjiu.lu@intel.com> | 2018-10-22 07:35:48 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-10-22 00:35:48 -0700 |
| commit | a48be73babd27c9deabf099b7202643dd447c9dc (patch) | |
| tree | fe7aa5f35d3d6c32c85c6ead27514e8bec36a5e9 /gcc/config | |
| parent | 0844e4324e7a6a92d76ff781e61ab086f528881d (diff) | |
| download | gcc-a48be73babd27c9deabf099b7202643dd447c9dc.zip gcc-a48be73babd27c9deabf099b7202643dd447c9dc.tar.gz gcc-a48be73babd27c9deabf099b7202643dd447c9dc.tar.bz2 | |
i386: Enable AVX512 memory broadcast for INT andnot
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT andnot operations.
gcc/
PR target/72782
* config/i386/sse.md (*andnot<mode>3_bcst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
From-SVN: r265370
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/sse.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e991da9..ee73e1f 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12102,6 +12102,19 @@ ] (const_string "<sseinsnmode>")))]) +(define_insn "*andnot<mode>3_bcst" + [(set (match_operand:VI 0 "register_operand" "=v") + (and:VI + (not:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand" "v")) + (vec_duplicate:VI48_AVX512VL + (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))] + "TARGET_AVX512F" + "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_insn "*andnot<mode>3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL |