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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-31 10:00:45 +0000 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2018-10-31 03:00:45 -0700 |
| commit | 563cc649beaf11d707c422e5f4e9e5cdacb818c3 (patch) | |
| tree | a4713d9eebef54bd572c5cbdd5238258187f98b8 /gcc/config | |
| parent | 7803ec5ee2a547043fb6708a08ddb1361ba91202 (diff) | |
| download | gcc-563cc649beaf11d707c422e5f4e9e5cdacb818c3.zip gcc-563cc649beaf11d707c422e5f4e9e5cdacb818c3.tar.gz gcc-563cc649beaf11d707c422e5f4e9e5cdacb818c3.tar.bz2 | |
aarch64: Force TImode values into even registers
The LSE CASP instruction requires values to be placed in even
register pairs. A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
16-byte modes held in GP registers to use an even regno.
From-SVN: r265661
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e646cce..9813a9d 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1452,10 +1452,14 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode) if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) return mode == Pmode; - if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16)) - return true; - - if (FP_REGNUM_P (regno)) + if (GP_REGNUM_P (regno)) + { + if (known_le (GET_MODE_SIZE (mode), 8)) + return true; + else if (known_le (GET_MODE_SIZE (mode), 16)) + return (regno & 1) == 0; + } + else if (FP_REGNUM_P (regno)) { if (vec_flags & VEC_STRUCT) return end_hard_regno (mode, regno) - 1 <= V31_REGNUM; |