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| author | H.J. Lu <hongjiu.lu@intel.com> | 2018-10-22 07:25:51 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-10-22 00:25:51 -0700 |
| commit | 26d50717b8fa7927e62f78092435db0e0c178035 (patch) | |
| tree | af7c6f63613051c9ddfe2123f718f020e1674906 /gcc/config | |
| parent | 0067ddcc0fca060a18243cec30d3d7f3931acbc3 (diff) | |
| download | gcc-26d50717b8fa7927e62f78092435db0e0c178035.zip gcc-26d50717b8fa7927e62f78092435db0e0c178035.tar.gz gcc-26d50717b8fa7927e62f78092435db0e0c178035.tar.bz2 | |
i386: Enable AVX512 memory broadcast for INT add
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT add operations.
gcc/
PR target/72782
* config/i386/sse.md (avx512bcst): Updated for V4SI, V2DI, V8SI,
V4DI, V16SI and V8DI.
(*sub<mode>3<mask_name>_bcst): New.
(*add<mode>3<mask_name>_bcst): Likewise.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-add-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-add-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512f-sub-di-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-add-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-add-si-ymm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-ymm-1.c: Likewise.
From-SVN: r265368
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/sse.md | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 28cecbf..c831ae2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -656,7 +656,10 @@ V16SF V8DF]) (define_mode_attr avx512bcst - [(V4SF "%{1to4%}") (V2DF "%{1to2%}") + [(V4SI "%{1to4%}") (V2DI "%{1to2%}") + (V8SI "%{1to8%}") (V4DI "%{1to4%}") + (V16SI "%{1to16%}") (V8DI "%{1to8%}") + (V4SF "%{1to4%}") (V2DF "%{1to2%}") (V8SF "%{1to8%}") (V4DF "%{1to4%}") (V16SF "%{1to16%}") (V8DF "%{1to8%}")]) @@ -10440,6 +10443,30 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "*sub<mode>3_bcst" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (minus:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand" "v") + (vec_duplicate:VI48_AVX512VL + (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))] + "TARGET_AVX512F && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)" + "vpsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}" + [(set_attr "type" "sseiadd") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "*add<mode>3_bcst" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (plus:VI48_AVX512VL + (vec_duplicate:VI48_AVX512VL + (match_operand:<ssescalarmode> 1 "memory_operand" "m")) + (match_operand:VI48_AVX512VL 2 "register_operand" "v")))] + "TARGET_AVX512F && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)" + "vpadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0|%0, %2, %1<avx512bcst>}" + [(set_attr "type" "sseiadd") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_insn "*<plusminus_insn><mode>3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL |