| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 4 hours | RISC-V: Support form 1 of integer scalar .SAT_ADDHEADtrunkmaster | Pan Li | 1 | -0/+11 |
| 7 days | RISC-V: Support IMM for operand 1 of ussub pattern | Pan Li | 1 | -1/+1 |
| 8 days | RISC-V: Support IMM for operand 0 of ussub pattern | Pan Li | 1 | -1/+1 |
| 2024-08-18 | RISC-V: Implement the quad and oct .SAT_TRUNC for scalar | Pan Li | 1 | -0/+20 |
| 2024-08-17 | [RISC-V][PR target/116282] Stabilize pattern conditions | Jeff Law | 1 | -8/+8 |
| 2024-08-15 | RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins | Vineet Gupta | 1 | -0/+63 |
| 2024-08-09 | RISC-V: Small stack tie changes | Raphael Moreira Zinsly | 1 | -1/+1 |
| 2024-08-08 | RISC-V: rv32/DF: Prevent 2 SImode loads using XTheadMemIdx | Christoph Müllner | 1 | -2/+2 |
| 2024-07-23 | RISC-V: Implement the .SAT_TRUNC for scalar | Pan Li | 1 | -0/+10 |
| 2024-07-15 | RISC-V: Implement locality for __builtin_prefetch | Monk Chiang | 1 | -3/+7 |
| 2024-07-15 | RISC-V: Add md files for vector BFloat16 | Feng Wang | 1 | -1/+12 |
| 2024-07-12 | [RISC-V] Avoid unnecessary sign extension after memcmp | Jeff Law | 1 | -2/+12 |
| 2024-07-11 | [to-be-committed,RISC-V] Eliminate unnecessary sign extension after inlined s... | Jeff Law | 1 | -4/+24 |
| 2024-06-29 | [to-be-committed,RISC-V,V4] movmem for RISCV with V extension | Sergei Lewis | 1 | -0/+22 |
| 2024-06-25 | [PATCH v2 3/3] RISC-V: cmpmem for RISCV with V extension | Sergei Lewis | 1 | -1/+6 |
| 2024-06-24 | [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension | Sergei Lewis | 1 | -2/+7 |
| 2024-06-08 | RISC-V: Implement .SAT_SUB for unsigned scalar int | Pan Li | 1 | -0/+11 |
| 2024-06-05 | RISC-V: Add Zfbfmin extension | Xiao Zeng | 1 | -7/+42 |
| 2024-05-28 | [to-be-committed] [RISC-V] Some basic patterns for zbkb code generation | Lyut Nersisyan | 1 | -3/+6 |
| 2024-05-26 | [to-be-committed][RISC-V] Reassociate constants in logical ops | Lyut Nersisyan | 1 | -0/+28 |
| 2024-05-24 | [to-be-committed,v2,RISC-V] Use bclri in constant synthesis | Jeff Law | 1 | -1/+1 |
| 2024-05-18 | [to-be-committed,RISC-V] Improve some shift-add sequences | Jeff Law | 1 | -0/+56 |
| 2024-05-18 | RISC-V: Fix "Nan-box the result of movbf on soft-bf16" | Xiao Zeng | 1 | -14/+5 |
| 2024-05-18 | RISC-V: Implement IFN SAT_ADD for both the scalar and vector | Pan Li | 1 | -0/+11 |
| 2024-05-15 | [v2,1/2] RISC-V: Add cmpmemsi expansion | Christoph Müllner | 1 | -0/+15 |
| 2024-05-14 | [to-be-committed,RISC-V] Remove redundant AND in shift-add sequence | Jeff Law | 1 | -0/+25 |
| 2024-05-14 | RISC-V: avoid LUI based const materialization ... [part of PR/106265] | Vineet Gupta | 1 | -0/+40 |
| 2024-05-14 | [PATCH 3/3] RISC-V: Add memset-zero expansion to cbo.zero | Christoph Müllner | 1 | -0/+24 |
| 2024-05-13 | Revert "[PATCH v2 1/3] RISC-V: movmem for RISCV with V extension" | Jeff Law | 1 | -23/+0 |
| 2024-05-13 | [PATCH v2 1/3] RISC-V: movmem for RISCV with V extension | Sergei Lewis | 1 | -0/+23 |
| 2024-05-08 | [PATCH v1 1/1] RISC-V: Nan-box the result of movbf on soft-bf16 | Xiao Zeng | 1 | -1/+11 |
| 2024-05-08 | RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4 | Christoph Müllner | 1 | -8/+17 |
| 2024-05-08 | RISC-V: Add zero_extract support for rv64gc | Christoph Müllner | 1 | -0/+30 |
| 2024-05-08 | RISC-V: Cover sign-extensions in lshrsi3_zero_extend_2 | Christoph Müllner | 1 | -4/+5 |
| 2024-05-06 | [RISC-V] Add support for _Bfloat16 | Xiao Zeng | 1 | -12/+12 |
| 2024-05-02 | [committed][RISC-V] Fix nearbyint failure on rv32 and formatting nits | Jeff Law | 1 | -31/+34 |
| 2024-05-02 | [RFA][RISC-V] Improve constant synthesis for constants with 2 bits set | Jeff Law | 1 | -1/+16 |
| 2024-04-30 | This is almost exclusively Jivan's work. His original post: | Jivan Hakobyan | 1 | -16/+195 |
| 2024-04-24 | Revert "RISC-V: Support highpart register overlap for vwcvt" | Pan Li | 1 | -24/+0 |
| 2024-04-22 | Revert "RISC-V: Rename vconstraint into group_overlap" | Pan Li | 1 | -11/+8 |
| 2024-04-22 | Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute" | Pan Li | 1 | -17/+2 |
| 2024-04-20 | Revert "RISC-V: Support one more overlap for wv instructions" | Pan Li | 1 | -10/+4 |
| 2024-04-08 | RISC-V: Implement TLS Descriptors. | Tatsuyuki Ishi | 1 | -1/+19 |
| 2024-03-18 | [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P | Mary Bennett | 1 | -1/+1 |
| 2024-03-18 | [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture. | Chen Jiawei | 1 | -1/+2 |
| 2024-03-01 | [14 regression] Fix insn types in risc-v port | Jeff Law | 1 | -14/+14 |
| 2024-02-21 | RISC-V: Add vector related pipelines | Edwin Lu | 1 | -0/+1 |
| 2024-02-21 | RISC-V: Add non-vector types to dfa pipelines | Edwin Lu | 1 | -9/+7 |
| 2024-02-16 | RISC-V: Fix *sge<u>_<X:mode><GPR:mode> pattern | Kito Cheng | 1 | -1/+1 |
| 2024-02-04 | RISC-V: Support scheduling for sifive p400 series | Monk Chiang | 1 | -1/+2 |
