aboutsummaryrefslogtreecommitdiff
path: root/gcc/common
AgeCommit message (Expand)AuthorFilesLines
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+1
2023-12-05RISC-V: Check if zcd conflicts with zcmt and zcmpKito Cheng1-0/+8
2023-12-04RISC-V: Update crypto vector ISA info with latest specFeng Wang1-2/+4
2023-12-04RISC-V: Refactor riscv_implied_info_t to make it able to handle conditional i...Kito Cheng1-11/+33
2023-12-04RISC-V: Refine riscv_subset_list::parse [NFC]Kito Cheng1-12/+19
2023-12-04i386: Fix CPUID of USER_MSR.Hu, Lin11-2/+2
2023-11-27RISC-V: Initial RV64E and LP64E supportTsukasa OI1-4/+4
2023-11-20Initial support for AVX10.1Haochen Jiang4-1/+92
2023-11-15RISC-V: Fix ICE in non-canonical march parsingPatrick O'Neill1-4/+13
2023-10-30i386: Zhaoxin yongfeng enablementMayshao3-5/+12
2023-10-22RISC-V: Prohibit combination of 'E' and 'H'Tsukasa OI1-0/+4
2023-10-22RISC-V: 'Zfa' extension is now ratifiedTsukasa OI1-1/+1
2023-10-18Initial Panther Lake SupportHaochen Jiang3-0/+12
2023-10-18Initial Clearwater Forest SupportHaochen Jiang3-0/+10
2023-10-12Support Intel USER_MSRHu, Lin14-0/+19
2023-10-11RISC-V: Extend riscv_subset_list, preparatory for target attribute supportKito Cheng1-0/+209
2023-10-11[PATCH v4 2/2] RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+2
2023-10-11[PATCH v4 1/2] RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+4
2023-10-09Initial support for -mevex512Haochen Jiang1-0/+15
2023-10-07[APX_EGPR] Initial support for APX_FKong Lingling4-1/+30
2023-09-08LoongArch: Enable -fsched-pressure by default at -O1 and higher.Guo Jie1-0/+1
2023-09-07RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' supportTsukasa OI1-0/+2
2023-09-05arc: Remove obsolete mbbit-peephole option and unused patterns.Claudiu Zissulescu1-1/+0
2023-08-29RISC-V: Add stub support for existing extensions (unprivileged)Tsukasa OI1-0/+1
2023-08-29RISC-V: Add stub support for existing extensions (vendor)Tsukasa OI1-0/+2
2023-08-29RISC-V: Add stub support for existing extensions (privileged)Tsukasa OI1-0/+18
2023-08-29LoongArch: Enable '-free' starting at -O2.Lulu Cheng1-0/+1
2023-08-28RISC-V: __builtin_riscv_pause for all environmentTsukasa OI1-0/+2
2023-08-25[PATCH v10] RISC-V: Add support for the Zfa extensionJin Ma1-0/+7
2023-08-24RISC-V: Enable pressure-aware scheduling by default.Robin Dapp1-0/+2
2023-08-24Revert "Initial support for AVX10.1"Haochen Jiang4-96/+1
2023-08-24Revert "Emit a warning when disabling AVX512 with AVX10 enabled or disabling ...Haochen Jiang1-54/+14
2023-08-24Revert "Emit a warning when AVX10 options conflict in vector width"Haochen Jiang1-20/+0
2023-08-24Fix target_clone ("arch=graniterapids-d") and target_clone ("arch=arrowlake-s")liuhongt1-4/+7
2023-08-21Support -march=gracemontliuhongt2-0/+5
2023-08-17Emit a warning when AVX10 options conflict in vector widthHaochen Jiang1-0/+20
2023-08-17Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 wi...Haochen Jiang1-14/+54
2023-08-17Initial support for AVX10.1Haochen Jiang4-1/+96
2023-08-14RISC-V: Minimal support for ZC* extensions.Jiawei1-0/+38
2023-08-14x86: Update model values for Raptorlake.Cui, Lili1-0/+1
2023-08-10RISC-V: Add Ztso atomic mappingsPatrick O'Neill1-0/+6
2023-08-09RISC-V: Remove non-existing 'Zve32d' extensionTsukasa OI1-1/+0
2023-08-09Rename local variable subleaf_level to max_subleaf_level.liuhongt1-3/+4
2023-08-09Workaround possible CPUID bug in Sandy Bridge.liuhongt1-39/+43
2023-08-02i386: refactor macros.Hu, Lin11-5/+5
2023-07-26[PATCH 1/5] [RISC-V] Recognize Zicond extensionXiao Zeng1-0/+3
2023-07-24[committed] Use single quote rather than backquote in RISC-V diagnosticJeff Law1-3/+3
2023-07-19RISC-V: Throw compilation error for unknown extensionsLehua Ding1-12/+56
2023-07-17RISC-V: Ensure all implied extensions are included [PR110696]Lehua Ding1-3/+30
2023-07-17Initial Lunar Lake, Arrow Lake and Arrow Lake S SupportMo, Zewei3-0/+27
generated by cgit v1.1 at 2024-08-23 07:31:24 +0000