RISC-V: Initial RV64E and LP64E support

Along with RV32E, RV64E is ratified.  Though ILP32E and LP64E ABIs are
still draft, it's worth supporting it.

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc
	(riscv_ext_version_table): Set version to ratified 2.0.
	(riscv_subset_list::parse_std_ext): Allow RV64E.
	* config.gcc: Parse base ISA 'rv64e' and ABI 'lp64e'.
	* config/riscv/arch-canonicalize: Parse base ISA 'rv64e'.
	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Define different macro per XLEN.  Add handling for ABI_LP64E.
	* config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi):
	Add handling for ABI_LP64E.
	* config/riscv/riscv-opts.h (enum riscv_abi_type): Add ABI_LP64E.
	* config/riscv/riscv.cc (riscv_option_override): Enhance error
	handling to support RV64E and LP64E.
	(riscv_conditional_register_usage): Change "RV32E" in a comment
	to "RV32E/RV64E".
	* config/riscv/riscv.h
	(UNITS_PER_FP_ARG): Add handling for ABI_LP64E.
	(STACK_BOUNDARY): Ditto.
	(ABI_STACK_BOUNDARY): Ditto.
	(MAX_ARGS_IN_REGISTERS): Ditto.
	(ABI_SPEC): Add support for "lp64e".
	* config/riscv/riscv.opt: Parse -mabi=lp64e as ABI_LP64E.
	* doc/invoke.texi: Add documentation of the LP64E ABI.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/predef-1.c: Test for __riscv_64e.
	* gcc.target/riscv/predef-2.c: Ditto.
	* gcc.target/riscv/predef-3.c: Ditto.
	* gcc.target/riscv/predef-4.c: Ditto.
	* gcc.target/riscv/predef-5.c: Ditto.
	* gcc.target/riscv/predef-6.c: Ditto.
	* gcc.target/riscv/predef-7.c: Ditto.
	* gcc.target/riscv/predef-8.c: Ditto.
	* gcc.target/riscv/predef-9.c: New test for RV64E and LP64E,
	based on predef-7.c.

1 files changed, 4 insertions, 4 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 5111626..ded85b4 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -169,9 +169,9 @@ struct riscv_ext_version
 static const struct riscv_ext_version riscv_ext_version_table[] =
 {
   /* name, ISA spec, major version, minor_version.  */
-  {"e", ISA_SPEC_CLASS_20191213, 1, 9},
-  {"e", ISA_SPEC_CLASS_20190608, 1, 9},
-  {"e", ISA_SPEC_CLASS_2P2,      1, 9},
+  {"e", ISA_SPEC_CLASS_20191213, 2, 0},
+  {"e", ISA_SPEC_CLASS_20190608, 2, 0},
+  {"e", ISA_SPEC_CLASS_2P2,      2, 0},
 
   {"i", ISA_SPEC_CLASS_20191213, 2, 1},
   {"i", ISA_SPEC_CLASS_20190608, 2, 1},
@@ -963,7 +963,7 @@ riscv_subset_list::parse_std_ext (const char *p)
 
       add ("e", major_version, minor_version, explicit_version_p, false);
 
-      if (m_xlen > 32)
+      if (m_xlen > 64)
 	{
 	  error_at (m_loc, "%<-march=%s%>: rv%de is not a valid base ISA",
 		    m_arch, m_xlen);