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author | Haochen Jiang <haochen.jiang@intel.com> | 2023-08-24 14:38:38 +0800 |
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committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-08-24 14:38:38 +0800 |
commit | 7e05cd632fab458717af4d4431c9f7e43ad062ad (patch) | |
tree | 3122b26c15111baae22b9ecf47cfbb1830f4dee9 /gcc/common | |
parent | cbd3b88382b5aea2781a2b7b34b0f27b4d0b19a0 (diff) | |
download | gcc-7e05cd632fab458717af4d4431c9f7e43ad062ad.zip gcc-7e05cd632fab458717af4d4431c9f7e43ad062ad.tar.gz gcc-7e05cd632fab458717af4d4431c9f7e43ad062ad.tar.bz2 |
Revert "Initial support for AVX10.1"
This reverts commit 11ad44da01dd1c91c96e45802fd8b1c50e88703f.
Diffstat (limited to 'gcc/common')
-rw-r--r-- | gcc/common/config/i386/cpuinfo.h | 36 | ||||
-rw-r--r-- | gcc/common/config/i386/i386-common.cc | 53 | ||||
-rw-r--r-- | gcc/common/config/i386/i386-cpuinfo.h | 3 | ||||
-rw-r--r-- | gcc/common/config/i386/i386-isas.h | 5 |
4 files changed, 1 insertions, 96 deletions
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 1652411..24ae0db 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -692,9 +692,6 @@ get_available_features (struct __processor_model *cpu_model, int amx_usable = 0; /* Check if KL is usable. */ int has_kl = 0; - /* Record AVX10 version. */ - int avx10_set = 0; - int version = 0; if ((ecx & bit_OSXSAVE)) { /* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and @@ -917,9 +914,6 @@ get_available_features (struct __processor_model *cpu_model, { if (eax & bit_AVX512BF16) set_feature (FEATURE_AVX512BF16); - /* AVX10 has the same XSTATE with AVX512. */ - if (edx & bit_AVX10) - avx10_set = 1; } if (amx_usable) { @@ -966,24 +960,6 @@ get_available_features (struct __processor_model *cpu_model, } } - /* Get Advanced Features at level 0x24 (eax = 0x24). */ - if (avx10_set && max_cpuid_level >= 0x24) - { - __cpuid (0x18, eax, ebx, ecx, edx); - version = ebx & 0xff; - if (ebx & bit_AVX10_256) - switch (version) - { - case 1: - set_feature (FEATURE_AVX10_1); - break; - default: - gcc_unreachable (); - } - if (ebx & bit_AVX10_512) - set_feature (FEATURE_AVX10_512BIT); - } - /* Check cpuid level of extended features. */ __cpuid (0x80000000, ext_level, ebx, ecx, edx); @@ -1188,18 +1164,6 @@ cpu_indicator_init (struct __processor_model *cpu_model, } } -#define SET_AVX10_512(A,B) \ - if (has_cpu_feature (cpu_model, cpu_features2, FEATURE_AVX10_##A)) \ - { \ - CHECK___builtin_cpu_supports (B); \ - set_cpu_feature (cpu_model, cpu_features2, FEATURE_AVX10_##A##_512); \ - } - - if (has_cpu_feature (cpu_model, cpu_features2, FEATURE_AVX10_512BIT)) - SET_AVX10_512 (1, "avx10.1-512"); - -#undef SET_AVX10_512 - gcc_assert (cpu_model->__cpu_vendor < VENDOR_MAX); gcc_assert (cpu_model->__cpu_type < CPU_TYPE_MAX); gcc_assert (cpu_model->__cpu_subtype < CPU_SUBTYPE_MAX); diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 9a3590f..95468b7 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -123,8 +123,6 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4 -#define OPTION_MASK_ISA2_AVX10_512BIT_SET OPTION_MASK_ISA2_AVX10_512BIT -#define OPTION_MASK_ISA2_AVX10_1_SET OPTION_MASK_ISA2_AVX10_1 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -234,8 +232,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX2_UNSET \ (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ - | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ - | OPTION_MASK_ISA2_AVX10_1_UNSET) + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ @@ -312,8 +309,6 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4 -#define OPTION_MASK_ISA2_AVX10_512BIT_UNSET OPTION_MASK_ISA2_AVX10_512BIT -#define OPTION_MASK_ISA2_AVX10_1_UNSET OPTION_MASK_ISA2_AVX10_1 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1346,52 +1341,6 @@ ix86_handle_option (struct gcc_options *opts, } return true; - case OPT_mavx10_max_512bit: - if (value) - { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_512BIT_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_512BIT_SET; - } - else - { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_512BIT_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_512BIT_UNSET; - } - return true; - - case OPT_mavx10_1: - if (value) - { - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; - } - else - { - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET; - } - return true; - - case OPT_mavx10_1_256: - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_512BIT_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_512BIT_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; - return true; - - case OPT_mavx10_1_512: - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET; - opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_512BIT_SET; - opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_512BIT_SET; - opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; - opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; - return true; - case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 8fbfb38..9153b4d 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -261,9 +261,6 @@ enum processor_features FEATURE_SM3, FEATURE_SHA512, FEATURE_SM4, - FEATURE_AVX10_512BIT, - FEATURE_AVX10_1, - FEATURE_AVX10_1_512, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 35be0cc..2297903 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -191,9 +191,4 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3") ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512") ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4") - ISA_NAMES_TABLE_ENTRY("avx10-max-512bit", FEATURE_AVX10_512BIT, - P_NONE, "-mavx10-max-512bit") - ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1, P_NONE, "-mavx10.1") - ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1, P_NONE, NULL) - ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, NULL) ISA_NAMES_TABLE_END |