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2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
2025-01-06RISC-V: Eliminate redundant instruction macroXiao Zeng1-1/+0
2025-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
2024-12-27LoongArch: Fix resolution of undefined weak hidden/protected symbolsXi Ruoyao1-0/+2
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+4
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore3-1790/+0
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclip...Nelson Chu2-0/+25
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei2-0/+17
2024-11-08aarch64: improve debuggability on array of enumMatthieu Longo1-3/+3
2024-11-08aarch64: change returned type to bool to match semantic of functionsMatthieu Longo1-1/+1
2024-11-08aarch64: make comment clearer about the locationMatthieu Longo1-1/+2
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira1-2/+2
2024-10-10s390: Add arch15 instructionsAndreas Krebbel1-0/+1
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei1-0/+10
2024-09-15MIPS/opcodes: Rework documentation for instruction argsMaciej W. Rozycki1-400/+402
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus1-4/+0
2024-09-07Add macros to get opcode of instructions approriatelyXin Wang1-5/+65
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2-0/+452
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2-0/+18
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2-2/+44
2024-08-06RISC-V: Add support for Zcmop extensionXiao Zeng2-0/+27
2024-08-06RISC-V: Add support for Zimop extensionXiao Zeng2-0/+123
2024-07-26microMIPS: Add MT ASE instruction set supportYunQiang Su1-3/+11
2024-07-19MIPS/opcodes: Replace "y" microMIPS operand code with "x"Maciej W. Rozycki1-2/+2
2024-07-19MIPS/opcodes: Remove the regular MIPS "+t" operand codeYunQiang Su1-2/+1
2024-07-19MIPS/opcodes: Discard unused OP_SH, OP_MASK, and OP_OP macrosMaciej W. Rozycki1-454/+0
2024-07-19MIPS/opcodes: Correct documentation for R6 operand typesMaciej W. Rozycki1-7/+6
2024-07-18opcodes: aarch64: enforce checks on subclass flags in aarch64-gen.cIndu Bhagat1-1/+2
2024-07-18include: opcodes: aarch64: define new subclassesIndu Bhagat1-1/+31
2024-07-12aarch64: Add support for sme2.1 zero instructions.Srinath Parvathaneni1-1/+10
2024-07-12aarch64: Add support for sme2.1 movaz instructions.Srinath Parvathaneni1-0/+1
2024-07-12aarch64: Add support for sme2.1 luti2 and luti4 instructions.Srinath Parvathaneni1-0/+1
2024-07-08aarch64: Add support for sve2p1 pmov instruction.srinath1-0/+8
2024-07-05aarch64: add STEP2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add SPMU2 feature and its associated registersMatthieu Longo1-0/+3
2024-07-05aarch64: add E3DSE feature and its associated registersMatthieu Longo1-1/+5
2024-06-28aarch64: Add support for Armv9.5-A architectureClaudio Bantaloukas1-0/+8
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei2-0/+7
2024-06-25aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.Srinath Parvathaneni1-3/+1
2024-06-25aarch64: Fix sve2p1 extq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Fix sve2p1 dupq instruction operands.Srinath Parvathaneni1-1/+1
2024-06-25aarch64: Enable mandatory feature bits for v9.4-A.Srinath Parvathaneni1-1/+2
2024-06-24aarch64: Add SME FP8 multiplication instructionsAndrew Carlotti1-0/+11
2024-06-24aarch64: Add FP8 Neon and SVE multiplication instructionsAndrew Carlotti1-6/+31
2024-06-24gas, aarch64: Add SME2 lutv2 extensionsaurabh.jha@arm.com1-0/+6
2024-06-23aarch64: Enable +cssc for armv8.9-aAndrew Carlotti1-0/+1
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu2-0/+4
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida2-0/+12
2024-06-13MIPS/opcodes: Rework INSN_* flags into a consistent blockMaciej W. Rozycki1-28/+25
2024-06-13MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREXMaciej W. Rozycki1-1/+1
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