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| author | YunQiang Su <yunqiang.su@cipunited.com> | 2024-07-19 19:01:52 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@redhat.com> | 2024-07-19 19:01:52 +0100 |
| commit | 73a833412e2d613be460a0daa3fc33568bec6c13 (patch) | |
| tree | 5cd4f5fbf6dd2c148b4b8d3127d5d76664181a1c /include/opcode | |
| parent | 31bd9f4682d611387993a8127a25ab42252b59c9 (diff) | |
| download | binutils-73a833412e2d613be460a0daa3fc33568bec6c13.zip binutils-73a833412e2d613be460a0daa3fc33568bec6c13.tar.gz binutils-73a833412e2d613be460a0daa3fc33568bec6c13.tar.bz2 | |
MIPS/opcodes: Remove the regular MIPS "+t" operand code
The semantics of the regular MIPS "+t" operand code is exactly the same
as that of the "E" operand code, so replace the former with the latter
in the single MFTC0 instruction with implicit 'sel' == 0 encoding where
it's used, matching the encoding with explicit 'sel' as well as other
instructions.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/mips.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f80110f..1e4b3e2 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -653,7 +653,6 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "y" 5 bit control target register (OP_*_RT) - "+t" 5 bit coprocessor 0 destination register (OP_*_RT) MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) @@ -760,7 +759,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "1234567890" "~!@#$%^&*|:'";\" "ABCEFGHIJKLMNOPQRSTUVWXZ" - "abcdefghijklmnopqrstuvwxyz" + "abcdefghijklmnopqrs uvwxyz" Extension character sequences used so far ("-" followed by the following), for quick reference when adding more: |