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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 11:30:24 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | f50b1a3c1f9514efdff6d808b2700eb18ab55630 (patch) | |
| tree | 2e56bf3b6c0291ba5507d7110f7e0e11774f1df0 /include/opcode | |
| parent | f5f38efc0a20cb50105da4fd2f656cda4561ccc2 (diff) | |
| download | binutils-f50b1a3c1f9514efdff6d808b2700eb18ab55630.zip binutils-f50b1a3c1f9514efdff6d808b2700eb18ab55630.tar.gz binutils-f50b1a3c1f9514efdff6d808b2700eb18ab55630.tar.bz2 | |
aarch64: Fix sve2p1 extq instruction operands.
This patch fixes the syntax of sve2p1 "extq" instruction by modifying the operands
count to 4. A new operand AARCH64_OPND_SVE_UIMM4 is defined to handle the 4th
argument an 4-bit unsigned immediate of extq instruction. The instruction encoding
is updated to use constraint C_SCAN_MOVPRFX, to enable "extq" instruction to immediately
precede in program order by a MOVPRFX instruction. Also removed the unused operand
AARCH64_OPND_SVE_Zm_imm4.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 78f19b6..a178e8c 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -757,6 +757,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ + AARCH64_OPND_SVE_UIMM4, /* SVE unsigned 4-bit immediate. */ AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ @@ -783,7 +784,6 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ - AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ |