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AgeCommit message (Expand)AuthorFilesLines
2018-10-03AArch64: Add SVE constraints verifier.Tamar Christina1-2/+8
2018-10-03AArch64: Refactor verifiers to make more general.Tamar Christina1-1/+3
2018-10-03AArch64: Refactor err_type.Tamar Christina1-1/+11
2018-10-03AArch64: Wire through instr_sequenceTamar Christina1-2/+22
2018-10-03AArch64: Mark sve instructions that require MOVPRFX constraintsTamar Christina1-2/+16
2018-10-02RISC-V: Add fence.tso instructionPalmer Dabbelt1-0/+2
2018-09-20Andes Technology has good news for you, we plan to update the nds32 port of b...Nick Clifton1-23/+181
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-2/+8
2018-08-29[MIPS] Add Loongson 2K1000 proccessor support.Chenghua Xu1-0/+1
2018-08-29[MIPS] Add Loongson 3A2000/3A3000 proccessor support.Chenghua Xu1-0/+1
2018-08-29[MIPS] Add Loongson 3A1000 proccessor support.Chenghua Xu1-7/+2
2018-08-29[MIPS/GAS] Add Loongson EXT2 Instructions support.Chenghua Xu1-0/+2
2018-08-29[MIPS/GAS] Split Loongson EXT Instructions from loongson3a.Chenghua Xu1-0/+2
2018-08-29[MIPS/GAS] Split Loongson CAM Instructions from loongson3aChenghua Xu1-0/+2
2018-08-21Use operand->extract to provide defaults for optional PowerPC operandsAlan Modra1-18/+22
2018-08-18S12Z: Move opcode header to public include directory.John Darrington1-0/+71
2018-08-06[ARC] Update handling AUX-registers.claziss1-0/+1
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-07-30Add support for the C_SKY series of processors.Andrew Jenner1-0/+110
2018-07-26PowerPC Improve support for Gekko & BroadwayAlex Chadwick1-1/+1
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu1-0/+2
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina1-0/+2
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker1-1/+6
2018-06-13MIPS: Add CRC ASE supportScott Egerton1-0/+3
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner1-8/+0
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina1-1/+5
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina1-1/+3
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina1-3/+12
2018-05-15Fix error messages in the NFP sources when building for 32-bit targets.Francois H. Theron1-55/+50
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson1-0/+6
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner1-3/+3
2018-04-30This patch adds support to objdump for disassembly of NFP (Netronome Flow Pro...Francois H. Theron1-0/+180
2018-04-16Remove m88k supportAlan Modra1-454/+0
2018-04-16Remove i370 supportAlan Modra1-266/+0
2018-04-16Remove tahoe supportAlan Modra1-232/+0
2018-04-11Remove i860, i960, bout and aout-adobe targetsAlan Modra2-1031/+0
2018-03-28Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+R...Nick Clifton1-0/+1
2018-03-14RISC-V: Add .insn support.Jim Wilson1-0/+21
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-6/+0
2018-02-27[ARM] Remove ARM_FEATURE_COPY macroThomas Preud'homme1-9/+0
2018-02-20MIPS16/opcodes: Free up `M' operand codeMaciej W. Rozycki1-3/+2
2018-01-04RISC-V: Add 2 missing privileged registers.Jim Wilson1-4/+8
2018-01-03Update year range in copyright notice of binutils filesAlan Modra72-72/+72
2017-12-28RISC-V: Add missing privileged spec registers.Jim Wilson1-148/+208
2017-12-19Correct disassembly of dot product instructions.Tamar Christina1-0/+5
2017-12-19Add support for V_4B so we can properly reject it.Tamar Christina1-0/+1
2017-12-01Use consistent types for holding instructions, instruction masks, etc.Peter Bergner1-7/+15
2017-11-16Add new AArch64 FP16 FM{A|S} instructions.Tamar Christina1-1/+3
2017-11-15Separate the new FP16 instructions backported from Armv8.4-a to Armv8.2-a int...Tamar Christina1-1/+2
2017-11-09Enable the Dot Product extension by default for Armv8.4-a.Tamar Christina1-1/+2
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