AArch64: Mark sve instructions that require MOVPRFX constraints

This patch series is to allow certain instructions such as the SVE MOVPRFX
instruction to apply a constraint/dependency on the instruction at PC+4.

This patch starts this off by marking which instructions impose the constraint
and which instructions must adhere to the constraint.  This is done in a
generic way by extending the verifiers.

* The constraint F_SCAN indicates that an instruction opens a sequence and imposes
a constraint on an instructions following it.  The length of the sequence depends
on the instruction itself and it handled in the verifier code.

* The C_SCAN_MOVPRFX flag is used to indicate which constrain the instruction is
checked against.  An instruction with both F_SCAN and C_SCAN_MOVPRFX starts a
block for the C_SCAN_MOVPRFX instruction, and one with only C_SCAN_MOVPRFX must
adhere to a previous block constraint is applicable.

The SVE instructions in this list have been marked according to the SVE
specification[1].

[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

include/

	* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
	extend flags field size.
	(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.

opcodes/

	* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
	_LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
	_SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
	V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
	constraints.
	(_SVE_INSNC): New.
	(struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
	constraints.
	(movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
	F_SCAN flags.
	(msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
	sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
	sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
	sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
	uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
	uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
	C_SCAN_MOVPRFX and C_MAX_ELEM constraints.

1 files changed, 16 insertions, 2 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7141927..c7d9008 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -700,7 +700,10 @@ struct aarch64_opcode
   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 
   /* Flags providing information about this instruction */
-  uint32_t flags;
+  uint64_t flags;
+
+  /* Extra constraints on the instruction that the verifier checks.  */
+  uint32_t constraints;
 
   /* If nonzero, this operand and operand 0 are both registers and
      are required to have the same register number.  */
@@ -771,7 +774,18 @@ extern aarch64_opcode aarch64_opcode_table[];
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
 #define F_SYS_WRITE (1ULL << 30)
-/* Next bit is 31.  */
+/* This instruction has an extra constraint on it that imposes a requirement on
+   subsequent instructions.  */
+#define F_SCAN (1ULL << 31)
+/* Next bit is 32.  */
+
+/* Instruction constraints.  */
+/* This instruction has a predication constraint on the instruction at PC+4.  */
+#define C_SCAN_MOVPRFX (1U << 0)
+/* This instruction's operation width is determined by the operand with the
+   largest element size.  */
+#define C_MAX_ELEM (1U << 1)
+/* Next bit is 2.  */
 
 static inline bfd_boolean
 alias_opcode_p (const aarch64_opcode *opcode)