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2024-06-05RISC-V: Tidy vendor core-v extension gas testcasesNelson Chu146-1629/+1393
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett67-0/+725
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett17-0/+86
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett9-0/+186
2024-06-04LoongArch: Make align symbol be in same section with alignment directivemengqinggang3-3/+38
2024-06-04arm: testsuite: fix msdos line endings in testsRichard Earnshaw2-18/+18
2024-05-31aarch64, testsuite: avoid regexes in opcode fieldClaudio Bantaloukas2-493/+493
2024-05-31gas, aarch64: Fixes in texi and tests following faminmax and lut changessaurabh.jha@arm.com3-154/+154
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich31-157/+101
2024-05-29x86/Intel: SHLD/SHRD have dual meaningJan Beulich3-0/+74
2024-05-28gas, aarch64: Add SVE2 lut extensionsaurabh.jha@arm.com8-1/+461
2024-05-28gas, aarch64: Add AdvSIMD lut extensionsaurabh.jha@arm.com7-0/+428
2024-05-24Re: LoongArch: gas: Adjust DWARF CIE alignment factorsAlan Modra1-22/+22
2024-05-24gas: extend \+ support to .irp / .irpcJan Beulich4-14/+10
2024-05-24gas: adjust handling of quotes for .irpcJan Beulich3-0/+26
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich2-0/+9
2024-05-22aarch64: fix incorrect encoding for system register pmsdsfr_el1Matthieu Longo1-2/+2
2024-05-22Support APX zero-upperCui, Lili6-0/+285
2024-05-22Add check for 8-bit old registers in EVEX formatCui, Lili2-0/+5
2024-05-20aarch64: Add support for the fpmr system registerClaudio Bantaloukas4-0/+23
2024-05-17aarch64: correct SVE2.1 ld2q (scalar plus scalar)Jan Beulich1-1/+1
2024-05-17aarch64: correct SVE2.1 ld{3,4}q / st{3,4}q (scalar plus immediate)Jan Beulich3-13/+13
2024-05-16aarch64: fp8 convert and scale - add sme2 insn variantsVictor Do Nascimento6-2/+623
2024-05-16aarch64: fp8 convert and scale - add sve2 insn variantsVictor Do Nascimento7-0/+313
2024-05-16aarch64: fp8 convert and scale - Add advsimd insn variantsVictor Do Nascimento5-0/+581
2024-05-16aarch64: add SPMU feature and its associated registersMatthieu Longo3-0/+27
2024-05-16Move assembler "IRP \+" test into a separate file. Add XFAILs for targets th...Nick Clifton6-9/+19
2024-05-16Fix FAIL: macros altmacroAlan Modra1-5/+5
2024-05-15gas: Fix \+ expansion for .irp and .irpcFangrui Song2-0/+9
2024-05-15aarch64: testsuite: share test utils macros and use themMatthieu Longo23-519/+576
2024-05-15aarch64: testsuite: reorder write and read to match macro orderMatthieu Longo11-292/+286
2024-05-15aarch64: testsuite: use same regs for read and write testsMatthieu Longo8-377/+377
2024-05-15aarch64: testsuite: replace instruction addresses by regexMatthieu Longo1-28/+28
2024-05-14Fix gas's 'macro count' test for various targetsNick Clifton1-10/+10
2024-05-14arm: opcodes: remove Maverick disassembly.Richard Earnshaw2-8/+8
2024-05-14arm: remove tests for Maverick FPU extensionsRichard Earnshaw12-2010/+0
2024-05-13Add new assembler macro pseudo-variable \+ which counts the number of times a...Nick Clifton6-3/+40
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu13-10/+25
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili2-0/+14
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich3-0/+974
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich5-0/+603
2024-04-25bpf: fix calculation when deciding to relax branchDavid Faust6-39/+62
2024-04-25LoongArch: gas: Simplify relocations in sections without code flagJinyang He2-0/+18
2024-04-23arm: Fix MVE vmla encodingClaudio Bantaloukas2-1353/+2039
2024-04-22x86/APX: Add invalid check for APX EVEX.X4.Cui, Lili2-0/+5
2024-04-20LoongArch: Add -mignore-start-align optionmengqinggang2-1/+1
2024-04-10x86-64: Use long NOPs for Intel Core processorsH.J. Lu4-4/+362
2024-04-10gas: scfi: bugfixes for SCFI state propagationIndu Bhagat4-0/+75
2024-04-10gas: gcfg: add_bb_at_ginsn must return root_bbIndu Bhagat4-0/+89
2024-04-09arm: Fix disassembly of MVE vq[r]shr[u]nAlex Coplan3-1808/+1875