aarch64: fp8 convert and scale - add sve2 insn variants

Add the SVE2 variant of the FP8 convert and scale instructions,
enabled at assembly-time using the `+sve2+fp8' architectural
extension flag.  More specifically, support is added for the
following instructions:

FP8 convert to BFloat16 (bottom/top):
-------------------------------------

  - bf1cvt Z<d>.H, Z<n>.B
  - bf2cvt Z<d>.H, Z<n>.B
  - bf1cvtlt Z<d>.H, Z<n>.B
  - bf2cvtlt Z<d>.H, Z<n>.B

FP8 convert to half-precision (bottom/top):
-------------------------------------------

  - f1cvt Z<d>.H, Z<n>.B
  - f2cvt Z<d>.H, Z<n>.B
  - f1cvtlt Z<d>.H, Z<n>.B
  - f2cvtlt Z<d>.H, Z<n>.B

BFloat16/half-precision convert, narrow and
interleave to FP8:
-------------------------------------------

  - bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
  - fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }

Single-precision convert, narrow and interleave
to FP8 (bottom/top):
-----------------------------------------------

  - fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S }
  - fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }

7 files changed, 313 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d b/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
new file mode 100644
index 0000000..16ed6b8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-fp8-streaming.d
@@ -0,0 +1,4 @@
+#as: -march=armv8.5-a+fp8+sme2
+#objdump: -dr
+#source: sve2-fp8.s
+#dump: sve2-fp8-dump
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-dump b/gas/testsuite/gas/aarch64/sve2-fp8-dump
new file mode 100644
index 0000000..570ff9c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-dump
@@ -0,0 +1,53 @@
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+:	65083800 	bf1cvt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65083801 	bf1cvt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65083820 	bf1cvt	z0.h, z1.b
+[ ]*[0-9a-f]+:	65083bfe 	bf1cvt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65083c00 	bf2cvt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65083c01 	bf2cvt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65083c20 	bf2cvt	z0.h, z1.b
+[ ]*[0-9a-f]+:	65083ffe 	bf2cvt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65093800 	bf1cvtlt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65093801 	bf1cvtlt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65093820 	bf1cvtlt	z0.h, z1.b
+[ ]*[0-9a-f]+:	65093bfe 	bf1cvtlt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65093c00 	bf2cvtlt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65093c01 	bf2cvtlt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65093c20 	bf2cvtlt	z0.h, z1.b
+[ ]*[0-9a-f]+:	65093ffe 	bf2cvtlt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65083000 	f1cvt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65083001 	f1cvt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65083020 	f1cvt	z0.h, z1.b
+[ ]*[0-9a-f]+:	650833fe 	f1cvt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65083400 	f2cvt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65083401 	f2cvt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65083420 	f2cvt	z0.h, z1.b
+[ ]*[0-9a-f]+:	650837fe 	f2cvt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65093000 	f1cvtlt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65093001 	f1cvtlt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65093020 	f1cvtlt	z0.h, z1.b
+[ ]*[0-9a-f]+:	650933fe 	f1cvtlt	z30.h, z31.b
+[ ]*[0-9a-f]+:	65093400 	f2cvtlt	z0.h, z0.b
+[ ]*[0-9a-f]+:	65093401 	f2cvtlt	z1.h, z0.b
+[ ]*[0-9a-f]+:	65093420 	f2cvtlt	z0.h, z1.b
+[ ]*[0-9a-f]+:	650937fe 	f2cvtlt	z30.h, z31.b
+[ ]*[0-9a-f]+:	650a3800 	bfcvtn	z0.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+:	650a3801 	bfcvtn	z1.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+:	650a3840 	bfcvtn	z0.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+:	650a3bdd 	bfcvtn	z29.b, {z30.h-z31.h}
+[ ]*[0-9a-f]+:	650a3000 	fcvtn	z0.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+:	650a3001 	fcvtn	z1.b, {z0.h-z1.h}
+[ ]*[0-9a-f]+:	650a3040 	fcvtn	z0.b, {z2.h-z3.h}
+[ ]*[0-9a-f]+:	650a33dd 	fcvtn	z29.b, {z30.h-z31.h}
+[ ]*[0-9a-f]+:	650a3400 	fcvtnb	z0.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+:	650a3401 	fcvtnb	z1.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+:	650a3440 	fcvtnb	z0.b, {z2.s-z3.s}
+[ ]*[0-9a-f]+:	650a37dd 	fcvtnb	z29.b, {z30.s-z31.s}
+[ ]*[0-9a-f]+:	650a3c00 	fcvtnt	z0.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+:	650a3c01 	fcvtnt	z1.b, {z0.s-z1.s}
+[ ]*[0-9a-f]+:	650a3c40 	fcvtnt	z0.b, {z2.s-z3.s}
+[ ]*[0-9a-f]+:	650a3fdd 	fcvtnt	z29.b, {z30.s-z31.s}
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.d b/gas/testsuite/gas/aarch64/sve2-fp8-fail.d
new file mode 100644
index 0000000..f20d457
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8+sve2 -mno-verbose-error
+#error_output: sve2-fp8-fail.l
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.l b/gas/testsuite/gas/aarch64/sve2-fp8-fail.l
new file mode 100644
index 0000000..ab48ff4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.l
@@ -0,0 +1,161 @@
+[^:]+: Assembler messages:
+[^:]+:6: Error: operand mismatch -- `bf1cvt z0.b,z1.b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvt z0.s,z1.b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvt z0.d,z1.b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf1cvt z0.h,z1.h'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvt z0.h,z1.s'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvt z0.h,z1.d'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf1cvt z0.h,p0,z1.d'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf1cvt z0.h,p0/z,z1.d'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf2cvt z0.b,z1.b'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvt z0.s,z1.b'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvt z0.d,z1.b'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf2cvt z0.h,z1.h'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvt z0.h,z1.s'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvt z0.h,z1.d'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf2cvt z0.h,p0,z1.d'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf2cvt z0.h,p0/z,z1.d'
+[^:]+:31:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf1cvtlt z0.b,z1.b'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf1cvtlt z0.s,z1.b'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf1cvtlt z0.d,z1.b'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf1cvtlt z0.h,z1.h'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtlt z0.h,z1.s'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtlt z0.h,z1.d'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf1cvtlt z0.h,p0,z1.d'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf1cvtlt z0.h,p0/z,z1.d'
+[^:]+:32:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `bf2cvtlt z0.b,z1.b'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `bf2cvtlt z0.s,z1.b'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtlt z0.d,z1.b'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `bf2cvtlt z0.h,z1.h'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtlt z0.h,z1.s'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtlt z0.h,z1.d'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `bf2cvtlt z0.h,p0,z1.d'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `bf2cvtlt z0.h,p0/z,z1.d'
+[^:]+:33:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f1cvt z0.b,z1.b'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvt z0.s,z1.b'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvt z0.d,z1.b'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f1cvt z0.h,z1.h'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvt z0.h,z1.s'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvt z0.h,z1.d'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f1cvt z0.h,p0,z1.d'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f1cvt z0.h,p0/z,z1.d'
+[^:]+:34:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f2cvt z0.b,z1.b'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvt z0.s,z1.b'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvt z0.d,z1.b'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f2cvt z0.h,z1.h'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvt z0.h,z1.s'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvt z0.h,z1.d'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f2cvt z0.h,p0,z1.d'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f2cvt z0.h,p0/z,z1.d'
+[^:]+:35:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f1cvtlt z0.b,z1.b'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f1cvtlt z0.s,z1.b'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtlt z0.d,z1.b'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f1cvtlt z0.h,z1.h'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtlt z0.h,z1.s'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtlt z0.h,z1.d'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f1cvtlt z0.h,p0,z1.d'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f1cvtlt z0.h,p0/z,z1.d'
+[^:]+:36:  Info: macro invoked from here
+[^:]+:6: Error: operand mismatch -- `f2cvtlt z0.b,z1.b'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:8: Error: operand mismatch -- `f2cvtlt z0.s,z1.b'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtlt z0.d,z1.b'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:12: Error: operand mismatch -- `f2cvtlt z0.h,z1.h'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtlt z0.h,z1.s'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtlt z0.h,z1.d'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:16: Error: expected an SVE vector register at operand 2 -- `f2cvtlt z0.h,p0,z1.d'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:17: Error: expected an SVE vector register at operand 2 -- `f2cvtlt z0.h,p0/z,z1.d'
+[^:]+:37:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bfcvtn z1.h,{z0.h-z1.h}'
+[^:]+:39:  Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `bfcvtn z0.s,{z0.h-z1.h}'
+[^:]+:39:  Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `bfcvtn z7.d,{z0.h-z1.h}'
+[^:]+:39:  Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `bfcvtn z0.b,{z1.h-z2.h}'
+[^:]+:39:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtn z1.h,{z0.h-z1.h}'
+[^:]+:40:  Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtn z0.s,{z0.h-z1.h}'
+[^:]+:40:  Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtn z7.d,{z0.h-z1.h}'
+[^:]+:40:  Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtn z0.b,{z1.h-z2.h}'
+[^:]+:40:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtnb z1.h,{z0.s-z1.s}'
+[^:]+:41:  Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtnb z0.s,{z0.s-z1.s}'
+[^:]+:41:  Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtnb z7.d,{z0.s-z1.s}'
+[^:]+:41:  Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtnb z0.b,{z1.s-z2.s}'
+[^:]+:41:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `fcvtnt z1.h,{z0.s-z1.s}'
+[^:]+:42:  Info: macro invoked from here
+[^:]+:24: Error: operand mismatch -- `fcvtnt z0.s,{z0.s-z1.s}'
+[^:]+:42:  Info: macro invoked from here
+[^:]+:25: Error: operand mismatch -- `fcvtnt z7.d,{z0.s-z1.s}'
+[^:]+:42:  Info: macro invoked from here
+[^:]+:27: Error: start register out of range at operand 2 -- `fcvtnt z0.b,{z1.s-z2.s}'
+[^:]+:42:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8-fail.s b/gas/testsuite/gas/aarch64/sve2-fp8-fail.s
new file mode 100644
index 0000000..057bb62
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8-fail.s
@@ -0,0 +1,42 @@
+	/* sve-fp8-fail.s Test file for error-checking AArch64 SVE 8-bit
+	floating-point vector instructions.  */
+
+	.macro cvt_pat1, op
+	/* Check element width qualifier for destination register.  */
+	\op	z0.b, z1.b
+	\op	z0.h, z1.b /* Valid.  */
+	\op	z0.s, z1.b
+	\op	z0.d, z1.b
+	/* Check element width qualifier for source register.  */
+	\op	z0.h, z1.b /* Valid.  */
+	\op	z0.h, z1.h
+	\op	z0.h, z1.s
+	\op	z0.h, z1.d
+	/* Ensure predicate register is not allowed.  */
+	\op	z0.h, p0, z1.d
+	\op	z0.h, p0/z, z1.d
+	.endm
+
+	.macro cvt_pat2, op, width
+	/* Check element width qualifier for destination register.  */
+	\op	z0.b, { z0.\width - z1.\width } /* Valid.  */
+	\op	z1.h, { z0.\width - z1.\width }
+	\op	z0.s, { z0.\width - z1.\width }
+	\op	z7.d, { z0.\width - z1.\width }
+	/* Check whether source register range starts at even register.  */
+	\op	z0.b, { z1.\width - z2.\width }
+	.endm
+
+	cvt_pat1 bf1cvt
+	cvt_pat1 bf2cvt
+	cvt_pat1 bf1cvtlt
+	cvt_pat1 bf2cvtlt
+	cvt_pat1 f1cvt
+	cvt_pat1 f2cvt
+	cvt_pat1 f1cvtlt
+	cvt_pat1 f2cvtlt
+
+	cvt_pat2 bfcvtn, h
+	cvt_pat2 fcvtn, h
+	cvt_pat2 fcvtnb, s
+	cvt_pat2 fcvtnt, s
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8.d b/gas/testsuite/gas/aarch64/sve2-fp8.d
new file mode 100644
index 0000000..774b8e7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8.d
@@ -0,0 +1,3 @@
+#as: -march=armv8.5-a+fp8+sve2
+#objdump: -dr
+#dump: sve2-fp8-dump
diff --git a/gas/testsuite/gas/aarch64/sve2-fp8.s b/gas/testsuite/gas/aarch64/sve2-fp8.s
new file mode 100644
index 0000000..62dee73
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-fp8.s
@@ -0,0 +1,48 @@
+	/* sve-fp8.s Test file for AArch64 SVE 8-bit floating-point vector
+	instructions.  */
+
+	.macro cvt_pat1, op
+	\op	z0.h, z0.b
+	\op	z1.h, z0.b
+	\op	z0.h, z1.b
+	\op	z30.h, z31.b
+	.endm
+
+	.macro cvt_pat2, op, width
+	\op	z0.b, { z0.\width - z1.\width }
+	\op	z1.b, { z0.\width - z1.\width }
+	\op	z0.b, { z2.\width - z3.\width }
+	\op	z29.b, { z30.\width - z31.\width }
+	.endm
+
+	/* 8-bit floating-point convert to BFloat16 (top/bottom) with scaling by
+	2^-UInt(FPMR.LSCALE{2}[5:0]).  */
+
+	cvt_pat1 bf1cvt
+	cvt_pat1 bf2cvt
+	cvt_pat1 bf1cvtlt
+	cvt_pat1 bf2cvtlt
+
+	/* 8-bit floating-point convert to half-precision (top/bottom) with
+	scaling by 2^-UInt(FPMR.LSCALE{2}[3:0]).  */
+
+	cvt_pat1 f1cvt
+	cvt_pat1 f2cvt
+	cvt_pat1 f1cvtlt
+	cvt_pat1 f2cvtlt
+
+	/* BFloat16 convert, narrow and interleave to 8-bit floating-point
+	with scaling by 2^SInt(FPMR.NSCALE).  */
+
+	cvt_pat2 bfcvtn, h
+
+	/* Half-precision convert, narrow and interleave to 8-bit floating-point
+	with scaling by 2^SInt(FPMR.NSCALE[4:0]).  */
+
+	cvt_pat2 fcvtn, h
+
+	/* Single-precision convert, narrow and interleave to 8-bit
+	floating-point (top/bottom) 2^SInt(FPMR.NSCALE).  */
+
+	cvt_pat2 fcvtnb, s
+	cvt_pat2 fcvtnt, s