aarch64: fp8 convert and scale - Add advsimd insn variants

Add the advanced SIMD variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+fp8'
architectural extension flag.  More specifically, support is
added for the following instructions:

FP8 convert to BFloat16 (vector):
---------------------------------

  - bf1cvtl V<d>.8H, V<n>.8B
  - bf2cvtl V<d>.8H, V<n>.8B
  - bf1cvtl2 V<d>.8H, V<n>.16B
  - bf2cvtl2 V<d>.8H, V<n>.16B

FP8 convert to half-precision (vector):
---------------------------------------

  - f1cvtl V<d>.8H, V<n>.8B
  - f2cvtl V<d>.8H, V<n>.8B
  - f1cvtl2 V<d>.8H, V<n>.16B
  - f2cvtl2 V<d>.8H, V<n>.16B

Single-precision to FP8 convert and narrow (vector):
----------------------------------------------------

  - fcvtn V<d>.8B, V<n>.4S, V<m>.4S
  - fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S

Half-precision to FP8 convert and narrow (vector):
--------------------------------------------------

  - fcvtn V<d>.8B, V<n>.4H, V<m>.4H
  - fcvtn V<d>.16B, V<n>.8H, V<m>.8H

Floating-point adjust exponent by vector:
-----------------------------------------

  - fscale V<d>.4H, V<n>.4H, V<m>.4H
  - fscale V<d>.8H, V<n>.8H, V<m>.8H
  - fscale V<d>.2S, V<n>.2S, V<m>.2S
  - fscale V<d>.4S, V<n>.4S, V<m>.4S
  - fscale V<d>.2d, V<n>.2d, V<m>.2d

5 files changed, 581 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
new file mode 100644
index 0000000..aaf0096
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.5-a+fp8 -mno-verbose-error
+#error_output: advsimd-fp8-fail.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
new file mode 100644
index 0000000..eea5a0b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.l
@@ -0,0 +1,262 @@
+[^:]+: Assembler messages:
+[^:]+:9: Error: operand mismatch -- `bf1cvtl v0.16b,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `bf1cvtl v0.8b,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf1cvtl v0.4h,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf1cvtl v0.2s,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf1cvtl v0.4s,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `bf1cvtl v0.2d,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `bf1cvtl v0,v1.8b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `bf1cvtl v0.8h,v1.4h'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `bf1cvtl v0.8h,v1.2s'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `bf1cvtl v0.8h,v1.16b'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `bf1cvtl v0.8h,v1.8h'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `bf1cvtl v0.8h,v1.4s'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bf1cvtl v0.8h,v1.2d'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `bf1cvtl v0.8h,v0'
+[^:]+:27:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `bf2cvtl v0.16b,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `bf2cvtl v0.8b,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `bf2cvtl v0.4h,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `bf2cvtl v0.2s,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `bf2cvtl v0.4s,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `bf2cvtl v0.2d,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `bf2cvtl v0,v1.8b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `bf2cvtl v0.8h,v1.4h'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `bf2cvtl v0.8h,v1.2s'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `bf2cvtl v0.8h,v1.16b'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `bf2cvtl v0.8h,v1.8h'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `bf2cvtl v0.8h,v1.4s'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `bf2cvtl v0.8h,v1.2d'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `bf2cvtl v0.8h,v0'
+[^:]+:28:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f1cvtl v0.16b,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `f1cvtl v0.8b,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f1cvtl v0.4h,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f1cvtl v0.2s,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f1cvtl v0.4s,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `f1cvtl v0.2d,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `f1cvtl v0,v1.8b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `f1cvtl v0.8h,v1.4h'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `f1cvtl v0.8h,v1.2s'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `f1cvtl v0.8h,v1.16b'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `f1cvtl v0.8h,v1.8h'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `f1cvtl v0.8h,v1.4s'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `f1cvtl v0.8h,v1.2d'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `f1cvtl v0.8h,v0'
+[^:]+:29:  Info: macro invoked from here
+[^:]+:9: Error: operand mismatch -- `f2cvtl v0.16b,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:10: Error: operand mismatch -- `f2cvtl v0.8b,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:11: Error: operand mismatch -- `f2cvtl v0.4h,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:13: Error: operand mismatch -- `f2cvtl v0.2s,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:14: Error: operand mismatch -- `f2cvtl v0.4s,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:15: Error: operand mismatch -- `f2cvtl v0.2d,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:16: Error: invalid use of vector register at operand 1 -- `f2cvtl v0,v1.8b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:18: Error: operand mismatch -- `f2cvtl v0.8h,v1.4h'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:19: Error: operand mismatch -- `f2cvtl v0.8h,v1.2s'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:20: Error: operand mismatch -- `f2cvtl v0.8h,v1.16b'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:21: Error: operand mismatch -- `f2cvtl v0.8h,v1.8h'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:22: Error: operand mismatch -- `f2cvtl v0.8h,v1.4s'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:23: Error: operand mismatch -- `f2cvtl v0.8h,v1.2d'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:24: Error: invalid use of vector register at operand 2 -- `f2cvtl v0.8h,v0'
+[^:]+:30:  Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bf1cvtl2 v0.16b,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bf1cvtl2 v0.8b,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `bf1cvtl2 v0.4h,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `bf1cvtl2 v0.2s,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `bf1cvtl2 v0.4s,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `bf1cvtl2 v0.2d,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `bf1cvtl2 v0,v1.16b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.8b'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.4h'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.2s'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.8h'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.4s'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `bf1cvtl2 v0.8h,v1.2d'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `bf1cvtl2 v0.8h,v1'
+[^:]+:56:  Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `bf2cvtl2 v0.16b,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `bf2cvtl2 v0.8b,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `bf2cvtl2 v0.4h,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `bf2cvtl2 v0.2s,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `bf2cvtl2 v0.4s,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `bf2cvtl2 v0.2d,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `bf2cvtl2 v0,v1.16b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.8b'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.4h'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.2s'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.8h'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.4s'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `bf2cvtl2 v0.8h,v1.2d'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `bf2cvtl2 v0.8h,v1'
+[^:]+:57:  Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `f1cvtl2 v0.16b,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `f1cvtl2 v0.8b,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `f1cvtl2 v0.4h,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `f1cvtl2 v0.2s,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `f1cvtl2 v0.4s,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `f1cvtl2 v0.2d,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `f1cvtl2 v0,v1.16b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.8b'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.4h'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.2s'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.8h'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.4s'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `f1cvtl2 v0.8h,v1.2d'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `f1cvtl2 v0.8h,v1'
+[^:]+:58:  Info: macro invoked from here
+[^:]+:37: Error: operand mismatch -- `f2cvtl2 v0.16b,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:38: Error: operand mismatch -- `f2cvtl2 v0.8b,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:39: Error: operand mismatch -- `f2cvtl2 v0.4h,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:41: Error: operand mismatch -- `f2cvtl2 v0.2s,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:42: Error: operand mismatch -- `f2cvtl2 v0.4s,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:43: Error: operand mismatch -- `f2cvtl2 v0.2d,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:44: Error: invalid use of vector register at operand 1 -- `f2cvtl2 v0,v1.16b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:46: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.8b'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:47: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.4h'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:48: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.2s'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:50: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.8h'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:51: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.4s'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:52: Error: operand mismatch -- `f2cvtl2 v0.8h,v1.2d'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:53: Error: invalid use of vector register at operand 2 -- `f2cvtl2 v0.8h,v1'
+[^:]+:59:  Info: macro invoked from here
+[^:]+:64: Error: operand mismatch -- `fscale v0.8b,v0.8b,v0.8b'
+[^:]+:65: Error: operand mismatch -- `fscale v0.16b,v0.16b,v0.16b'
+[^:]+:72: Error: operand mismatch -- `fcvtn v0.4h,v1.4h,v2.4h'
+[^:]+:73: Error: operand mismatch -- `fcvtn v0.2s,v1.4h,v2.4h'
+[^:]+:74: Error: operand mismatch -- `fcvtn v0.16b,v1.4h,v2.4h'
+[^:]+:75: Error: operand mismatch -- `fcvtn v0.8h,v1.4h,v2.4h'
+[^:]+:76: Error: operand mismatch -- `fcvtn v0.4s,v1.4h,v2.4h'
+[^:]+:77: Error: operand mismatch -- `fcvtn v0.2d,v1.4h,v2.4h'
+[^:]+:79: Error: operand mismatch -- `fcvtn v0.8b,v1.8h,v2.8h'
+[^:]+:80: Error: operand mismatch -- `fcvtn v0.4h,v1.8h,v2.8h'
+[^:]+:81: Error: operand mismatch -- `fcvtn v0.2s,v1.8h,v2.8h'
+[^:]+:83: Error: operand mismatch -- `fcvtn v0.8h,v1.8h,v2.8h'
+[^:]+:84: Error: operand mismatch -- `fcvtn v0.4s,v1.8h,v2.8h'
+[^:]+:85: Error: operand mismatch -- `fcvtn v0.2d,v1.8h,v2.8h'
+[^:]+:88: Error: operand mismatch -- `fcvtn v0.8b,v1.8b,v2.8b'
+[^:]+:90: Error: operand mismatch -- `fcvtn v0.8b,v1.2s,v2.2s'
+[^:]+:91: Error: operand mismatch -- `fcvtn v0.8b,v1.16b,v2.16b'
+[^:]+:92: Error: operand mismatch -- `fcvtn v0.8b,v1.8h,v2.8h'
+[^:]+:94: Error: operand mismatch -- `fcvtn v0.8b,v1.2d,v2.2d'
+[^:]+:96: Error: operand mismatch -- `fcvtn v0.16b,v1.8b,v2.8b'
+[^:]+:97: Error: operand mismatch -- `fcvtn v0.16b,v1.4h,v2.4h'
+[^:]+:98: Error: operand mismatch -- `fcvtn v0.16b,v1.2s,v2.2s'
+[^:]+:99: Error: operand mismatch -- `fcvtn v0.16b,v1.16b,v2.16b'
+[^:]+:101: Error: operand mismatch -- `fcvtn v0.16b,v1.4s,v2.4s'
+[^:]+:102: Error: operand mismatch -- `fcvtn v0.16b,v1.2d,v2.2d'
+[^:]+:107: Error: operand mismatch -- `fcvtn v0.4h,v1.4s,v2.4s'
+[^:]+:108: Error: operand mismatch -- `fcvtn v0.2s,v1.4s,v2.4s'
+[^:]+:109: Error: operand mismatch -- `fcvtn v0.16b,v1.4s,v2.4s'
+[^:]+:110: Error: operand mismatch -- `fcvtn v0.8h,v1.4s,v2.4s'
+[^:]+:111: Error: operand mismatch -- `fcvtn v0.4s,v1.4s,v2.4s'
+[^:]+:112: Error: operand mismatch -- `fcvtn v0.2d,v1.4s,v2.4s'
+[^:]+:115: Error: operand mismatch -- `fcvtn2 v0.16b,v1.8b,v2.8b'
+[^:]+:116: Error: operand mismatch -- `fcvtn2 v0.16b,v1.4h,v2.4h'
+[^:]+:117: Error: operand mismatch -- `fcvtn2 v0.16b,v1.2d,v2.2d'
+[^:]+:118: Error: operand mismatch -- `fcvtn2 v0.16b,v1.16b,v2.16b'
+[^:]+:119: Error: operand mismatch -- `fcvtn2 v0.16b,v1.8h,v2.8h'
+[^:]+:121: Error: operand mismatch -- `fcvtn2 v0.16b,v1.2d,v2.2d'
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
new file mode 100644
index 0000000..71ebf3c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8-fail.s
@@ -0,0 +1,121 @@
+	/* advsimd-fp8-fail.s Test file for error-checking AArch64 8-bit
+	floating-point vector instructions.  */
+
+	/* Instructions convert the elements from the lower half of the source
+	vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]).  */
+
+	.macro cvrt_lowerhalf, op
+	/* Check the number and width of destination vector elements.  */
+	\op	v0.16b, v1.8b
+	\op	v0.8b, v1.8b
+	\op	v0.4h, v1.8b
+	\op	v0.8h, v1.8b /* Valid.  */
+	\op 	v0.2s, v1.8b
+	\op 	v0.4s, v1.8b
+	\op 	v0.2d, v1.8b
+	\op 	v0, v1.8b
+	/* Check the number and width of source vector elements.  */
+	\op 	v0.8h, v1.4h
+	\op 	v0.8h, v1.2s
+	\op 	v0.8h, v1.16b
+	\op 	v0.8h, v1.8h
+	\op 	v0.8h, v1.4s
+	\op 	v0.8h, v1.2d
+	\op 	v0.8h, v0
+	.endm
+
+	cvrt_lowerhalf	bf1cvtl
+	cvrt_lowerhalf	bf2cvtl
+	cvrt_lowerhalf	f1cvtl
+	cvrt_lowerhalf	f2cvtl
+
+	/* Instructions convert the elements from the upper half of the source
+	vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]).  */
+
+	.macro cvrt_upperhalf, op
+	/* Check the number and width of destination vector elements.  */
+	\op	v0.16b, v1.16b
+	\op	v0.8b, v1.16b
+	\op	v0.4h, v1.16b
+	\op	v0.8h, v1.16b /* Valid.  */
+	\op 	v0.2s, v1.16b
+	\op 	v0.4s, v1.16b
+	\op 	v0.2d, v1.16b
+	\op 	v0, v1.16b
+	/* Check the number and width of source vector elements.  */
+	\op 	v0.8h, v1.8b
+	\op 	v0.8h, v1.4h
+	\op 	v0.8h, v1.2s
+	\op 	v0.8h, v1.16b /* Valid.  */
+	\op 	v0.8h, v1.8h
+	\op 	v0.8h, v1.4s
+	\op 	v0.8h, v1.2d
+	\op 	v0.8h, v1
+	.endm
+
+	cvrt_upperhalf	bf1cvtl2
+	cvrt_upperhalf	bf2cvtl2
+	cvrt_upperhalf	f1cvtl2
+	cvrt_upperhalf	f2cvtl2
+
+	/* Floating-point adjust exponent by vector.  */
+
+	/* Check invalid vector element number and width combinations.  */
+	fscale	v0.8b, v0.8b, v0.8b
+	fscale	v0.16b, v0.16b, v0.16b
+
+	/* Half and single-precision to FP8 convert and narrow.  */
+
+	/* Half-precision variant.  */
+	/* Check the number and width of destination vector elements.  */
+	fcvtn	v0.8b, v1.4h, v2.4h /* Valid.  */
+	fcvtn	v0.4h, v1.4h, v2.4h
+	fcvtn	v0.2s, v1.4h, v2.4h
+	fcvtn	v0.16b, v1.4h, v2.4h
+	fcvtn	v0.8h, v1.4h, v2.4h
+	fcvtn	v0.4s, v1.4h, v2.4h
+	fcvtn	v0.2d, v1.4h, v2.4h
+
+	fcvtn	v0.8b, v1.8h, v2.8h
+	fcvtn	v0.4h, v1.8h, v2.8h
+	fcvtn	v0.2s, v1.8h, v2.8h
+	fcvtn	v0.16b, v1.8h, v2.8h /* Valid.  */
+	fcvtn	v0.8h, v1.8h, v2.8h
+	fcvtn	v0.4s, v1.8h, v2.8h
+	fcvtn	v0.2d, v1.8h, v2.8h
+
+	/* Check the number and width of source vector elements.  */
+	fcvtn	v0.8b, v1.8b, v2.8b
+	fcvtn	v0.8b, v1.4h, v2.4h /* Valid.  */
+	fcvtn	v0.8b, v1.2s, v2.2s
+	fcvtn	v0.8b, v1.16b, v2.16b
+	fcvtn	v0.8b, v1.8h, v2.8h
+	fcvtn	v0.8b, v1.4s, v2.4s /* Valid.  */
+	fcvtn	v0.8b, v1.2d, v2.2d
+
+	fcvtn	v0.16b, v1.8b, v2.8b
+	fcvtn	v0.16b, v1.4h, v2.4h
+	fcvtn	v0.16b, v1.2s, v2.2s
+	fcvtn	v0.16b, v1.16b, v2.16b
+	fcvtn	v0.16b, v1.8h, v2.8h  /* Valid.  */
+	fcvtn	v0.16b, v1.4s, v2.4s
+	fcvtn	v0.16b, v1.2d, v2.2d
+
+	/* Single-precision variant.  */
+	/* Check the number and width of destination vector elements.  */
+	fcvtn	v0.8b, v1.4s, v2.4s /* Valid.  */
+	fcvtn	v0.4h, v1.4s, v2.4s
+	fcvtn	v0.2s, v1.4s, v2.4s
+	fcvtn	v0.16b, v1.4s, v2.4s
+	fcvtn	v0.8h, v1.4s, v2.4s
+	fcvtn	v0.4s, v1.4s, v2.4s
+	fcvtn	v0.2d, v1.4s, v2.4s
+
+	/* Check the number and width of source vector elements.  */
+	fcvtn2	v0.16b, v1.8b, v2.8b
+	fcvtn2	v0.16b, v1.4h, v2.4h
+	fcvtn2	v0.16b, v1.2d, v2.2d
+	fcvtn2	v0.16b, v1.16b, v2.16b
+	fcvtn2	v0.16b, v1.8h, v2.8h
+	fcvtn2	v0.16b, v1.4s, v2.4s  /* Valid.  */
+	fcvtn2	v0.16b, v1.2d, v2.2d
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8.d b/gas/testsuite/gas/aarch64/advsimd-fp8.d
new file mode 100644
index 0000000..b4592a7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8.d
@@ -0,0 +1,120 @@
+#as: -march=armv8.5-a+fp8
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[ ]*[0-9a-f]+:	2ea17800 	bf1cvtl	v0.8h, v0.8b
+[ ]*[0-9a-f]+:	2ea17801 	bf1cvtl	v1.8h, v0.8b
+[ ]*[0-9a-f]+:	2ea17820 	bf1cvtl	v0.8h, v1.8b
+[ ]*[0-9a-f]+:	2ea17821 	bf1cvtl	v1.8h, v1.8b
+[ ]*[0-9a-f]+:	2ea17a30 	bf1cvtl	v16.8h, v17.8b
+[ ]*[0-9a-f]+:	2ee17800 	bf2cvtl	v0.8h, v0.8b
+[ ]*[0-9a-f]+:	2ee17801 	bf2cvtl	v1.8h, v0.8b
+[ ]*[0-9a-f]+:	2ee17820 	bf2cvtl	v0.8h, v1.8b
+[ ]*[0-9a-f]+:	2ee17821 	bf2cvtl	v1.8h, v1.8b
+[ ]*[0-9a-f]+:	2ee17a30 	bf2cvtl	v16.8h, v17.8b
+[ ]*[0-9a-f]+:	2e217800 	f1cvtl	v0.8h, v0.8b
+[ ]*[0-9a-f]+:	2e217801 	f1cvtl	v1.8h, v0.8b
+[ ]*[0-9a-f]+:	2e217820 	f1cvtl	v0.8h, v1.8b
+[ ]*[0-9a-f]+:	2e217821 	f1cvtl	v1.8h, v1.8b
+[ ]*[0-9a-f]+:	2e217a30 	f1cvtl	v16.8h, v17.8b
+[ ]*[0-9a-f]+:	2e617800 	f2cvtl	v0.8h, v0.8b
+[ ]*[0-9a-f]+:	2e617801 	f2cvtl	v1.8h, v0.8b
+[ ]*[0-9a-f]+:	2e617820 	f2cvtl	v0.8h, v1.8b
+[ ]*[0-9a-f]+:	2e617821 	f2cvtl	v1.8h, v1.8b
+[ ]*[0-9a-f]+:	2e617a30 	f2cvtl	v16.8h, v17.8b
+[ ]*[0-9a-f]+:	6ea17800 	bf1cvtl2	v0.8h, v0.16b
+[ ]*[0-9a-f]+:	6ea17801 	bf1cvtl2	v1.8h, v0.16b
+[ ]*[0-9a-f]+:	6ea17820 	bf1cvtl2	v0.8h, v1.16b
+[ ]*[0-9a-f]+:	6ea17821 	bf1cvtl2	v1.8h, v1.16b
+[ ]*[0-9a-f]+:	6ea17a30 	bf1cvtl2	v16.8h, v17.16b
+[ ]*[0-9a-f]+:	6ee17800 	bf2cvtl2	v0.8h, v0.16b
+[ ]*[0-9a-f]+:	6ee17801 	bf2cvtl2	v1.8h, v0.16b
+[ ]*[0-9a-f]+:	6ee17820 	bf2cvtl2	v0.8h, v1.16b
+[ ]*[0-9a-f]+:	6ee17821 	bf2cvtl2	v1.8h, v1.16b
+[ ]*[0-9a-f]+:	6ee17a30 	bf2cvtl2	v16.8h, v17.16b
+[ ]*[0-9a-f]+:	6e217800 	f1cvtl2	v0.8h, v0.16b
+[ ]*[0-9a-f]+:	6e217801 	f1cvtl2	v1.8h, v0.16b
+[ ]*[0-9a-f]+:	6e217820 	f1cvtl2	v0.8h, v1.16b
+[ ]*[0-9a-f]+:	6e217821 	f1cvtl2	v1.8h, v1.16b
+[ ]*[0-9a-f]+:	6e217a30 	f1cvtl2	v16.8h, v17.16b
+[ ]*[0-9a-f]+:	6e617800 	f2cvtl2	v0.8h, v0.16b
+[ ]*[0-9a-f]+:	6e617801 	f2cvtl2	v1.8h, v0.16b
+[ ]*[0-9a-f]+:	6e617820 	f2cvtl2	v0.8h, v1.16b
+[ ]*[0-9a-f]+:	6e617821 	f2cvtl2	v1.8h, v1.16b
+[ ]*[0-9a-f]+:	6e617a30 	f2cvtl2	v16.8h, v17.16b
+[ ]*[0-9a-f]+:	2ec03c00 	fscale	v0.4h, v0.4h, v0.4h
+[ ]*[0-9a-f]+:	2ec03c01 	fscale	v1.4h, v0.4h, v0.4h
+[ ]*[0-9a-f]+:	2ec03c20 	fscale	v0.4h, v1.4h, v0.4h
+[ ]*[0-9a-f]+:	2ec13c00 	fscale	v0.4h, v0.4h, v1.4h
+[ ]*[0-9a-f]+:	2ec03c21 	fscale	v1.4h, v1.4h, v0.4h
+[ ]*[0-9a-f]+:	2ec13c20 	fscale	v0.4h, v1.4h, v1.4h
+[ ]*[0-9a-f]+:	2ec13c21 	fscale	v1.4h, v1.4h, v1.4h
+[ ]*[0-9a-f]+:	2ed23e30 	fscale	v16.4h, v17.4h, v18.4h
+[ ]*[0-9a-f]+:	6ec03c00 	fscale	v0.8h, v0.8h, v0.8h
+[ ]*[0-9a-f]+:	6ec03c01 	fscale	v1.8h, v0.8h, v0.8h
+[ ]*[0-9a-f]+:	6ec03c20 	fscale	v0.8h, v1.8h, v0.8h
+[ ]*[0-9a-f]+:	6ec13c00 	fscale	v0.8h, v0.8h, v1.8h
+[ ]*[0-9a-f]+:	6ec03c21 	fscale	v1.8h, v1.8h, v0.8h
+[ ]*[0-9a-f]+:	6ec13c20 	fscale	v0.8h, v1.8h, v1.8h
+[ ]*[0-9a-f]+:	6ec13c21 	fscale	v1.8h, v1.8h, v1.8h
+[ ]*[0-9a-f]+:	6ed23e30 	fscale	v16.8h, v17.8h, v18.8h
+[ ]*[0-9a-f]+:	2ea0fc00 	fscale	v0.2s, v0.2s, v0.2s
+[ ]*[0-9a-f]+:	2ea0fc01 	fscale	v1.2s, v0.2s, v0.2s
+[ ]*[0-9a-f]+:	2ea0fc20 	fscale	v0.2s, v1.2s, v0.2s
+[ ]*[0-9a-f]+:	2ea1fc00 	fscale	v0.2s, v0.2s, v1.2s
+[ ]*[0-9a-f]+:	2ea0fc21 	fscale	v1.2s, v1.2s, v0.2s
+[ ]*[0-9a-f]+:	2ea1fc20 	fscale	v0.2s, v1.2s, v1.2s
+[ ]*[0-9a-f]+:	2ea1fc21 	fscale	v1.2s, v1.2s, v1.2s
+[ ]*[0-9a-f]+:	2eb2fe30 	fscale	v16.2s, v17.2s, v18.2s
+[ ]*[0-9a-f]+:	6ea0fc00 	fscale	v0.4s, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	6ea0fc01 	fscale	v1.4s, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	6ea0fc20 	fscale	v0.4s, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	6ea1fc00 	fscale	v0.4s, v0.4s, v1.4s
+[ ]*[0-9a-f]+:	6ea0fc21 	fscale	v1.4s, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	6ea1fc20 	fscale	v0.4s, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	6ea1fc21 	fscale	v1.4s, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	6eb2fe30 	fscale	v16.4s, v17.4s, v18.4s
+[ ]*[0-9a-f]+:	6ee0fc00 	fscale	v0.2d, v0.2d, v0.2d
+[ ]*[0-9a-f]+:	6ee0fc01 	fscale	v1.2d, v0.2d, v0.2d
+[ ]*[0-9a-f]+:	6ee0fc20 	fscale	v0.2d, v1.2d, v0.2d
+[ ]*[0-9a-f]+:	6ee1fc00 	fscale	v0.2d, v0.2d, v1.2d
+[ ]*[0-9a-f]+:	6ee0fc21 	fscale	v1.2d, v1.2d, v0.2d
+[ ]*[0-9a-f]+:	6ee1fc20 	fscale	v0.2d, v1.2d, v1.2d
+[ ]*[0-9a-f]+:	6ee1fc21 	fscale	v1.2d, v1.2d, v1.2d
+[ ]*[0-9a-f]+:	6ef2fe30 	fscale	v16.2d, v17.2d, v18.2d
+[ ]*[0-9a-f]+:	0e40f400 	fcvtn	v0.8b, v0.4h, v0.4h
+[ ]*[0-9a-f]+:	0e40f401 	fcvtn	v1.8b, v0.4h, v0.4h
+[ ]*[0-9a-f]+:	0e40f420 	fcvtn	v0.8b, v1.4h, v0.4h
+[ ]*[0-9a-f]+:	0e41f400 	fcvtn	v0.8b, v0.4h, v1.4h
+[ ]*[0-9a-f]+:	0e40f421 	fcvtn	v1.8b, v1.4h, v0.4h
+[ ]*[0-9a-f]+:	0e41f420 	fcvtn	v0.8b, v1.4h, v1.4h
+[ ]*[0-9a-f]+:	0e41f421 	fcvtn	v1.8b, v1.4h, v1.4h
+[ ]*[0-9a-f]+:	0e52f630 	fcvtn	v16.8b, v17.4h, v18.4h
+[ ]*[0-9a-f]+:	4e40f400 	fcvtn	v0.16b, v0.8h, v0.8h
+[ ]*[0-9a-f]+:	4e40f401 	fcvtn	v1.16b, v0.8h, v0.8h
+[ ]*[0-9a-f]+:	4e40f420 	fcvtn	v0.16b, v1.8h, v0.8h
+[ ]*[0-9a-f]+:	4e41f400 	fcvtn	v0.16b, v0.8h, v1.8h
+[ ]*[0-9a-f]+:	4e40f421 	fcvtn	v1.16b, v1.8h, v0.8h
+[ ]*[0-9a-f]+:	4e41f420 	fcvtn	v0.16b, v1.8h, v1.8h
+[ ]*[0-9a-f]+:	4e41f421 	fcvtn	v1.16b, v1.8h, v1.8h
+[ ]*[0-9a-f]+:	4e52f630 	fcvtn	v16.16b, v17.8h, v18.8h
+[ ]*[0-9a-f]+:	0e00f400 	fcvtn	v0.8b, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	0e00f401 	fcvtn	v1.8b, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	0e00f420 	fcvtn	v0.8b, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	0e01f400 	fcvtn	v0.8b, v0.4s, v1.4s
+[ ]*[0-9a-f]+:	0e00f421 	fcvtn	v1.8b, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	0e01f420 	fcvtn	v0.8b, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	0e01f421 	fcvtn	v1.8b, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	0e12f630 	fcvtn	v16.8b, v17.4s, v18.4s
+[ ]*[0-9a-f]+:	4e00f400 	fcvtn2	v0.16b, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	4e00f401 	fcvtn2	v1.16b, v0.4s, v0.4s
+[ ]*[0-9a-f]+:	4e00f420 	fcvtn2	v0.16b, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	4e01f400 	fcvtn2	v0.16b, v0.4s, v1.4s
+[ ]*[0-9a-f]+:	4e00f421 	fcvtn2	v1.16b, v1.4s, v0.4s
+[ ]*[0-9a-f]+:	4e01f420 	fcvtn2	v0.16b, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	4e01f421 	fcvtn2	v1.16b, v1.4s, v1.4s
+[ ]*[0-9a-f]+:	4e12f630 	fcvtn2	v16.16b, v17.4s, v18.4s
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp8.s b/gas/testsuite/gas/aarch64/advsimd-fp8.s
new file mode 100644
index 0000000..e49f38d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-fp8.s
@@ -0,0 +1,76 @@
+	/* advsimd-fp8.s Test file for AArch64 8-bit floating-point vector
+	instructions.  */
+
+	/* Instructions convert the elements from the lower half of the source
+	vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]).  */
+
+	.macro cvrt_lowerhalf, op
+	\op 	v0.8h, v0.8b
+	\op 	v1.8h, v0.8b
+	\op 	v0.8h, v1.8b
+	\op 	v1.8h, v1.8b
+	\op 	v16.8h, v17.8b
+	.endm
+
+	cvrt_lowerhalf	bf1cvtl
+	cvrt_lowerhalf	bf2cvtl
+	cvrt_lowerhalf	f1cvtl
+	cvrt_lowerhalf	f2cvtl
+
+	/* Instructions convert the elements from the upper half of the source
+	vector while scaling the values by 2^-UInt(FPMR.LSCALE{2}[3:0]).  */
+
+	.macro cvrt_upperhalf, op
+	\op 	v0.8h, v0.16b
+	\op 	v1.8h, v0.16b
+	\op 	v0.8h, v1.16b
+	\op 	v1.8h, v1.16b
+	\op 	v16.8h, v17.16b
+	.endm
+
+	cvrt_upperhalf	bf1cvtl2
+	cvrt_upperhalf	bf2cvtl2
+	cvrt_upperhalf	f1cvtl2
+	cvrt_upperhalf	f2cvtl2
+
+	/* Floating-point adjust exponent by vector.  */
+
+	.macro fscale_gen, op_var
+	fscale	v0.\op_var, v0.\op_var, v0.\op_var
+	fscale	v1.\op_var, v0.\op_var, v0.\op_var
+	fscale	v0.\op_var, v1.\op_var, v0.\op_var
+	fscale	v0.\op_var, v0.\op_var, v1.\op_var
+	fscale	v1.\op_var, v1.\op_var, v0.\op_var
+	fscale	v0.\op_var, v1.\op_var, v1.\op_var
+	fscale	v1.\op_var, v1.\op_var, v1.\op_var
+	fscale	v16.\op_var, v17.\op_var, v18.\op_var
+	.endm
+
+	/* Half-precision variant.  */
+	fscale_gen	4h
+	fscale_gen	8h
+	/* Single-precision variant.  */
+	fscale_gen	2s
+	fscale_gen	4s
+	fscale_gen	2d
+
+	/* Half and single-precision to FP8 convert and narrow.  */
+
+	.macro fcvtn_to_fp8, op, sd, ss
+	\op	v0.\sd, v0.\ss, v0.\ss
+	\op	v1.\sd, v0.\ss, v0.\ss
+	\op	v0.\sd, v1.\ss, v0.\ss
+	\op	v0.\sd, v0.\ss, v1.\ss
+	\op	v1.\sd, v1.\ss, v0.\ss
+	\op	v0.\sd, v1.\ss, v1.\ss
+	\op	v1.\sd, v1.\ss, v1.\ss
+	\op	v16.\sd, v17.\ss, v18.\ss
+	.endm
+
+	/* Half-precision variant.  */
+	fcvtn_to_fp8 fcvtn 8b, 4h
+	fcvtn_to_fp8 fcvtn 16b, 8h
+
+	/* Single-precision variant.  */
+	fcvtn_to_fp8 fcvtn, 8b, 4s
+	fcvtn_to_fp8 fcvtn2, 16b, 4s