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Only works against spike, where I've implemented some custom debug
registers to test against.
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* Debug: Actually use the --32 and --64 command line arguments
* debug: make XLEN mismatch message clearer
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Fixes #83.
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The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.
Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.
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Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.
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When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.
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Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
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I don't exactly understand why it has to be the way it is, but I just
want it to work.
Also fix a pylint complaint.
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files.
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Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.
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I'm using this for a target where misa is at an old address, to
set riscv use_compressed_breakpoints off
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Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.
Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.
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The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000.
Also a minor change to log file naming so that 'make all' works again.
I'll fix this better later.
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If we want we can start using print(), but if so let's consistently use
it instead of piecemeal. See also
https://stackoverflow.com/questions/28694380/pylint-says-unnecessary-parens-after-r-keyword
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(actually it just gets an exception anyway).
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The main change was to read misa before running any other test. If misa
indicates C is supported, then use compressed code. This required
changing some tests, mostly to ensure correct alignment. The single
step test also needs to know the correct addresses to step through in
compressed code.
Only print at most 1000 lines from each log file.
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Relying on something that the compiler automatically sets is apparently
not reliable.
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It's not Just Working, and none of the tests so far actually care.
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This took a lot of refactoring to make it look reasonable.
There isn't actually any functional OpenOCD test yet. But a dummy test
runs a command (and fails).
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