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| author | Tim Newsome <tim@sifive.com> | 2017-02-17 09:45:53 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-17 09:45:53 -0800 |
| commit | 7dfc16ad687186faa57368a251489e56b72b6f91 (patch) | |
| tree | 6eb2b57f12dafe2cb5bb08cd63801e295098ca1b /debug/targets.py | |
| parent | e9951fc39dff4f4030cdfaaf479b936ae37799e2 (diff) | |
| download | riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.zip riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.tar.gz riscv-tests-7dfc16ad687186faa57368a251489e56b72b6f91.tar.bz2 | |
Add HiFive1 target.
Diffstat (limited to 'debug/targets.py')
| -rw-r--r-- | debug/targets.py | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/debug/targets.py b/debug/targets.py index bcebc0b..52b623c 100644 --- a/debug/targets.py +++ b/debug/targets.py @@ -92,6 +92,10 @@ class FreedomE300Target(Target): instruction_hardware_breakpoint_count = 2 openocd_config = "targets/%s/openocd.cfg" % name +class HiFive1Target(FreedomE300Target): + name = "HiFive1" + openocd_config = "targets/%s/openocd.cfg" % name + class FreedomE300SimTarget(Target): name = "freedom-e300-sim" xlen = 32 @@ -130,7 +134,8 @@ targets = [ FreedomE300Target, FreedomU500Target, FreedomE300SimTarget, - FreedomU500SimTarget] + FreedomU500SimTarget, + HiFive1Target] def add_target_options(parser): group = parser.add_mutually_exclusive_group(required=True) |