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| author | Tim Newsome <tim@sifive.com> | 2018-02-19 13:31:40 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-03-01 15:19:25 -0800 |
| commit | fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5 (patch) | |
| tree | 14038bee96c5aa4351465fd54c44f0e2ebe069ba /debug/targets/RISC-V | |
| parent | 208298c733a0e5ba9e4f7f892123745bdc7156c1 (diff) | |
| download | riscv-tests-fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5.zip riscv-tests-fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5.tar.gz riscv-tests-fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5.tar.bz2 | |
Test debugging with/without a program buffer
Diffstat (limited to 'debug/targets/RISC-V')
| -rw-r--r-- | debug/targets/RISC-V/spike32-2-rtos.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike32-2.py | 2 | ||||
| -rw-r--r-- | debug/targets/RISC-V/spike64.py | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index a7b9a1c..79105d5 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self) + return testlib.Spike(self, progbufsize=0) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index f57f816..89d3c2a 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self, isa="RV32IMAFC") + return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 2aa1dd0..d5802b5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -16,4 +16,4 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only - return testlib.Spike(self, isa="RV64IMAFC") + return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0) |