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-rw-r--r--debug/targets/RISC-V/spike32-2-rtos.py2
-rw-r--r--debug/targets/RISC-V/spike32-2.py2
-rw-r--r--debug/targets/RISC-V/spike64.py2
3 files changed, 3 insertions, 3 deletions
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index a7b9a1c..79105d5 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
timeout_sec = 30
def create(self):
- return testlib.Spike(self)
+ return testlib.Spike(self, progbufsize=0)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index f57f816..89d3c2a 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
timeout_sec = 30
def create(self):
- return testlib.Spike(self, isa="RV32IMAFC")
+ return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0)
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 2aa1dd0..d5802b5 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -16,4 +16,4 @@ class spike64(targets.Target):
def create(self):
# 32-bit FPRs only
- return testlib.Spike(self, isa="RV64IMAFC")
+ return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0)