From fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Mon, 19 Feb 2018 13:31:40 -0800 Subject: Test debugging with/without a program buffer --- debug/targets/RISC-V/spike32-2-rtos.py | 2 +- debug/targets/RISC-V/spike32-2.py | 2 +- debug/targets/RISC-V/spike64.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'debug/targets/RISC-V') diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py index a7b9a1c..79105d5 100644 --- a/debug/targets/RISC-V/spike32-2-rtos.py +++ b/debug/targets/RISC-V/spike32-2-rtos.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self) + return testlib.Spike(self, progbufsize=0) diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py index f57f816..89d3c2a 100644 --- a/debug/targets/RISC-V/spike32-2.py +++ b/debug/targets/RISC-V/spike32-2.py @@ -9,4 +9,4 @@ class spike32_2(targets.Target): timeout_sec = 30 def create(self): - return testlib.Spike(self, isa="RV32IMAFC") + return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0) diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py index 2aa1dd0..d5802b5 100644 --- a/debug/targets/RISC-V/spike64.py +++ b/debug/targets/RISC-V/spike64.py @@ -16,4 +16,4 @@ class spike64(targets.Target): def create(self): # 32-bit FPRs only - return testlib.Spike(self, isa="RV64IMAFC") + return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0) -- cgit v1.1