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path: root/debug/targets/RISC-V
AgeCommit message (Expand)AuthorFilesLines
2024-06-27Change DTM IDCODE from SiFive HiFive1's 0x10e31913 to Spike's 0xdeadbeef (#565)Tommy Murphy4-5/+5
2024-05-01[debug tests] increase remotetimeout for all spike-based targets (#553)Anatoly Parshintsev8-10/+8
2023-07-17debug: Add support_unavailable_control property.Tim Newsome7-0/+7
2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome4-21/+21
2022-10-24Increase timeouts for multi-spike test. (#423)Tim Newsome1-2/+1
2022-10-21Change memory address used in debug tests. (#422)Tim Newsome2-2/+2
2022-10-12Get coverage of progbuf FPR accesses.Tim Newsome2-2/+4
2022-05-31Address pylint warnings. (#385)Tim Newsome6-13/+13
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
2021-10-05Remove slen. (#360)Tim Newsome3-18/+14
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome3-22/+9
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome4-2/+89
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome3-4/+9
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome1-29/+0
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome1-20/+0
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome2-0/+2
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome6-0/+6
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
2020-08-06Add enable_rtos_riscv (#288)Tim Newsome1-0/+2
2020-06-25Add manual hwbp test. (#283)Tim Newsome2-0/+2
2020-05-26Test semihosting calls (#280)Tim Newsome5-5/+14
2020-04-10Change slen to a value that spike supports. (#271)Tim Newsome1-1/+3
2020-02-14Add tests for vector register access (#244)Tim Newsome3-10/+13
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome8-7/+19
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-1/+3
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome1-0/+2
2019-05-16Cover with/without halt groups. (#191)Tim Newsome4-5/+6
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome3-0/+3
2018-03-27Test debug authentication.Tim Newsome3-3/+18
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome3-0/+12
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
2017-08-28Make pylint happy.Tim Newsome2-2/+2
2017-08-28WIP multicore testing.Tim Newsome2-0/+4
2017-08-28Make the debug tests aware of multicore.Tim Newsome6-25/+35
2017-06-26Move target definition into individual files.Tim Newsome6-0/+132
generated by cgit v1.1 at 2024-07-16 08:10:24 +0000