| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2024-06-11 | Separate RV32 and RV64 C instructions into separate files | Andrew Waterman | 1 | -9/+3 | |
| 2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 1 | -2/+2 | |
| 2022-10-19 | Template-ize loads | Andrew Waterman | 1 | -2/+2 | |
| 2018-05-04 | Revert "C.LWSP and C.LDSP with rd=0 are legal instructions" | Andrew Waterman | 1 | -0/+1 | |
| See https://github.com/riscv/riscv-isa-manual/commit/01190b6ebeb29cfac6783a3e7ce30cd529bf6c59 | |||||
| 2018-05-03 | C.LWSP and C.LDSP with rd=0 are legal instructions | Andrew Waterman | 1 | -1/+0 | |
| This mistake derives from an ambiguity in the specification that has since been corrected: https://github.com/riscv/riscv-isa-manual/commit/272d038abebe7f006ed7960b522f1e51890bb982 | |||||
| 2017-04-10 | Implement new FP encoding | Andrew Waterman | 1 | -1/+1 | |
| https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ | |||||
| 2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 1 | -1/+1 | |
| 2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -0/+9 | |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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