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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-06-28 10:12:10 +0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-11-17 15:37:52 -0800 |
| commit | 0adf9307eaef62402c4368d33e88bbb5e1211653 (patch) | |
| tree | 10770c782ec98477ba0d083732bfa6855f9d22d0 /riscv/insns/c_flwsp.h | |
| parent | 251ecc9d1d5b31e4e964d0437271003533070c50 (diff) | |
| download | riscv-isa-sim-0adf9307eaef62402c4368d33e88bbb5e1211653.zip riscv-isa-sim-0adf9307eaef62402c4368d33e88bbb5e1211653.tar.gz riscv-isa-sim-0adf9307eaef62402c4368d33e88bbb5e1211653.tar.bz2 | |
add support for zca zcd and zcf
Diffstat (limited to 'riscv/insns/c_flwsp.h')
| -rw-r--r-- | riscv/insns/c_flwsp.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/c_flwsp.h b/riscv/insns/c_flwsp.h index a9a4b2c..eea0ec5 100644 --- a/riscv/insns/c_flwsp.h +++ b/riscv/insns/c_flwsp.h @@ -1,9 +1,9 @@ -require_extension('C'); if (xlen == 32) { - require_extension('F'); + require_extension(EXT_ZCF); require_fp; WRITE_FRD(f32(MMU.load<uint32_t>(RVC_SP + insn.rvc_lwsp_imm()))); } else { // c.ldsp + require_extension(EXT_ZCA); require(insn.rvc_rd() != 0); WRITE_RD(MMU.load<int64_t>(RVC_SP + insn.rvc_ldsp_imm())); } |