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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 19:59:42 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-24 18:40:56 -0800 |
| commit | 45b894876112a9f6ac5639bb6ee8427211df7280 (patch) | |
| tree | b082793598a1b957b177b48c4a29bcdf86db35e1 /riscv | |
| parent | 60428fcc44e0b2cf2932f3e0ce6a66d54755dab6 (diff) | |
| download | riscv-isa-sim-45b894876112a9f6ac5639bb6ee8427211df7280.zip riscv-isa-sim-45b894876112a9f6ac5639bb6ee8427211df7280.tar.gz riscv-isa-sim-45b894876112a9f6ac5639bb6ee8427211df7280.tar.bz2 | |
rvv: totally remove ediv
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 2 | ||||
| -rw-r--r-- | riscv/processor.h | 3 |
2 files changed, 1 insertions, 4 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e00bc85..07e6c62 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -393,11 +393,9 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vlmax = (VLEN/vsew) * vflmul; vta = extract64(newType, 6, 1); vma = extract64(newType, 7, 1); - vediv = 1 << extract64(newType, 8, 2); vill = !(vflmul >= 0.125 && vflmul <= 8) || vsew > std::min(vflmul, 1.0f) * ELEN - || vediv != 1 || (newType >> 8) != 0; if (vill) { diff --git a/riscv/processor.h b/riscv/processor.h index 7fb5103..09b24ac 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -244,7 +244,6 @@ typedef enum { typedef enum { // 65('A') ~ 90('Z') is reserved for standard isa in misa EXT_ZFH = 0, - EXT_ZVEDIV, } isa_extension_t; typedef enum { @@ -491,7 +490,7 @@ public: reg_t vlmax; reg_t vstart, vxrm, vxsat, vl, vtype, vlenb; reg_t vma, vta; - reg_t vediv, vsew; + reg_t vsew; float vflmul; reg_t ELEN, VLEN; bool vill; |