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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 09:01:30 -0800 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-24 18:40:55 -0800 |
commit | 60428fcc44e0b2cf2932f3e0ce6a66d54755dab6 (patch) | |
tree | f4e6f19ff9d9a6182f4211516580f392b487c457 /riscv | |
parent | 487f1b7cd8fc74e94ac76f8912ce8f3e335ba940 (diff) | |
download | riscv-isa-sim-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.zip riscv-isa-sim-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.tar.gz riscv-isa-sim-60428fcc44e0b2cf2932f3e0ce6a66d54755dab6.tar.bz2 |
rvv: add vse1/vle1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv')
-rw-r--r-- | riscv/decode.h | 24 | ||||
-rw-r--r-- | riscv/encoding.h | 6 | ||||
-rw-r--r-- | riscv/insns/vle16_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vle1_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vle32_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vle64_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vle8_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vlse16_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vlse32_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vlse64_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vlse8_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vse16_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vse1_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vse32_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vse64_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vse8_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsse16_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsse32_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsse64_v.h | 2 | ||||
-rw-r--r-- | riscv/insns/vsse8_v.h | 2 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 2 |
21 files changed, 40 insertions, 28 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index b7af775..465b816 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -531,18 +531,18 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) } \ } -#define VI_CHECK_STORE(elt_width) \ +#define VI_CHECK_STORE(elt_width, is_mask_ldst) \ require_vector(false); \ - reg_t veew = sizeof(elt_width##_t) * 8; \ - float vemul = ((float)veew / P.VU.vsew * P.VU.vflmul); \ + reg_t veew = is_mask_ldst ? 1 : sizeof(elt_width##_t) * 8; \ + float vemul = is_mask_ldst ? 1 : ((float)veew / P.VU.vsew * P.VU.vflmul); \ reg_t emul = vemul < 1 ? 1 : vemul; \ require(vemul >= 0.125 && vemul <= 8); \ require_align(insn.rd(), vemul); \ require((nf * emul) <= (NVPR / 4) && \ (insn.rd() + nf * emul) <= NVPR); \ -#define VI_CHECK_LOAD(elt_width) \ - VI_CHECK_STORE(elt_width); \ +#define VI_CHECK_LOAD(elt_width, is_mask_ldst) \ + VI_CHECK_STORE(elt_width, is_mask_ldst); \ require_vm; \ #define VI_CHECK_DSS(is_vs1) \ @@ -1606,12 +1606,12 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ } -#define VI_LD(stride, offset, elt_width) \ +#define VI_LD(stride, offset, elt_width, is_mask_ldst) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = P.VU.vl; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ - VI_CHECK_LOAD(elt_width); \ + VI_CHECK_LOAD(elt_width, is_mask_ldst); \ for (reg_t i = 0; i < vl; ++i) { \ VI_ELEMENT_SKIP(i); \ VI_STRIP(i); \ @@ -1660,12 +1660,12 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ P.VU.vstart = 0; -#define VI_ST(stride, offset, elt_width) \ +#define VI_ST(stride, offset, elt_width, is_mask_ldst) \ const reg_t nf = insn.v_nf() + 1; \ - const reg_t vl = P.VU.vl; \ + const reg_t vl = is_mask_ldst ? ((P.VU.vl + 7) / 8) : P.VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t vs3 = insn.rd(); \ - VI_CHECK_STORE(elt_width); \ + VI_CHECK_STORE(elt_width, is_mask_ldst); \ for (reg_t i = 0; i < vl; ++i) { \ VI_STRIP(i) \ VI_ELEMENT_SKIP(i); \ @@ -1720,7 +1720,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ const reg_t vl = p->VU.vl; \ const reg_t baseAddr = RS1; \ const reg_t rd_num = insn.rd(); \ - VI_CHECK_LOAD(elt_width); \ + VI_CHECK_LOAD(elt_width, false); \ bool early_stop = false; \ for (reg_t i = p->VU.vstart; i < vl; ++i) { \ VI_STRIP(i); \ diff --git a/riscv/encoding.h b/riscv/encoding.h index ccc8d74..ba5fa21 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -1226,6 +1226,10 @@ #define MASK_VSETVLI 0x8000707f #define MATCH_VSETVL 0x80007057 #define MASK_VSETVL 0xfe00707f +#define MATCH_VLE1_V 0x2b00007 +#define MASK_VLE1_V 0xfff0707f +#define MATCH_VSE1_V 0x2b00027 +#define MASK_VSE1_V 0xfff0707f #define MATCH_VLE8_V 0x7 #define MASK_VLE8_V 0x1df0707f #define MATCH_VLE16_V 0x5007 @@ -2889,6 +2893,8 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) DECLARE_INSN(vsetvli, MATCH_VSETVLI, MASK_VSETVLI) DECLARE_INSN(vsetvl, MATCH_VSETVL, MASK_VSETVL) +DECLARE_INSN(vle1_v, MATCH_VLE1_V, MASK_VLE1_V) +DECLARE_INSN(vse1_v, MATCH_VSE1_V, MASK_VSE1_V) DECLARE_INSN(vle8_v, MATCH_VLE8_V, MASK_VLE8_V) DECLARE_INSN(vle16_v, MATCH_VLE16_V, MASK_VLE16_V) DECLARE_INSN(vle32_v, MATCH_VLE32_V, MASK_VLE32_V) diff --git a/riscv/insns/vle16_v.h b/riscv/insns/vle16_v.h index 7bd2e83..70bf39f 100644 --- a/riscv/insns/vle16_v.h +++ b/riscv/insns/vle16_v.h @@ -1,2 +1,2 @@ // vle16.v and vlseg[2-8]e16.v -VI_LD(0, (i * nf + fn), int16); +VI_LD(0, (i * nf + fn), int16, false); diff --git a/riscv/insns/vle1_v.h b/riscv/insns/vle1_v.h new file mode 100644 index 0000000..6d3f83a --- /dev/null +++ b/riscv/insns/vle1_v.h @@ -0,0 +1,2 @@ +// vle1.v and vlseg[2-8]e8.v +VI_LD(0, (i * nf + fn), int8, true); diff --git a/riscv/insns/vle32_v.h b/riscv/insns/vle32_v.h index 9399fd6..f1d0e73 100644 --- a/riscv/insns/vle32_v.h +++ b/riscv/insns/vle32_v.h @@ -1,2 +1,2 @@ // vle32.v and vlseg[2-8]e32.v -VI_LD(0, (i * nf + fn), int32); +VI_LD(0, (i * nf + fn), int32, false); diff --git a/riscv/insns/vle64_v.h b/riscv/insns/vle64_v.h index 3f2654d..86deb5c 100644 --- a/riscv/insns/vle64_v.h +++ b/riscv/insns/vle64_v.h @@ -1,2 +1,2 @@ // vle64.v and vlseg[2-8]e64.v -VI_LD(0, (i * nf + fn), int64); +VI_LD(0, (i * nf + fn), int64, false); diff --git a/riscv/insns/vle8_v.h b/riscv/insns/vle8_v.h index 5613a1d..ffe17c3 100644 --- a/riscv/insns/vle8_v.h +++ b/riscv/insns/vle8_v.h @@ -1,2 +1,2 @@ // vle8.v and vlseg[2-8]e8.v -VI_LD(0, (i * nf + fn), int8); +VI_LD(0, (i * nf + fn), int8, false); diff --git a/riscv/insns/vlse16_v.h b/riscv/insns/vlse16_v.h index 7622ded..5ac23a9 100644 --- a/riscv/insns/vlse16_v.h +++ b/riscv/insns/vlse16_v.h @@ -1,2 +1,2 @@ // vlse16.v and vlsseg[2-8]e16.v -VI_LD(i * RS2, fn, int16); +VI_LD(i * RS2, fn, int16, false); diff --git a/riscv/insns/vlse32_v.h b/riscv/insns/vlse32_v.h index 1afc5e9..cfd74fb 100644 --- a/riscv/insns/vlse32_v.h +++ b/riscv/insns/vlse32_v.h @@ -1,2 +1,2 @@ // vlse32.v and vlsseg[2-8]e32.v -VI_LD(i * RS2, fn, int32); +VI_LD(i * RS2, fn, int32, false); diff --git a/riscv/insns/vlse64_v.h b/riscv/insns/vlse64_v.h index c6d9999..2e33963 100644 --- a/riscv/insns/vlse64_v.h +++ b/riscv/insns/vlse64_v.h @@ -1,2 +1,2 @@ // vlse64.v and vlsseg[2-8]e64.v -VI_LD(i * RS2, fn, int64); +VI_LD(i * RS2, fn, int64, false); diff --git a/riscv/insns/vlse8_v.h b/riscv/insns/vlse8_v.h index 021a1fb..275f022 100644 --- a/riscv/insns/vlse8_v.h +++ b/riscv/insns/vlse8_v.h @@ -1,2 +1,2 @@ // vlse8.v and vlsseg[2-8]e8.v -VI_LD(i * RS2, fn, int8); +VI_LD(i * RS2, fn, int8, false); diff --git a/riscv/insns/vse16_v.h b/riscv/insns/vse16_v.h index 20b04c8..9f9afec 100644 --- a/riscv/insns/vse16_v.h +++ b/riscv/insns/vse16_v.h @@ -1,2 +1,2 @@ // vse16.v and vsseg[2-8]e16.v -VI_ST(0, (i * nf + fn), uint16); +VI_ST(0, (i * nf + fn), uint16, false); diff --git a/riscv/insns/vse1_v.h b/riscv/insns/vse1_v.h new file mode 100644 index 0000000..e1d468b --- /dev/null +++ b/riscv/insns/vse1_v.h @@ -0,0 +1,2 @@ +// vse1.v +VI_ST(0, (i * nf + fn), uint8, true); diff --git a/riscv/insns/vse32_v.h b/riscv/insns/vse32_v.h index efd2973..1c6a231 100644 --- a/riscv/insns/vse32_v.h +++ b/riscv/insns/vse32_v.h @@ -1,2 +1,2 @@ // vse32.v and vsseg[2-8]e32.v -VI_ST(0, (i * nf + fn), uint32); +VI_ST(0, (i * nf + fn), uint32, false); diff --git a/riscv/insns/vse64_v.h b/riscv/insns/vse64_v.h index 9b36c8d..61d0ba6 100644 --- a/riscv/insns/vse64_v.h +++ b/riscv/insns/vse64_v.h @@ -1,2 +1,2 @@ // vse64.v and vsseg[2-8]e64.v -VI_ST(0, (i * nf + fn), uint64); +VI_ST(0, (i * nf + fn), uint64, false); diff --git a/riscv/insns/vse8_v.h b/riscv/insns/vse8_v.h index 32dee14..01f59ce 100644 --- a/riscv/insns/vse8_v.h +++ b/riscv/insns/vse8_v.h @@ -1,2 +1,2 @@ // vse8.v and vsseg[2-8]e8.v -VI_ST(0, (i * nf + fn), uint8); +VI_ST(0, (i * nf + fn), uint8, false); diff --git a/riscv/insns/vsse16_v.h b/riscv/insns/vsse16_v.h index adbbcf5..5dcbaf9 100644 --- a/riscv/insns/vsse16_v.h +++ b/riscv/insns/vsse16_v.h @@ -1,2 +1,2 @@ // vsse16v and vssseg[2-8]e16.v -VI_ST(i * RS2, fn, uint16); +VI_ST(i * RS2, fn, uint16, false); diff --git a/riscv/insns/vsse32_v.h b/riscv/insns/vsse32_v.h index 73bd272..80276b2 100644 --- a/riscv/insns/vsse32_v.h +++ b/riscv/insns/vsse32_v.h @@ -1,2 +1,2 @@ // vsse32.v and vssseg[2-8]e32.v -VI_ST(i * RS2, fn, uint32); +VI_ST(i * RS2, fn, uint32, false); diff --git a/riscv/insns/vsse64_v.h b/riscv/insns/vsse64_v.h index 1785a56..a4b6290 100644 --- a/riscv/insns/vsse64_v.h +++ b/riscv/insns/vsse64_v.h @@ -1,2 +1,2 @@ // vsse64.v and vssseg[2-8]e64.v -VI_ST(i * RS2, fn, uint64); +VI_ST(i * RS2, fn, uint64, false); diff --git a/riscv/insns/vsse8_v.h b/riscv/insns/vsse8_v.h index c5daf0b..5ba3cce 100644 --- a/riscv/insns/vsse8_v.h +++ b/riscv/insns/vsse8_v.h @@ -1,2 +1,2 @@ // vsse8.v and vssseg[2-8]e8.v -VI_ST(i * RS2, fn, uint8); +VI_ST(i * RS2, fn, uint8, false); diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 92a5c7c..0a25b0a 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -815,6 +815,7 @@ riscv_insn_ext_v_amo = \ vamoxorei64_v \ riscv_insn_ext_v_ldst = \ + vle1_v \ vle8_v \ vle16_v \ vle32_v \ @@ -851,6 +852,7 @@ riscv_insn_ext_v_ldst = \ vl2re64_v \ vl4re64_v \ vl8re64_v \ + vse1_v \ vse8_v \ vse16_v \ vse32_v \ |