Merge pull request #550 from chihminchao/rvv-pre-1.0-2020-09-22

Rvv pre 1.0 2020 09 22

18 files changed, 178 insertions, 19 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index ce5ee15..c1a6dbd 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -2330,7 +2330,9 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   for (reg_t i=P.VU.vstart; i<vl; ++i){ \
     VI_LOOP_ELEMENT_SKIP();
 
-#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, is_widen, eew_check) \
+#define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, \
+                         CHECK8, CHECK16, CHECK32, \
+                         is_widen, eew_check) \
   if (is_widen) { \
     VI_CHECK_DSS(false);\
   } else { \
@@ -2339,6 +2341,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   require(eew_check); \
   switch(P.VU.vsew) { \
     case e8: {\
+      CHECK8 \
       VI_VFP_LOOP_SCALE_BASE \
         BODY8 \
         set_fp_exceptions; \
@@ -2346,6 +2349,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
       } \
       break; \
     case e16: {\
+      CHECK16 \
       VI_VFP_LOOP_SCALE_BASE \
         BODY16 \
         set_fp_exceptions; \
@@ -2353,6 +2357,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
       } \
       break; \
     case e32: {\
+      CHECK32 \
       VI_VFP_LOOP_SCALE_BASE \
         BODY32 \
         set_fp_exceptions; \
diff --git a/riscv/insns/vfncvt_f_f_w.h b/riscv/insns/vfncvt_f_f_w.h
index 65af339..e9f3b25 100644
--- a/riscv/insns/vfncvt_f_f_w.h
+++ b/riscv/insns/vfncvt_f_f_w.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-}, false, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('D'));
+},
+false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_f_x_w.h b/riscv/insns/vfncvt_f_x_w.h
index 55163b3..556ee3c 100644
--- a/riscv/insns/vfncvt_f_x_w.h
+++ b/riscv/insns/vfncvt_f_x_w.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
-}, false, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_f_xu_w.h b/riscv/insns/vfncvt_f_xu_w.h
index 686b23f..0626ecb 100644
--- a/riscv/insns/vfncvt_f_xu_w.h
+++ b/riscv/insns/vfncvt_f_xu_w.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
-}, false, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_rod_f_f_w.h b/riscv/insns/vfncvt_rod_f_f_w.h
index 11d87e0..7113fd5 100644
--- a/riscv/insns/vfncvt_rod_f_f_w.h
+++ b/riscv/insns/vfncvt_rod_f_f_w.h
@@ -12,4 +12,14 @@ VI_VFP_CVT_SCALE
   softfloat_roundingMode = softfloat_round_odd;
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-}, false, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+false, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfncvt_rtz_x_f_w.h b/riscv/insns/vfncvt_rtz_x_f_w.h
index 7e4ec3a..1dfc6ec 100644
--- a/riscv/insns/vfncvt_rtz_x_f_w.h
+++ b/riscv/insns/vfncvt_rtz_x_f_w.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
-}, false, (P.VU.vsew <= 32))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_rtz_xu_f_w.h b/riscv/insns/vfncvt_rtz_xu_f_w.h
index e20ba0e..c6adcec 100644
--- a/riscv/insns/vfncvt_rtz_xu_f_w.h
+++ b/riscv/insns/vfncvt_rtz_xu_f_w.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, softfloat_round_minMag, true);
-}, false, (P.VU.vsew <= 32))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_x_f_w.h b/riscv/insns/vfncvt_x_f_w.h
index 2b1f012..01b52a2 100644
--- a/riscv/insns/vfncvt_x_f_w.h
+++ b/riscv/insns/vfncvt_x_f_w.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
-}, false, (P.VU.vsew <= 32))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfncvt_xu_f_w.h b/riscv/insns/vfncvt_xu_f_w.h
index bad09d8..bb55ec3 100644
--- a/riscv/insns/vfncvt_xu_f_w.h
+++ b/riscv/insns/vfncvt_xu_f_w.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
-}, false, (P.VU.vsew <= 32))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+false, (P.VU.vsew <= 32))
diff --git a/riscv/insns/vfwcvt_f_f_v.h b/riscv/insns/vfwcvt_f_f_v.h
index 2e92fef..9bf3f38 100644
--- a/riscv/insns/vfwcvt_f_f_v.h
+++ b/riscv/insns/vfwcvt_f_f_v.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
-}, true, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('D'));
+},
+true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_f_x_v.h b/riscv/insns/vfwcvt_f_x_v.h
index 4f0f4f4..481f371 100644
--- a/riscv/insns/vfwcvt_f_x_v.h
+++ b/riscv/insns/vfwcvt_f_x_v.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
-}, true, (P.VU.vsew >= 8))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+true, (P.VU.vsew >= 8))
diff --git a/riscv/insns/vfwcvt_f_xu_v.h b/riscv/insns/vfwcvt_f_xu_v.h
index b9fd0d8..544f33d 100644
--- a/riscv/insns/vfwcvt_f_xu_v.h
+++ b/riscv/insns/vfwcvt_f_xu_v.h
@@ -11,4 +11,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
-}, true, (P.VU.vsew >= 8))
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+{
+  require(p->supports_extension('D'));
+},
+true, (P.VU.vsew >= 8))
diff --git a/riscv/insns/vfwcvt_rtz_x_f_v.h b/riscv/insns/vfwcvt_rtz_x_f_v.h
index 62ecb51..7cbcf31 100644
--- a/riscv/insns/vfwcvt_rtz_x_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_x_f_v.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true);
-}, true, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_rtz_xu_f_v.h b/riscv/insns/vfwcvt_rtz_xu_f_v.h
index 69b70d4..81be047 100644
--- a/riscv/insns/vfwcvt_rtz_xu_f_v.h
+++ b/riscv/insns/vfwcvt_rtz_xu_f_v.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true);
-}, true, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_x_f_v.h b/riscv/insns/vfwcvt_x_f_v.h
index 6b266b2..ebd99c0 100644
--- a/riscv/insns/vfwcvt_x_f_v.h
+++ b/riscv/insns/vfwcvt_x_f_v.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
-}, true, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+true, (P.VU.vsew >= 16))
diff --git a/riscv/insns/vfwcvt_xu_f_v.h b/riscv/insns/vfwcvt_xu_f_v.h
index 2b535a9..55036f6 100644
--- a/riscv/insns/vfwcvt_xu_f_v.h
+++ b/riscv/insns/vfwcvt_xu_f_v.h
@@ -10,4 +10,14 @@ VI_VFP_CVT_SCALE
 {
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
-}, true, (P.VU.vsew >= 16))
+},
+{
+  ;
+},
+{
+  require(p->supports_extension(EXT_ZFH));
+},
+{
+  require(p->supports_extension('F'));
+},
+true, (P.VU.vsew >= 16))
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 00e91f9..05bfe87 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1299,7 +1299,7 @@ void processor_t::set_csr(int which, reg_t val)
 // Note that get_csr is sometimes called when read side-effects should not
 // be actioned.  In other words, Spike cannot currently support CSRs with
 // side effects on reads.
-reg_t processor_t::get_csr(int which, insn_t insn, bool write)
+reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek)
 {
   uint32_t ctr_en = -1;
   if (state.prv < PRV_M)
@@ -1643,6 +1643,10 @@ out:
   // Check permissions.  Raise virtual-instruction exception if V=1,
   // privileges are insufficient, and the CSR belongs to supervisor or
   // hypervisor.  Raise illegal-instruction exception otherwise.
+
+  if (peek)
+    return res;
+
   unsigned csr_priv = get_field(which, 0x300);
   bool csr_read_only = get_field(which, 0xC00) == 3;
   unsigned priv = state.prv == PRV_S && !state.v ? PRV_HS : state.prv;
diff --git a/riscv/processor.h b/riscv/processor.h
index 14ba843..169b43f 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -272,8 +272,8 @@ public:
   void reset();
   void step(size_t n); // run for n cycles
   void set_csr(int which, reg_t val);
-  reg_t get_csr(int which, insn_t insn, bool write);
-  reg_t get_csr(int which) { return get_csr(which, insn_t(0), false); }
+  reg_t get_csr(int which, insn_t insn, bool write, bool peek = 0);
+  reg_t get_csr(int which) { return get_csr(which, insn_t(0), false, true); }
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
   unsigned get_xlen() { return xlen; }