diff options
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 00e91f9..05bfe87 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1299,7 +1299,7 @@ void processor_t::set_csr(int which, reg_t val) // Note that get_csr is sometimes called when read side-effects should not // be actioned. In other words, Spike cannot currently support CSRs with // side effects on reads. -reg_t processor_t::get_csr(int which, insn_t insn, bool write) +reg_t processor_t::get_csr(int which, insn_t insn, bool write, bool peek) { uint32_t ctr_en = -1; if (state.prv < PRV_M) @@ -1643,6 +1643,10 @@ out: // Check permissions. Raise virtual-instruction exception if V=1, // privileges are insufficient, and the CSR belongs to supervisor or // hypervisor. Raise illegal-instruction exception otherwise. + + if (peek) + return res; + unsigned csr_priv = get_field(which, 0x300); bool csr_read_only = get_field(which, 0xC00) == 3; unsigned priv = state.prv == PRV_S && !state.v ? PRV_HS : state.prv; |