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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-03-05 14:23:20 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-05 14:23:20 -0800 |
| commit | 323a93e3e47e6a6474b4883bfa157245ecfd1411 (patch) | |
| tree | 92519af6cbc05a5412a57fc45b349288bc2cc0f8 /riscv | |
| parent | 0cd5a8bf3bdc13979a355e3d87e43a7697edb153 (diff) | |
| download | riscv-isa-sim-323a93e3e47e6a6474b4883bfa157245ecfd1411.zip riscv-isa-sim-323a93e3e47e6a6474b4883bfa157245ecfd1411.tar.gz riscv-isa-sim-323a93e3e47e6a6474b4883bfa157245ecfd1411.tar.bz2 | |
Fix hedeleg to match Privileged Spec requirements (#669)
Table 5.2 requires certain bits to be writable in hedeleg:
https://github.com/riscv/riscv-isa-manual/blob/0453d462a180927169656e6e3f7faf3042b23e5b/src/hypervisor.tex#L386-L409
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index aef212d..4af4384 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1147,6 +1147,8 @@ void processor_t::set_csr(int which, reg_t val) case CSR_HEDELEG: { reg_t mask = (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_FETCH_ACCESS) | + (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) | (1 << CAUSE_MISALIGNED_LOAD) | (1 << CAUSE_LOAD_ACCESS) | |