diff options
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index aef212d..4af4384 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1147,6 +1147,8 @@ void processor_t::set_csr(int which, reg_t val) case CSR_HEDELEG: { reg_t mask = (1 << CAUSE_MISALIGNED_FETCH) | + (1 << CAUSE_FETCH_ACCESS) | + (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) | (1 << CAUSE_MISALIGNED_LOAD) | (1 << CAUSE_LOAD_ACCESS) | |